Search results for "interconnect optimization"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Yici Cai, Yibo Wang, Xianlong Hong	A global interconnect optimization algorithm under accurate delay model using solution space smoothing.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Min Ma, Mourad Oulmane, Nicholas C. Rumin	Explicit delay metric for interconnect optimization.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Jason Cong, David Zhigang Pan, Prasanna V. Srinivas	Improved crosstalk modeling for noise constrained interconnect optimization.	ASP-DAC	2001	DBLP DOI BibTeX RDF
2	Minghorng Lai, D. F. Wong	Memory-efficient interconnect optimization.	ASP-DAC	2001	DBLP DOI BibTeX RDF
2	Christos A. Papachristou, Haluk Konuk	A Linear Program Driven Scheduling and Allocation Method Followed by an Interconnect Optimization Algorithm.	DAC	1990	DBLP DOI BibTeX RDF
1	Shoaib Kamil, Leonid Oliker, Ali Pinar, John Shalf	Communication Requirements and Interconnect Optimization for High-End Scientific Applications.	IEEE Trans. Parallel Distrib. Syst.	2010	DBLP DOI BibTeX RDF	performance analysis, topology, Interconnections
1	Shih-Lun Huang, Chung-Wei Lin, Yao-Wen Chang	Efficient provably good OPC modeling and its applications to interconnect optimization.	ICCD	2010	DBLP DOI BibTeX RDF
1	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Interconnect power and delay optimization by dynamic programming in gridded design rules.	ISPD	2010	DBLP DOI BibTeX RDF	gridded design rules, interconnect sizing and spacing, power-delay optimization, dynamic programming, interconnect optimization
1	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Power-delay optimization in VLSI microprocessors by wire spacing.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Wire spacing, power optimization, interconnect optimization, delay-optimization
1	Shiyan Hu, Zhuo Li, Charles J. Alpert	A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion.	DAC	2009	DBLP DOI BibTeX RDF	dynamic programming, NP-complete, buffer insertion, fully polynomial time approximation scheme, cost minimization
1	Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Diederik Verkest	Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor.	VLSI Design	2008	DBLP DOI BibTeX RDF	Interconnect-Aware Design, Low Power, Processor Architecture, Energy-Aware Design
1	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Timing-aware power-optimal ordering of signals.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Wire ordering, wire spacing, power optimization, interconnect optimization
1	Abinash Roy, Masud H. Chowdhury	Global Interconnect Optimization in the Presence of On-chip Inductance.	ISCAS	2007	DBLP DOI BibTeX RDF
1	David Bañeres, Jordi Cortadella, Michael Kishinevsky	Layout-aware gate duplication and buffer insertion.	DATE	2007	DBLP DOI BibTeX RDF
1	Chiu-Wing Sham, Evangeline F. Y. Young	Area reduction by deadspace utilization on interconnect optimized floorplan.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	area reduction, Floorplanning
1	Jarrod A. Roy, Igor L. Markov	ECO-system: Embracing the Change in Placement.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Jarrod A. Roy, Igor L. Markov	ECO-System: Embracing the Change in Placement.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou	Reliable crosstalk-driven interconnect optimization.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	post-layout optimization, VLSI, interconnect, lagrangian relaxation
1	J. Balachandran, Steven Brebels, Geert Carchon, Maarten Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne	Constant impedance scaling paradigm for interconnect synthesis.	SLIP	2006	DBLP DOI BibTeX RDF	transmission lines, interconnect optimization, global interconnects
1	Sean X. Shi, David Z. Pan	Wire sizing with scattering effect for nanoscale interconnection.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Min Tang, Jun-Fa Mao	Optimization of Global Interconnects in High Performance VLSI Circuits.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry	POMR: a power-aware interconnect optimization methodology.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Yibo Wang, Yici Cai, Xianlong Hong	A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model.	VLSI Design	2005	DBLP DOI BibTeX RDF	accurate delay model, obstacle-aware routing, buffer insertion, interconnect optimization
1	Hayward H. Chan, Saurabh N. Adya, Igor L. Markov	Are floorplan representations important in digital design?	ISPD	2005	DBLP DOI BibTeX RDF	B*-tree, floorplanning, sequence pair, circuit layout
1	Mariagrazia Graziano, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni	Effects of temperature in deep-submicron global interconnect optimization in future technology nodes.	Microelectronics Journal	2004	DBLP DOI BibTeX RDF
1	Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao	Simultaneous floor plan and buffer-block optimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Arif Ishaq Abou-Seido, Brian Nowak, Chris Chong-Nuen Chu	Fitted Elmore delay: a simple and accurate interconnect delay model.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Bao Liu	Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization.	ISVLSI	2003	DBLP DOI BibTeX RDF
1	Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni	Effects of Temperature in Deep-Submicron Global Interconnect Optimization.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Mohamed A. Elgamel, Kannan S. Tharmalingam, Magdy A. Bayoumi	Noise-constrained interconnect optimization for nanometer technologies.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu	A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees.	DATE	2003	DBLP DOI BibTeX RDF
1	Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham	Buffer insertion with adaptive blockage avoidance.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Jason Cong	Timing closure based on physical hierarchy.	ISPD	2002	DBLP DOI BibTeX RDF	interconnect planning, logic hierarchy, physical hierarchy, retiming and pipelining, sequential arrival time, interconnect optimization, timing closure, multilevel optimization
1	Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham	Buffer insertion with adaptive blockage avoidance.	ISPD	2002	DBLP DOI BibTeX RDF
1	Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao	Flip-Flop and Repeater Insertion for Early Interconnect Planning.	DATE	2002	DBLP DOI BibTeX RDF
1	Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Chu	Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model.	ICCD	2002	DBLP DOI BibTeX RDF
1	Chunhong Chen	Probabilistic Analysis of Rectilinear Steiner Trees.	VLSI Design	2002	DBLP DOI BibTeX RDF
1	Chunhong Chen, Jiang Zhao, Majid Ahmadi	Probability-based approach to rectilinear Steiner tree problems.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Tao Lin, Lawrence T. Pileggi	RC(L) interconnect sizing with second order considerations via posynomial programming.	ISPD	2001	DBLP DOI BibTeX RDF	RC trees, VLSI design automation, central moments, posynomiality, convex programming, interconnect optimization
1	Chris C. N. Chu, D. F. Wong	Closed form solutions to simultaneous buffer insertion/sizing and wire sizing.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	buffer insertion, buffer sizing, closed form solution, interconnect optimization, wire sizing
1	Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou	Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou	Optimal reliable crosstalk-driven interconnect optimization.	ISPD	2000	DBLP DOI BibTeX RDF
1	Cheng-Kok Koh, Patrick H. Madden	Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
1	Yanhong Yuan, Prithviraj Banerjee	A Parallel Implementation of a Fast Multipole Based 3-D Capacitance Extraction Program on Distributed Memory Multicomputer. (PDF / PS)	IPDPS	2000	DBLP DOI BibTeX RDF	fast multipole algorithm, parallel algorithms, distributed memory multiprocessors, Capacitance extraction
1	Sung-Woo Hur, Ashok Jagannathan, John Lillis	Timing-driven maze routing.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	Ananth Durbha, Srinivas Katkoori	RT-level Route-and-Place Design Methodology for Interconnect Optimization in DSM Regime.	VLSI	1999	DBLP BibTeX RDF
1	Andrew B. Kahng, Sudhakar Muddu, Egino Sarto	Interconnect Optimization Strategies for High-Performance VLSI Designs.	VLSI Design	1999	DBLP BibTeX RDF
1	Real G. Pomerleau, Paul D. Frazon, Griff L. Bilbro	Improved Selay Prediction for On-Chip Buses.	DAC	1999	DBLP DOI BibTeX RDF	RC wiring delay, buffer optimization, high-level synthesis, floorplanning, interconnect optimization
1	Abdel Ejnioui, N. Ranganathan	Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems.	FPGA	1999	DBLP DOI BibTeX RDF	layout synthesis, integer programming, FPGA architecture, interconnect optimization, branch-and-price, FPGA routing
1	Noel Menezes, Chung-Ping Chen	Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect.	VLSI Design	1999	DBLP DOI BibTeX RDF
1	Michael W. Beattie, Lawrence T. Pileggi	Error bounds for capacitance extraction via window techniques.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Jason Cong, Lei He	Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Jason Cong, Lei He	An efficient technique for device and interconnect optimization in deep submicron designs.	ISPD	1998	DBLP DOI BibTeX RDF
1	Chris C. N. Chu, D. F. Wong	A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing.	DATE	1998	DBLP DOI BibTeX RDF	Simultaneous buffer and wire sizing, buffer sizing, interconnect optimization, wire sizing
1	Jianhua Shao, Richard M. M. Chen	MCM Interconnect Design Using Two-Pole Approximation.	DATE	1998	DBLP DOI BibTeX RDF	Two-Pole Approximation, Interconnect Optimization, Interconnect Design
1	Gareth Keane, Jonathan Spanier, Roger Woods	The impact of data characteristics and hardware topology on hardware selection for low power DSP.	ISLPED	1998	DBLP DOI BibTeX RDF
1	Chris C. N. Chu, D. F. Wong	Greedy wire-sizing is linear time.	ISPD	1998	DBLP DOI BibTeX RDF
1	Daksh Lehther, Sachin S. Sapatnekar	Clock tree synthesis for multi-chip modules.	ICCAD	1996	DBLP DOI BibTeX RDF	Pade' approximants, Interconnect optimization
1	Takumi Okamoto, Jason Cong	Buffered Steiner tree construction with wire sizing for interconnect layout optimization.	ICCAD	1996	DBLP DOI BibTeX RDF	Steiner Tree, Buffer Insertion, Interconnect Optimization, Wire Sizing
1	Jason Cong, Lei He	Optimal wiresizing for interconnects with multiple sources.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	bundled refinement, decomposition of multi-source routing tree, dominance property, multi-source net, multi-source routing tree, optimal wiresizing, variable segment-division, high performance, SPICE, fidelity, interconnect optimization, Elmore delay, local refinement, layout optimization
1	Jason Cong, Lei He	Optimal wiresizing for interconnects with multiple sources.	ICCAD	1995	DBLP DOI BibTeX RDF	performance driven layout, optimal wiresizing, interconnect optimization, VLSI routing
1	Sachin S. Sapatnekar	RC Interconnect Optimization Under the Elmore Delay Model.	DAC	1994	DBLP DOI BibTeX RDF