Search results for "intra-chip "

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Md. Sajjad Rahaman, Masud H. Chowdhury	Improved ber performance in intra-chip rf/wireless interconnect systems.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	RF interconnect, intra-chip channel, wireless interconnect, interleaver, error control coding, channel coding
2	Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang, Ioannis Savidis, Manish Jain, Rebecca Berman, Peng Liu, Michael C. Huang, Hui Wu, Eby G. Friedman, Gary Wicks, Duncan Moore	An intra-chip free-space optical interconnect.	ISCA	2010	DBLP DOI BibTeX RDF	free-space optical interconnect, intra-chip, 3d
2	Md. Sajjad Rahaman, Masud H. Chowdhury	Time diversity approach for intra-chip RF/wireless interconnect systems.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Eli Yablonovitch	Can nano-photonic silicon circuits become an INTRA-chip interconnect technology?	ICCAD	2007	DBLP DOI BibTeX RDF
2	Tomoaki Hasegawa, Yuya Homma, Michitaka Kameyama	Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Md. Sajjad Rahaman, Masud H. Chowdhury	Energy efficiency of error control coding in intra-chip RF/wireless interconnect systems.	Microelectronics Journal	2010	DBLP DOI BibTeX RDF
1	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk	Wave-pipelined intra-chip signaling for on-FPGA communications.	Integration	2010	DBLP DOI BibTeX RDF
1	Ankit More, Baris Taskin	Leakage current analysis for intra-chip wireless interconnects.	ISQED	2010	DBLP DOI BibTeX RDF
1	Igor Loi, Pol Marchal, Antonio Pullini, Luca Benini	3D NoCs - Unifying inter & intra chip communication.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Pranay Koka, Michael O. McCracken, Herb Schwetman, Xuezhe Zheng, Ron Ho, Ashok V. Krishnamoorthy	Silicon-photonic network architectures for scalable, power-efficient multi-chip systems.	ISCA	2010	DBLP DOI BibTeX RDF	interconnection networks, nanophotonics
1	Phi-Hung Pham, Phuong Mau, Chulwoo Kim	A 64-PE folded-torus intra-chip communication fabric for guaranteed throughput in Network-on-Chip based applications.	CICC	2009	DBLP DOI BibTeX RDF
1	Yo Ohtake, Naoya Onizawa, Takahiro Hanyu	High-performance Asynchronous Intra-chip Communication Link based on a Multiple-valued Current-mode Single-track Scheme.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Shirish Bahirat, Sudeep Pasricha	Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	photonic interconnect, network-on-chip, chip multiprocessor
1	Hikmet Dursun, Ken-ichi Nomura, Liu Peng, Richard Seymour, Weiqiang Wang, Rajiv K. Kalia, Aiichiro Nakano, Priya Vashishta	A Multilevel Parallelization Framework for High-Order Stencil Computations.	Euro-Par	2009	DBLP DOI BibTeX RDF	single instruction multiple data parallelism, spatial decomposition, message passing, multithreading, Stencil computation
1	Claudio Favi, Edoardo Charbon	Techniques for fully integrated intra-/inter-chip optical communication.	DAC	2008	DBLP DOI BibTeX RDF	intra-chip & inter-chip communication, low power optical communication, miniaturized optical channel and detector
1	Richard H. Larson, John K. Salmon, Ron O. Dror, Martin M. Deneroff, Cliff Young, J. P. Grossman, Yibing Shan, John L. Klepeis, David E. Shaw	High-throughput pairwise point interactions in Anton, a specialized machine for molecular dynamics simulation.	HPCA	2008	DBLP DOI BibTeX RDF
1	Michele Petracca, Keren Bergman, Luca P. Carloni	Photonic networks-on-chip: Opportunities and challenges.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran	Fundamental Data Retention Limits in SRAM Standby Experimental Results.	ISQED	2008	DBLP DOI BibTeX RDF	standby, data retention, low power, SRAM, error control code
1	David E. Shaw	Architectures and algorithms for millisecond-scale molecular dynamics simulations of proteins.	MICRO	2008	DBLP DOI BibTeX RDF
1	Assaf Shacham, Keren Bergman, Luca P. Carloni	Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
1	Dan Zhao, Yi Wang	MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-Chip.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Cheng Wang, Ho-Seop Kim, Youfeng Wu, Victor Ying	Compiler-Managed Software-based Redundant Multi-Threading for Transient Fault Detection.	CGO	2007	DBLP DOI BibTeX RDF
1	Steve Pawlowski	Petascale Computing Research Challenges - A Manycore Perspective.	HPCA	2007	DBLP DOI BibTeX RDF
1	Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran	Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM.	ISCAS	2007	DBLP DOI BibTeX RDF
1	J. Balachandran, Steven Brebels, Geert Carchon, T. Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne	Analysis and modeling of power grid transmission lines.	DATE	2006	DBLP DOI BibTeX RDF
1	Louis Scheffer	An overview of on-chip interconnect variation.	SLIP	2006	DBLP DOI BibTeX RDF	causes of variability, on-chip variation, design rules
1	Chun-Lung Hsu, Chang-Hsin Cheng, Yu-Sheng Huang, Chih-Jung Chen	An Adaptive Low-Power Control Scheme for On-Chip Network Applications.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Min-An Song, Ting-Chun Huang, Sy-Yen Kuo	A Functional Verification Environment for Advanced Switching Architecture.	DELTA	2006	DBLP DOI BibTeX RDF
1	Stas Polonsky, M. Bhushan, A. Gattiker, Alan J. Weger, Peilin Song	Photon emission microscopy of inter/intra chip device performance variations.	Microelectronics Reliability	2005	DBLP DOI BibTeX RDF
1	Hongliang Chang, Sachin S. Sapatnekar	Full-chip analysis of leakage power under process variations, including spatial correlations.	DAC	2005	DBLP DOI BibTeX RDF
1	Salem Abdennadher, Saghir A. Shaikh	Challenges in High Speed Interface Testing.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi	VLSI architecture based on packet data transfer scheme and its application.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Y. P. Zhang	Bit-error-rate performance of intra-chip wireless interconnect systems.	IEEE Communications Letters	2004	DBLP DOI BibTeX RDF
1	Akira Mochizuki, Takashi Takeuchi, Takahiro Hanyu	Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding.	ISMVL	2004	DBLP DOI BibTeX RDF
1	Anand Pappu, Alyssa B. Apsel	Electrical isolation and fanout in intra-chip optical interconnects.	ISCAS	2004	DBLP BibTeX RDF
1	Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim	Profile-guided microarchitectural floorplanning for deep submicron processor design.	DAC	2004	DBLP DOI BibTeX RDF	microarchitectural planning, computer architecture, floorplanning
1	Ian O'Connor	Optical solutions for system-level interconnect.	SLIP	2004	DBLP DOI BibTeX RDF	interconnect technology, optical network on chip, optical interconnect
1	Aline Mello, Leandro Möller, Ney Calazans, Fernando Gehm Moraes	MultiNoC: A Multiprocessing System Enabled by a Network on Chip.	DATE	2004	DBLP DOI BibTeX RDF
1	Anand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu	Analytical Bound for Unwanted Clock Skew due to Wire Width Variation.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Dan Zhao, Shambhu J. Upadhyaya, Martin Margala	Control Constrained Resource Partitioning for Complex SoCs.	DFT	2003	DBLP DOI BibTeX RDF
1	Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera	Statistical modeling of gate-delay variation with consideration of intra-gate variability.	ISCAS	2003	DBLP DOI BibTeX RDF
1	George S. Almasi, Eduard Ayguadé, Calin Cascaval, José G. Castaños, Jesús Labarta, Francisco Martínez, Xavier Martorell, José E. Moreira	Evaluation of OpenMP for the Cyclops Multithreaded Architecture.	WOMPAT	2003	DBLP DOI BibTeX RDF
1	Louis Scheffer	Explicit computation of performance as a function of process variation.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	static timing, process variation, yield, statistical timing
1	Calin Cascaval, José G. Castaños, Luis Ceze, Monty Denneau, Manish Gupta, Derek Lieber, José E. Moreira, Karin Strauss, Henry S. Warren Jr.	Evaluation of a Multithreaded Architecture for Cellular Computing.	HPCA	2002	DBLP DOI BibTeX RDF
1	Yasushi Yuminaka, Tatsuya Morishita, Takafumi Aoki, Tatsuo Higuchi	Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI. (PDF / PS)	ISMVL	2002	DBLP DOI BibTeX RDF	new paradigm computing, high-speed signaling, code-division multiple access, equalization, VLSI systems
1	Paolo Ienne, Patrick Thiran, Giovanni De Micheli, Frederic Worm	An Adaptive Low-Power Transmission Scheme for On-Chip Networks.	ISSS	2002	DBLP DOI BibTeX RDF	low-power, systems-on-chip, networks-on-chip
1	Toshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto	CMOS Circuit Technology for Precise GHz Timing Generator.	ITC	2002	DBLP DOI BibTeX RDF
1	D. Miyawaki, Shizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Masami Suetake, Michiko Miura-Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama	Correlation method of circuit-performance and technology fluctuations for improved design reliability.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu	Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits.	ICCAD	2000	DBLP BibTeX RDF
1	Gregorio Cappuccino, Giuseppe Cocorullo	A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines.	EUROMICRO	1999	DBLP DOI BibTeX RDF
1	Stuart K. Tewksbury, Lawrence A. Hornak	Optical Clock Distribution in Electronic Systems.	VLSI Signal Processing	1997	DBLP DOI BibTeX RDF
1	Nobuyasu Kanekawa, Makoto Nohmi, Yoshimichi Satoh, Hiroshi Satoh	Self-Checking and Fail-Safe LSIs by Intra-Chip Redundancy.	FTCS	1996	DBLP DOI BibTeX RDF