Search results for "latch"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Martin Omaña, Daniele Rossi, Cecilia Metra	Latch Susceptibility to Transient Faults and New Hardening Approach.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Static Latch, Hardened Latch, Soft Errors, Transient Faults, Robust Design
4	Pong-Fei Lu, Nianzheng Cao, Leon J. Sigal, Pieter Woltgens, Raphael Robertazzi, David F. Heidel	A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors.	ISLPED	2006	DBLP DOI BibTeX RDF	pulse latch, low-power, latch
4	Kei-Yong Khoo, Alan N. Willson Jr.	Single-transistor transparent-latch clocking.	ARVLSI	1995	DBLP DOI BibTeX RDF	transparent-latch clocking, single-phase clocking scheme, CMOS VLSI designs, single NMOS transistor, allowable width, clock driver, dynamic buffer, architecture-driven voltage scaling, pipelining latches, latch-intensive architectures, filter structures, transposed-form FIR filter, VLSI, flip-flops, clocks, integrated circuit design, digital filters, FIR filters, power dissipation, CMOS digital integrated circuits
4	Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray	Concurrent timing optimization of latch-based digital systems. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	concurrent timing optimization, latch-based digital systems, digital system timing, intentional clock skew, latch-based designed systems, multi-phase clocking, resynchronization, latches insertion, optimisation, timing, logic design, flip-flops, retiming, mixed integer linear program, race conditions, integrated framework, wave pipelining, hazards and race conditions, clock period
3	Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang	Pulsed-latch aware placement for timing-integrity optimization.	DAC	2010	DBLP DOI BibTeX RDF	pulsed latch, placement, physical design
3	Martin Saint-Laurent, Baker Mohammad, Paul Bassett	A 65-nm pulsed latch with a single clocked transistor.	ISLPED	2007	DBLP DOI BibTeX RDF	low voltage swing, minimum clock power, pulsed latch, virtual-ground clocking
3	Amit M. Sheth, Jacob Savir	Scan Latch Design for Test Applications.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	shift register latch, scan design, hardware overhead, LSSD
3	Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz	An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists.	Formal Methods in System Design	2003	DBLP DOI BibTeX RDF	phase abstraction, automatic abstraction, CTL model checking, level-sensitive latch, bisimulation, model reduction
3	Kelvin Ng, Mukul R. Prasad, Rajarshi Mukherjee, Jawahar Jain	Solving the latch mapping problem in an industrial setting.	DAC	2003	DBLP DOI BibTeX RDF	latch mapping, combinational equivalence checking
3	Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai	Optimal time borrowing analysis and timing budgeting optimization for latch-based designs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	latch-based design, time borrowing, timing budgeting, static timing analysis, Cycle stealing
3	Victor V. Zyuban, Stephen V. Kosonocky	Low power integrated scan-retention mechanism.	ISLPED	2002	DBLP DOI BibTeX RDF	balloon latch, data retention, low power, scan, leakage, latch, MTCMOS, subthreshold
3	K. Wayne Current	Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch. (PDF / PS)	ISMVL	2000	DBLP DOI BibTeX RDF	quaternary, memory, circuit, latch
3	Jacob Savir	Reduced Latch Count Shift Registers.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	shift register latch, scan register, shifting clocks, STUMPS architecture, LSSD
3	Shaz Qadeer, Robert K. Brayton, Vigyan Singhal	Latch Redundancy Removal Without Global Reset. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	global reset assumption, latch redundancy, safe replacement, delayed replacement, Finite state machine, core, strongly connected components
3	Samy Makar, Edward J. McCluskey	Checking experiments to test latches.	VTS	1995	DBLP DOI BibTeX RDF	exhaustive functional tests, 2-state latches, minimum-length checking, D-latch, HSpice implementation, transmission gate latch, detectable shorted interconnects, open interconnects, short-to-power faults, short-to-ground faults, pin fault test set, multiplexer-based test set, sequential elements, 2-state state machines, simulation, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, CMOS, circuit analysis computing, CMOS logic circuits, SPICE, stuck open faults, checking experiments, stuck-on faults
3	Arthur F. Champernowne, Louis B. Bushard, John T. Rusterholz, John R. Schomburg	Latch-to-Latch Timing Rules.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	latch-to-latch timing rules, consecutive latch pairs, multiple skew levels, data propagation delays, multiple clock pulse widths, clock phases, logic design, synchronous systems, combinational logic, propagation delay
2		Latch Coupling.	Encyclopedia of Database Systems	2009	DBLP DOI BibTeX RDF
2	Flavio Carbognani, Luca Henzen	Cross-over current suppressing latch compared to state-of-the-art for low-power low-frequency applications with resonant clocking.	ISLPED	2009	DBLP DOI BibTeX RDF	flipflops, low power design, clock, digital circuits, adiabatic
2	Chen-Hsuan Lin, Chun-Yao Wang	Dependent latch identification in the reachable state space.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	S. Srivastava, J. Roychowdhury	Independent and Interdependent Latch Setup/Hold Time Characterization via Newton-Raphson Solution and Euler Curve Tracking of State-Transition Equations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Yoichi Sasaki, Kazuteru Namba, Hideo Ito	Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Masking circuit, Pass transistor, Schmitt trigger circuit, Soft error, Latch
2	Tomohiro Yoshihara, Dai Kobayashi, Haruo Yokota	A concurrency control protocol for parallel B-tree structures without latch-coupling for explosively growing digital content.	EDBT	2008	DBLP DOI BibTeX RDF
2	Sean X. Shi, Anand Ramalingam, Daifeng Wang, David Z. Pan	Latch Modeling for Statistical Timing Analysis.	DATE	2008	DBLP DOI BibTeX RDF
2	Tzu-Yuan Kuo, Jinn-Shyan Wang	A low-voltage latch-adder based tree multiplier.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Hideo Kohinata, Masayuki Arai, Satoshi Fukumoto	An Experimental Study on Latch Up Failure of CMOS LSI.	SSIRI	2008	DBLP DOI BibTeX RDF	latch up, CMOS LSI
2	Hyein Lee, Seungwhun Paik, Youngsoo Shin	Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
2	Chuan Lin, Hai Zhou	Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Seongmoo Heo, Ronny Krashinsky, Krste Asanovic	Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Saihua Lin, Huazhong Yang, Rong Luo	High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Mahdi Fazeli, Ahmad Patooghy, Seyed Ghassem Miremadi, Alireza Ejlali	Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies.	DSN	2007	DBLP DOI BibTeX RDF
2	Shweta Srivastava, Jaijeet S. Roychowdhury	Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations.	DAC	2007	DBLP DOI BibTeX RDF
2	Shweta Srivastava, Jaijeet S. Roychowdhury	Rapid and accurate latch characterization via direct Newton solution of setup/hold times.	DATE	2007	DBLP DOI BibTeX RDF
2	S. Dabas, Ning Dong, Jaijeet S. Roychowdhury	Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate delay modelling, accurate delay/timing macromodels, digital gates, trajectory-piecewise automated nonlinear macromodelling methods, mixed-signal/RF domain, SPICE-level netlists, transparent retargetability, NAND gates, NOR gates, sequential latch, latches, full adder, current-source models, XOR gates
2	Kun Young Chung, Sandeep K. Gupta	Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing.	VTS	2006	DBLP DOI BibTeX RDF
2	Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner	Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications.	PATMOS	2005	DBLP DOI BibTeX RDF
2	Yingmin Li, Mark Hempstead, Patrick Mauro, David Brooks, Zhigang Hu, Kevin Skadron	Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices.	ISLPED	2005	DBLP DOI BibTeX RDF	architecture, power, temperature, clock gating
2	Holly Pekau, Lee Hartley, James W. Haslett	A re-configurable high-speed CMOS track and latch comparator with rail-to-rail input for IF digitization [software radio receiver applications].	ISCAS	2005	DBLP DOI BibTeX RDF
2	Srivathsan Krishnamohan, Nihar R. Mahapatra	Analysis and design of soft-error hardened latches.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	multiple-upset, single-event, soft errors, single-event upset, latch, radiation hardening
2	Oleg Semenov, Hossein Sarbishaei, Manoj Sachdev	Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment.	ISQED	2005	DBLP DOI BibTeX RDF	Electrostatic discharge (ESD), electrical overstress (EOS), LVTSCR, latch-up, burn-in
2	R. Singh, N. Bhat	An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
2	Manan Syal, Michael S. Hsiao, Sreejit Chakravarty	Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks.	ITC	2004	DBLP DOI BibTeX RDF
2	Omid Mirmotahari, Yngvar Berg	A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged Logic.	ISMVL	2004	DBLP DOI BibTeX RDF
2	Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu	Static statistical timing analysis for latch-based pipeline designs.	ICCAD	2004	DBLP DOI BibTeX RDF
2	Masayuki Tsukisaka, Masashi Imai, Takashi Nanya	Asynchronous Scan-Latch controller for Low Area Overhead DFT.	ICCD	2004	DBLP DOI BibTeX RDF
2	Martin Omaña, Daniele Rossi, Cecilia Metra	Novel Transient Fault Hardened Static Latch.	ITC	2003	DBLP DOI BibTeX RDF
2	Kun Young Chung, Sandeep K. Gupta	Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing.	ITC	2003	DBLP DOI BibTeX RDF
2	Peter Dahlgren, Paul Dickinson, Ishwar Parulkar	Latch Divergency In Microprocessor Failure Analysis.	ITC	2003	DBLP DOI BibTeX RDF
2	Marek Wróblewski, Matthias Müller, Andreas Wortmann, Sven Simon, Wilhelm Pieper, Josef A. Nossek	A power efficient register file architecture using master latch sharing.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Massimo Alioto, Gaetano Palumbo	Design of MUX, XOR and D-latch SCL gates.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Massimo Alioto, Gaetano Palumbo	Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates.	PATMOS	2002	DBLP DOI BibTeX RDF
2	Seongmoo Heo, Ronny Krashinsky, Krste Asanovic	Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.	ARVLSI	2001	DBLP DOI BibTeX RDF
2	Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada	A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme.	ASP-DAC	2001	DBLP DOI BibTeX RDF
2	Li Ding 0002, Pinaki Mazumder, N. Srinivas	A dual-rail static edge-triggered latch.	ISCAS	2001	DBLP DOI BibTeX RDF
2	Nikolai Starodoubtsev, Alexandre V. Bystrov, Alexandre Yakovlev	Semi-modular Latch Chains for Asynchronous Circuit Design.	PATMOS	2000	DBLP DOI BibTeX RDF
2	Claude Arm, Jean-Marc Masgonty, Christian Piguet	Double-Latch Clocking Scheme for Low-Power I.P. Cores.	PATMOS	2000	DBLP DOI BibTeX RDF
2	Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang	"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF
2	Saeid Nooshabadi, Juan A. Montiel-Nelson, Antonio Núñez, Roberto Sarmiento, Javier Sosa	A Single Phase Latch for High Speed GaAs Domino Circuits.	DATE	2000	DBLP DOI BibTeX RDF
2	Nicola Nicolici, Bashir M. Al-Hashimi	Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits.	DATE	2000	DBLP DOI BibTeX RDF
2	Charles E. Molnar, Ian W. Jones	Simple Circuits that Work for Complicated Reasons. (PDF / PS)	ASYNC	2000	DBLP DOI BibTeX RDF	MUTEX, Delay measurement technique, Latch control circuit, Charlie Box, Asynchronous, FIFO, Arbiter, Micropipeline
2	Masayuki Tsukisaka, Takashi Nanya	A testable design for asynchronous fine-grain pipeline circuits.	PRDC	2000	DBLP DOI BibTeX RDF	asynchronous fine-grain pipeline circuits, dynamic gates, high-performance datapath design, pipeline latches, scan latch libraries, logic testing, logic CAD, SPICE, CMOS technology, scan path, SPICE simulation, testable design
2	Victor V. Zyuban, Peter M. Kogge	Application of STD to latch-power estimation.	IEEE Trans. VLSI Syst.	1999	DBLP DOI BibTeX RDF
2	Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury	Reconfigurable Latch Controllers for Low Power Asynchronous Circuits.	ASYNC	1999	DBLP DOI BibTeX RDF
2	Kei-Yong Khoo, Chao-Liang Chen, Alan N. Willson Jr.	A CMOS pipelined carry-save array using true single-phase single-transistor-latch clocking.	ISCAS	1999	DBLP DOI BibTeX RDF
2	Octavian-Dumitru Mocanu, Joan Oliver	Fault-Tolerant Memory Architecture Against Radiation-Dependent Errors: A Mixed Error Control Approach.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	hamming SEC code, latch-up, memory system, single event upset, built-in current sensor
2	Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa	A unified approach in the analysis of latches and flip-flops for low-power systems.	ISLPED	1998	DBLP DOI BibTeX RDF	master-slave latch, optimization, timing, flip-flop, power measurement
2	Stephen B. Furber, P. Day	Four-phase micropipeline latch control circuits.	IEEE Trans. VLSI Syst.	1996	DBLP DOI BibTeX RDF
2	Ellen Sentovich, Horia Toma, Gérard Berry	Latch optimization in circuits generated from high-level descriptions.	ICCAD	1996	DBLP DOI BibTeX RDF	sequential optimisation, high-level synthesis, state assignment
2	P. Day, J. V. Woods	Investigation into micropipeline latch design styles.	IEEE Trans. VLSI Syst.	1995	DBLP DOI BibTeX RDF
2	Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia	Fast discrete function evaluation using decision diagrams.	ICCAD	1995	DBLP DOI BibTeX RDF	address lookups, cycle-based logic simulation, decision-diagram based function evaluation, fast discrete function evaluation, latch ports, orders-of-magnitude potential speedup, output ports, logic design, memory hierarchy, logic CAD, decision theory, circuit analysis computing, memory bandwidth, table lookup, digital circuits, logic simulators, logic function, function evaluation, multi-valued decision diagrams
2	Branka Medved Rogina, Bozidar Vojnovic	Metastability evaluation method by propagation delay distribution measurement.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	propagation delay distribution measurement, edge-triggered flip-flops, input signals time relationship, output signal timing characteristics, analytical representation, propagation delay density distribution function, fault events, integrated propagation delay density distribution function, flip-flop normal propagation delay, resolution time constant, automatic data acquisition, complex architecture microsystems, MTBF, latch devices, custom CMOS, VLSI, VLSI, fault diagnosis, logic testing, delays, logic design, asynchronous circuits, flip-flops, data acquisition, failure analysis, reliability analysis, graphical representation, metastability, PLD, asynchronous logic, integrated circuit reliability, statistical measurement
2	Jacob Savir	Module level weighted random patterns.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	module level self-test architecture, pseudorandom pattern generator, universal weighting generator, scan latch, near-optimal weight, signal pins, weight control function, self-test time, logic testing, probability, integrated circuit testing, automatic testing, multivalued logic circuits, boundary scan testing, scan test, weighted random patterns, multiple input signature register
2	Joel Grodstein, Eric Lehman, Heather Harkness, Hervé J. Touati, Bill Grundmann	Optimal latch mapping and retiming within a tree.	ICCAD	1994	DBLP DOI BibTeX RDF
2	Karem A. Sakallah, Trevor N. Mudge, Oyekunle A. Olukotun	Analysis and design of latch-controlled synchronous digital circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1992	DBLP DOI BibTeX RDF
2	Karem A. Sakallah, Trevor N. Mudge, Kunle Olukotun	Analysis and Design of Latch-Controlled Synchronous Digital Circuits.	DAC	1990	DBLP DOI BibTeX RDF
2	Jacob Savir	The Bidirectional Double Latch (BDDL).	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	shift register latch, shift register failure diagnostics, Design for testability, hardware overhead, LSSD
1	Terrence S. T. Mak	Truncation error analysis of MTBF computation for multi-latch synchronizers.	Microelectronics Journal	2012	DBLP DOI BibTeX RDF
1	Riadul Islam	A highly reliable SEU hardened latch and high performance SEU hardened flip-flop.	ISQED	2012	DBLP DOI BibTeX RDF
1	Keisuke Inoue, Mineo Kaneko	Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Chih-Long Chang, Iris H.-R. Jiang, Yu-Ming Yang, Evan Y.-W. Tsai, Aki S.-H. Chen	Novel pulsed-latch replacement based on time borrowing and spiral clustering.	ISPD	2012	DBLP DOI BibTeX RDF
1	Haipeng Zhang, Ruisheng Qi, Liang Zhang, Buchun Su, Dejun Wang	Vertical Gate RF SOI LIGBT for SPICs with Significantly Improved Latch-Up Immunity.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang	Pulsed-Latch Aware Placement for Timing-Integrity Optimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Seungwhun Paik, Seonggwan Lee, Youngsoo Shin	Retiming Pulsed-Latch Circuits With Regulating Pulse Width.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Haiqing Nan, Ken Choi	Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology.	Microelectronics Reliability	2011	DBLP DOI BibTeX RDF
1	Dionyz Pogany, Sergey Bychikhin, Michael Heer, W. Mamanee, Erich Gornik	Application of transient interferometric mapping method for ESD and latch-up analysis.	Microelectronics Reliability	2011	DBLP DOI BibTeX RDF
1	R. Llido, J. Gomez, Vincent Goubier, N. Froidevaux, L. Dufayard, G. Haller, Vincent Pouget, Dean Lewis	Photoelectric Laser Stimulation applied to Latch-Up phenomenon and localization of parasitic transistors in an industrial failure analysis laboratory.	Microelectronics Reliability	2011	DBLP DOI BibTeX RDF
1	Ippokratis Pandis, Pinar Tözün, Ryan Johnson, Anastasia Ailamaki	PLP: Page Latch-free Shared-everything OLTP.	PVLDB	2011	DBLP BibTeX RDF
1	Jason Sewall, Jatin Chhugani, Changkyu Kim, Nadathur Satish, Pradeep Dubey	PALM: Parallel Architecture-Friendly Latch-Free Modifications to B+ Trees on Many-Core Processors.	PVLDB	2011	DBLP BibTeX RDF
1	Youngsoo Shin, Seungwhun Paik	Pulsed-Latch Circuits: A New Dimension in ASIC Design.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF
1	Li Yu, Jingyong Zhang, Lei Wang, Jianguo Lu	A 12-bit fully differential SAR ADC with dynamic latch comparator for portable physiological monitoring applications.	BMEI	2011	DBLP DOI BibTeX RDF
1	Pan Dong, Long Fan, Suge Yue, Hongchao Zheng, Shougang Du	New Latch-Up Model for Deep Sub-micron Integrated Circuits.	DASC	2011	DBLP DOI BibTeX RDF
1	Sandeep Sriram, Haiqing Nan, Ken Choi	Low power latch design in near sub-threshold region to improve reliability for soft error.	ISQED	2011	DBLP DOI BibTeX RDF
1	Carlos Aristoteles De La Cruz Blas, Michael M. Green	CMOS latch based on a class-AB transconductor.	ECCTD	2011	DBLP DOI BibTeX RDF
1	Bill Teng, Jason Helge Anderson	Latch-Based Performance Optimization for FPGAs.	FPL	2011	DBLP DOI BibTeX RDF
1	Hong-Ting Lin, Yi-Lin Chuang, Tsung-Yi Ho	Pulsed-latch-based clock tree migration for dynamic power reduction.	ISLPED	2011	DBLP BibTeX RDF
1	Jong-In Kim, Wan Kim, Barosaim Sung, Seung-Tak Ryu	A time-domain latch interpolation technique for low power flash ADCs.	CICC	2011	DBLP DOI BibTeX RDF
1	Peiyuan Wang, Xiang Chen, Yiran Chen, Hai Helen Li, Seung H. Kang, Xiaochun Zhu, Wenqing Wu	A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis.	CICC	2011	DBLP DOI BibTeX RDF
1	Hai Yu, Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh	Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor.	European Test Symposium	2011	DBLP DOI BibTeX RDF	GRAAL, fault detection, DSP, soft error, SETs
1	Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin	Pulser gating: A clock gating of pulsed-latch circuits.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Chih-Ting Yeh, Yung-Chih Liang, Ming-Dou Ker	Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Yi-Lin Chuang, Hong-Ting Lin, Tsung-Yi Ho, Yao-Wen Chang, Diana Marculescu	PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs.	ICCAD	2011	DBLP DOI BibTeX RDF