Search results for "leakage"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
7	Ashesh Rastogi, Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu	On Composite Leakage Current Maximization.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Leakage Maximizing Pattern Generation (LMPG), Sub-threshold leakage, Band-To-Band Tunneling (BTBT) leakage, Leakage maximization, Weighted max-satisfiability problem, Branch-and-bound heuristic, Gate leakage
5	Wei Wang, Yu Hu, Yinhe Han, Xiaowei Li, You-Sheng Zhang	Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	don’t care bits, minimum leakage vector, leakage power, leakage current
5	Geoffrey C.-F. Yeap	Leakage current in low standby power and high performance devices: trends and challenges.	ISPD	2002	DBLP DOI BibTeX RDF	gate tunneling leakage, low standby power, off-state sub-threshold leakage, system-on-a-ship (SoC), high performance, CMOS technology, leakage current
4	Alodeep Sanyal, Ashesh Rastogi, Wei Chen, Sandip Kundu	An Efficient Technique for Leakage Current Estimation in Nanoscaled CMOS Circuits Incorporating Self-Loading Effects.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	band-to-band-tunneling leakage, loading effect, Newton-Raphson method, gate leakage, Subthreshold leakage
4	Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Park	Leakage Minimization Technique for Nanoscale CMOS VLSI.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	nanometer CMOS, cell characterization, gate-tunneling current, input pattern generation, leakage power, subthreshold leakage current
4	Frank Sill, Jiaxi You, Dirk Timmermann	Design of mixed gates for leakage reduction.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	mixed gates, leakage current, threshold voltage, gate leakage
4	Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi	Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate leakage current, nanometer-scale CMOS circuits, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm, power gating, subthreshold leakage current, 90 nm
4	Yu-Shiang Lin, Dennis Sylvester	Runtime leakage power estimation technique for combinational circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	subthreshold leakage analysis, runtime leakage power estimation technique, dynamic estimation methods, static estimation methods, combinational circuits, error estimation, SPICE simulations
4	Tsung-Yi Wu, Jr-Luen Tzeng, Kuang-Yao Chen	A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost.	ASP-DAC	2007	DBLP DOI BibTeX RDF	MLV controller, probability-based algorithm, leakage current reduction, minimum leakage vector
4	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	LEAF: A System Level Leakage-Aware Floorplanner for SoCs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	LEAF, leakage-aware floorplanning, temperature-aware leakage power, dynamic power profile, system on chip, SoC designs
4	Jie Gu, John Keane, Chris H. Kim	Modeling and analysis of leakage induced damping effect in low voltage LSIs.	ISLPED	2006	DBLP DOI BibTeX RDF	damping effect, supply noise, gate leakage, subthreshold leakage
4	Masaya Sumita	High resolution body bias techniques for reducing the impacts of leakage current and parasitic bipolar.	ISLPED	2005	DBLP DOI BibTeX RDF	band-to band tunneling, body bias generator, dead lock, leakage components, process compensation, substrate bias, process variation, leakage current, CMOS scaling
4	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy	Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits.	ISLPED	2005	DBLP DOI BibTeX RDF	double-gate devices, quantum effect, stacking effect, estimation, SRAM, gate leakage, subthreshold leakage
4	Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty	Managing standby and active mode leakage power in deep sub-micron design.	ISLPED	2004	DBLP DOI BibTeX RDF	SRAM leakage control, TGSRAM, battery lifetime, drowsy mode, thick gate shadow latch, transistor leakage, MTCMOS
4	Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown	Efficient techniques for gate leakage estimation.	ISLPED	2003	DBLP DOI BibTeX RDF	pattern-dependent, pattern-independent, estimation, leakage, gate leakage
4	Saibal Mukhopadhyay, Kaushik Roy	Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation.	ISLPED	2003	DBLP DOI BibTeX RDF	band-to-band tunneling, variability, Monte Carlo, threshold voltage, gate leakage, subthreshold leakage
4	Benton H. Calhoun, Frank Honoré, Anantha Chandrakasan	Design methodology for fine-grained leakage control in MTCMOS.	ISLPED	2003	DBLP DOI BibTeX RDF	fine-grain sleep regions, sneak leakage, low power, design methodology, leakage, circuit design, sleep mode, MTCMOS
4	Amit Agarwal, Kaushik Roy	A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime.	ISLPED	2003	DBLP DOI BibTeX RDF	diode, low leakage cache, SRAM, gate leakage
4	Cassondra Neau, Kaushik Roy	Optimal body bias selection for leakage improvement and process compensation over different technology generations.	ISLPED	2003	DBLP DOI BibTeX RDF	band-to-band tunneling, leakage components, process compensation, substrate bias, process variation, leakage current, CMOS scaling, body bias
4	Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita	Transistor leakage fault location with ZDDQ measurement.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	field effect transistor circuits, transistor leakage fault location, I/sub DDQ/ measurement, equivalence fault collapsing, diagnosed faults, gate-array circuit, fault diagnosis, logic testing, random tests, fault location, CMOS logic circuits, leakage currents, logic arrays, CMOS circuit, deterministic tests, electric current measurement, diagnostic resolution
3	Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino	Dynamic indexing: concurrent leakage and aging optimization for caches.	ISLPED	2010	DBLP DOI BibTeX RDF	leakage optimization, memory hierarchy, aging, NBTI
3	Hyunhee Kim, Jung Ho Ahn, Jihong Kim	Replication-aware leakage management in chip multiprocessors with private L2 cache.	ISLPED	2010	DBLP DOI BibTeX RDF	leakage power management, chip multiprocessors, L2 caches
3	Alireza Vahdatpour, Miodrag Potkonjak	Leakage minimization using self sensing and thermal management.	ISLPED	2010	DBLP DOI BibTeX RDF	delay, thermal management, leakage energy
3	Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino	Aging effects of leakage optimizations for caches.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	memory hierarchy, aging, leakage reduction
3	Ruijing Shen, Sheldon X.-D. Tan, Jinjun Xiong	A linear statistical analysis for full-chip leakage power with spatial correlation.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	statistical leakage analysis, strong and weak correlation, linear, look-up table
3	Mingzhi Gao, Zuochang Ye, Yan Wang, Zhiping Yu	Efficient tail estimation for massive correlated log-normal sums: with applications in statistical leakage analysis.	DAC	2010	DBLP DOI BibTeX RDF	comonotonicity, fast correlation transform, statistical leakage analysis, tail behavior
3	Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil Dutt	Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	multiple sleep mode, peripheral circuits, sram memory, temperature reduction, leakage power
3	Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin	Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	scheduling, placement, Reconfigurable computing, leakage, partially dynamical reconfiguration
3	Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma	Leakage reduction, delay compensation using partition-based tunable body-biasing techniques.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	low-power design, process variations, leakage current, Body biasing
3	Pepijn J. de Langen, Ben H. H. Juurlink	Leakage-Aware Multiprocessor Scheduling.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Scheduling, Multiprocessor, Leakage power, Voltage scaling
3	Michael J. Anderson, Azadeh Davoodi, Jungseob Lee, Abhishek A. Sinkar, Nam Sung Kim	Statistical static timing analysis considering leakage variability in power gated designs.	ISLPED	2009	DBLP DOI BibTeX RDF	process variations, leakage, power gating, ssta
3	Andrea Calimera, Enrico Macii, Massimo Poncino	NBTI-aware power gating for concurrent leakage and aging optimization.	ISLPED	2009	DBLP DOI BibTeX RDF	aging, leakage, power-gating, nbti
3	Xiaoming Chen, Yu Wang 0002, Yu Cao, Yuchun Ma, Huazhong Yang	Variation-aware supply voltage assignment for minimizing circuit degradation and leakage.	ISLPED	2009	DBLP DOI BibTeX RDF	dynamic vdd scaling, leakage power, negative bias temperature instability (NBTI), dual vdd
3	Sherief Reda, Aung Si, R. Iris Bahar	Reducing the leakage and timing variability of 2D ICcs using 3D ICs.	ISLPED	2009	DBLP DOI BibTeX RDF	3D integrated circuit, timing, variability, leakage
3	Kiyoo Itoh	Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era.	ISLPED	2009	DBLP DOI BibTeX RDF	0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet
3	Jinhui Wang, Lei Zuo, Na Gong, Daming Gao, Shuqin Geng, Wang Zhang, Ligang Hou, Xiaohong Peng, Wuchen Wu	Estimation for Speed and Leakage Power of Dual Threshold Domino OR Based on Wavelet Neural Networks.	ISNN	2009	DBLP DOI BibTeX RDF	Dual threshold domino OR, Leakage power, Speed, Wavelet Neural Networks
3	Vikas Kaushal, Quentin Diduck, Martin Margala	Study of leakage current mechanisms in ballistic deflection transistors.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	ballistic transport, current leakage mechanism, deflection transistors, silvaco simulation, geometry, monte carlo simulation
3	Vineeth Veetil, Dennis Sylvester, David Blaauw, Saumil Shah, Steffen Rochel	Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence.	DAC	2009	DBLP DOI BibTeX RDF	statistical leakage, Monte Carlo, variance reduction
3	Xuan-Lun Huang, Chen-Yuan Yang, Jiun-Lang Huang	Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input.	ASP-DAC	2009	DBLP DOI BibTeX RDF	?? modulation, analog/mixed-signal testing, integrator leakage, diagnosis, design-for-test (DfT)
3	Ting Zhu, Ziguo Zhong, Yu Gu 0001, Tian He, Zhi-Li Zhang	Leakage-aware energy synchronization for wireless sensor networks.	MobiSys	2009	DBLP DOI BibTeX RDF	ultra-capacitor, wireless sensor networks, energy, leakage
3	Bilge Mutlu, Fumitaka Yamaoka, Takayuki Kanda, Hiroshi Ishiguro, Norihiro Hagita	Nonverbal leakage in robots: communication of intentions through seemingly unintentional behavior.	HRI	2009	DBLP DOI BibTeX RDF	geminoid, humanlikeness, nonverbal leakage, robovie, gaze, nonverbal behavior
3	Lei Cheng, Deming Chen, Martin D. F. Wong	A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Input vector control, gate replacement, leakage reduction
3	Sandeep Gupta, Jaya Singh, Abhijit Roy	A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs.	ISQED	2008	DBLP DOI BibTeX RDF	Dual-Vt Technology, Cell-Based Approach, Cell-swapping, Leakage Power
3	Shaobo Liu, Qinru Qiu, Qing Wu	Full-chip leakage current estimation based on statistical sampling techniques.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	leakage estimation, statistical sampling, vlsi
3	Maziar Goudarzi, Tohru Ishihara	Instruction cache leakage reduction by changing register operands and using asymmetric sram cells.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	asymmetric sram, leakage, instruction cache, register renaming
3	Tao Li, Wenjun Zhang, Zhiping Yu	Full-chip leakage analysis in nano-scale technologies: mechanisms, variation sources, and verification.	DAC	2008	DBLP DOI BibTeX RDF	leakage modeling, variation source, statistical analysis
3	Vivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal	Leakage power reduction using stress-enhanced layouts.	DAC	2008	DBLP DOI BibTeX RDF	performance, mobility, layout, leakage, stress
3	Min Ni, Seda Ogrenci Memik	Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction.	DAC	2008	DBLP DOI BibTeX RDF	dual-Vth, leakage power optimization, gate sizing, clock skew scheduling
3	Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao	Dose map and placement co-optimization for timing yield enhancement and leakage power reduction.	DAC	2008	DBLP DOI BibTeX RDF	dose map, placement, timing yield, leakage power reduction
3	Ziguo Zhong, Ting Zhu, Tian He, Zhi-Li Zhang	Leakage-aware energy synchronization on twin-star nodes.	SenSys	2008	DBLP DOI BibTeX RDF	energy synchronization, twin-star, leakage
3	Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum	Multiple sleep mode leakage control for cache peripheral circuits in embedded processors.	CASES	2008	DBLP DOI BibTeX RDF	multiple sleep mode, peripheral circuits, cache, embedded processor, leakage power
3	Maziar Goudarzi, Tohru Ishihara, Hamid Noori	Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation.	HiPEAC	2008	DBLP DOI BibTeX RDF	process variation, cache memory, Leakage power, power reduction
3	Wei Zhang 0002, Bramha Allu	Reducing branch predictor leakage energy by exploiting loops.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	compiler, Branch prediction, leakage energy
3	Yuan-Shin Hwang, Jia-Jhe Li	Snug set-associative caches: Reducing leakage power of instruction and data caches with no performance penalties.	TACO	2007	DBLP DOI BibTeX RDF	Caches, leakage power, drowsy caches, cache decay
3	Hongliang Chang, Sachin S. Sapatnekar	Prediction of leakage power under process uncertainties.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	process variation, yield, leakage, Circuit
3	Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang	Post-placement leakage optimization for partially dynamically reconfigurable FPGAs.	ISLPED	2007	DBLP DOI BibTeX RDF	post-placement optimization, scheduling, field-programmable gate array, leakage
3	Simone Medardoni, Davide Bertozzi, Enrico Macii	Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies.	ISLPED	2007	DBLP DOI BibTeX RDF	RTL synthesis, leakage-aware, power management, selection strategy
3	Olga Golubeva, Mirko Loghi, Enrico Macii, Massimo Poncino	Locality-driven architectural cache sub-banking for leakage energy reduction.	ISLPED	2007	DBLP DOI BibTeX RDF	banked cache, memory hierarchy, leakage reduction, architectural optimization
3	Andrew B. Kahng, Swamy Muddu, Puneet Sharma	Detailed placement for leakage reduction using systematic through-pitch variation.	ISLPED	2007	DBLP DOI BibTeX RDF	aCLV, through-pitch, leakage, lithography, detailed placement
3	Jacopo Giorgetti, Giuseppe Scotti, Andrea Simonetti, Alessandro Trifiletti	Analysis of data dependence of leakage current in CMOS cryptographic hardware.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	leakage power consumption, side channel analysis, cryptographic hardware
3	Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas	Modeling and estimating leakage current in series-parallel CMOS networks.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	leakage current modeling, static power dissipation, CMOS gates
3	Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari	Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors.	ISPD	2007	DBLP DOI BibTeX RDF	multi-VTH, optimization, timing, low-power design, microprocessor, EDA, leakage power, sizing
3	Raphael C.-W. Phan, Kim-Kwang Raymond Choo, Swee-Huay Heng	Security of a Leakage-Resilient Protocol for Key Establishment and Mutual Authentication.	ProvSec	2007	DBLP DOI BibTeX RDF	mutual athentication, leakage-resilient, Key establishment
3	Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen	Cache leakage control mechanism for hard real-time systems.	CASES	2007	DBLP DOI BibTeX RDF	cache leakage control policy, hard real-time system
3	Juan M. Cebrian, Juan L. Aragón, José M. García, Stefanos Kaxiras	Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	leakage, value prediction, energy efficient architectures, cache decay
3	Hassan Hassan, Mohab Anis, Mohamed I. Elmasry	A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, timing-driven algorithm, MTCMOS FPGA, MTCMOS CAD methodology, subthreshold leakage power reduction, nanometer FPGA, circuit timing information, CMOS process
3	Jian-Jia Chen, Tei-Wei Kuo	Procrastination determination for periodic real-time tasks in leakage-aware dynamic voltage scaling systems.	ICCAD	2007	DBLP DOI BibTeX RDF	job procrastination, leakage-aware scheduling, scheduling, dynamic voltage scaling, energy-aware systems
3	Yifan Zhu, Frank Mueller	DVSleak: combining leakage reduction and voltage scaling in feedback EDF scheduling.	LCTES	2007	DBLP DOI BibTeX RDF	scheduling, real-time systems, dynamic voltage scaling, leakage, feedback control
3	Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan	Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach.	ASP-DAC	2007	DBLP DOI BibTeX RDF	programming method, decoupling capacitor budgeting algorithm, random walk approach, decap budgeting algorithm, power ground network design, isolation property, decap optimization process, leakage currents optimization algorithm, refined leakage model, heuristic method
3	Wei Zhang 0002, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Reducing dynamic and leakage energy in VLIW architectures.	ACM Trans. Embedded Comput. Syst.	2006	DBLP DOI BibTeX RDF	dynamic energy, schedule slacks, compiler, VLIW architecture, leakage energy
3	Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim	Leakage Power Analysis and Reduction for Nanoscale Circuits.	IEEE Micro	2006	DBLP DOI BibTeX RDF	nanoscale circuits, CMOS, technology scaling, leakage power reduction
3	Yi-Ping You, Chingren Lee, Jenq Kuen Lee	Compilers for leakage power reduction.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Compilers for low power, power-gating mechanisms, leakage-power reduction
3	Sachin S. Sapatnekar	Book Reviews: Plumbing the Depths of Leakage.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	nanometer CMOS technology, leakage
3	Zhiyu Liu, Volkan Kursun	Leakage Biased Sleep Switch Domino Logic.	ISQED	2006	DBLP DOI BibTeX RDF	gate oxide tunneling, sleep mode, Domino logic, subthreshold leakage current, dual threshold voltage
3	Rahul Nagpal, Y. N. Srikant	Compiler-assisted leakage energy optimization for clustered VLIW architectures.	EMSOFT	2006	DBLP DOI BibTeX RDF	scheduling, leakage energy, energy-aware scheduling, clustered VLIW processors
3	Yu Wang 0002, Yongpan Liu, Rong Luo, Huazhong Yang, Hui Wang 0004	Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	leakage current reduction, two-phase fine-grain sleep transistor insertion, mixed integer linear programming
3	Baozhen Yu, Michael L. Bushnell	A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	power cutoff, standby current, stacking, leakage current, dynamic power
3	Ke Meng, Russ Joseph	Process variation aware cache leakage management.	ISLPED	2006	DBLP DOI BibTeX RDF	gated-VDD, selective cache ways, low power, process variation, leakage, cache management
3	Domenik Helms, Günter Ehmen, Wolfgang Nebel	Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation.	ISLPED	2006	DBLP DOI BibTeX RDF	modeling, process variation, leakage, state dependence
3	Javid Jaffari, Mohab Anis	Variability-aware device optimization under ION and leakage current constraints.	ISLPED	2006	DBLP DOI BibTeX RDF	device design, optimization, performance, process variation, leakage current
3	Michele Boreale	Quantifying Information Leakage in Process Calculi.	ICALP	2006	DBLP DOI BibTeX RDF	information theory, process calculi, secrecy, information leakage
3	Zhiyu Liu, Volkan Kursun	Leakage current starved domino logic.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	gate oxide tunneling, sleep mode, domino logic, subthreshold leakage current, dual threshold voltage
3	Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. Massoud	An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	gate oxide tunneling, low power circuit design, subthreshold leakage, dual threshold voltage
3	Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino	STV-Cache: a leakage energy-efficient architecture for data caches.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	architecture, caches, leakage power
3	Sung Woo Chung, Kevin Skadron	Using Branch Prediction Information for Near-Optimal I-Cache Leakage.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Low Power, Branch Prediction, Leakage, Instruction Cache, Drowsy Cache
3	Chengyi Zhang, Hongwei Zhou, Minxuan Zhang, Zuocheng Xing	An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Periodically Drowsy Speculative Recover, Adaptive, Leakage Power, Drowsy cache
3	Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky	Gain-based technology mapping for minimum runtime leakage under input vector uncertainty.	DAC	2006	DBLP DOI BibTeX RDF	leakage, technology mapping, logical effort
3	Xin Li, Jiayong Le, Lawrence T. Pileggi	Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions.	DAC	2006	DBLP DOI BibTeX RDF	statistical analysis, leakage power
3	Hari Ananthan, Kaushik Roy	A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS.	DAC	2006	DBLP DOI BibTeX RDF	leakage distribution, multiple-gate, tri-gate, process variations, finFET, double-gate
3	Lei Cheng, Liang Deng, Deming Chen, Martin D. F. Wong	A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction.	DAC	2006	DBLP DOI BibTeX RDF	gate replacement, input vector control, leakage reduction
3	Saumil Shah, Puneet Gupta, Andrew B. Kahng	Standard cell library optimization for leakage reduction.	DAC	2006	DBLP DOI BibTeX RDF	gate-length biasing, library optimization, leakage reduction
3	Georges Nabaa, Navid Azizi, Farid N. Najm	An adaptive FPGA architecture with process variation compensation and reduced leakage.	DAC	2006	DBLP DOI BibTeX RDF	FPGA, process variations, leakage, body-biasing
3	Yan Meng, Timothy Sherwood, Ryan Kastner	Leakage power reduction of embedded memories on FPGAs through location assignment.	DAC	2006	DBLP DOI BibTeX RDF	location assignment, leakage power, embedded memory
3	Govind Kabra, Ravishankar Ramamurthy, S. Sudarshan	Redundancy and information leakage in fine-grained access control.	SIGMOD Conference	2006	DBLP DOI BibTeX RDF	query optimization, redundancy, information leakage, fine-grained access control
3	Wann-Yun Shieh, Hsin-Dar Chen	Saving Register-File Leakage Power by Monitoring Instruction Sequence in ROB.	EUC Workshops	2006	DBLP DOI BibTeX RDF	register leakage power, high-end embedded processor, dynamic voltage scaling (DVS), reorder buffer
3	Jian-Jia Chen, Heng-Ruey Hsu, Tei-Wei Kuo	Leakage-Aware Energy-Efficient Scheduling of Real-Time Tasks in Multiprocessor Systems.	IEEE Real Time Technology and Applications Symposium	2006	DBLP DOI BibTeX RDF	Leakage-aware scheduling, Real-time and embedded systems and Task partitioning
3	Eric Wong, Jacob R. Minz, Sung Kyu Lim	Decoupling capacitor planning and sizing for noise and leakage reduction.	ICCAD	2006	DBLP DOI BibTeX RDF	3D floorplanning, power supply noise, decoupling capacitors, leakage power reduction
3	Jian-Jia Chen, Tei-Wei Kuo	Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processor.	LCTES	2006	DBLP DOI BibTeX RDF	leakage-aware scheduling, scheduling, dynamic voltage scaling, fixed-priority scheduling, energy-aware systems, rate-monotonic scheduling
3	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	Floorplan driven leakage power aware IP-based SoC design space exploration.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	floorplan, leakage power, temperature
3	Zhiyu Liu, Volkan Kursun	Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages.	ISQED	2006	DBLP DOI BibTeX RDF	Low Voltage Swing, Gate Oxide Leakage, Domino Logic, Subthreshold Leakage, Dual Threshold Voltage