Search results for "leakage current"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Wei Wang, Yu Hu, Yinhe Han, Xiaowei Li, You-Sheng Zhang	Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	don’t care bits, minimum leakage vector, leakage power, leakage current
3	Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas	Modeling and estimating leakage current in series-parallel CMOS networks.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	leakage current modeling, static power dissipation, CMOS gates
3	Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi	Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate leakage current, nanometer-scale CMOS circuits, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm, power gating, subthreshold leakage current, 90 nm
3	Tsung-Yi Wu, Jr-Luen Tzeng, Kuang-Yao Chen	A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost.	ASP-DAC	2007	DBLP DOI BibTeX RDF	MLV controller, probability-based algorithm, leakage current reduction, minimum leakage vector
3	Zhiyu Liu, Volkan Kursun	Leakage current starved domino logic.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	gate oxide tunneling, sleep mode, domino logic, subthreshold leakage current, dual threshold voltage
3	Masaya Sumita	High resolution body bias techniques for reducing the impacts of leakage current and parasitic bipolar.	ISLPED	2005	DBLP DOI BibTeX RDF	band-to band tunneling, body bias generator, dead lock, leakage components, process compensation, substrate bias, process variation, leakage current, CMOS scaling
3	A. Amirabadi, Javid Jaffari, Ali Afzali-Kusha, Mehrdad Nourani, Ali Khaki-Firooz	Leakage current reduction by new technique in standby mode.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	subthreshold current, low power, leakage current, digital integrated circuits, static power
3	Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester	Statistical estimation of leakage current considering inter- and intra-die process variation.	ISLPED	2003	DBLP DOI BibTeX RDF	variability, Monte Carlo, leakage current
3	Yongjun Xu, Zuying Luo, Zhiguo Chen, Xiaowei Li	Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	stack effect, leakage current simulation, propagation of signal probability, macromodeling
3	Geoffrey C.-F. Yeap	Leakage current in low standby power and high performance devices: trends and challenges.	ISPD	2002	DBLP DOI BibTeX RDF	gate tunneling leakage, low standby power, off-state sub-threshold leakage, system-on-a-ship (SoC), high performance, CMOS technology, leakage current
3	Manoj Sachdev	SeparateIDDQ testing of signal and bias paths in CMOS ICs for defect diagnosis.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	junction leakage current, diagnostics, deep sub-micron, I DDQ testing, subthreshold leakage current
2	Vikas Kaushal, Quentin Diduck, Martin Margala	Study of leakage current mechanisms in ballistic deflection transistors.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	ballistic transport, current leakage mechanism, deflection transistors, silvaco simulation, geometry, monte carlo simulation
2	Yongli Zhu, Yuanqing Huang	Application of EMD in the De-noise of Insulator Leakage Current.	IFITA	2009	DBLP DOI BibTeX RDF	insulators, end effect, noise, leakage current
2	Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma	Leakage reduction, delay compensation using partition-based tunable body-biasing techniques.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	low-power design, process variations, leakage current, Body biasing
2	Ashesh Rastogi, Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu	On Composite Leakage Current Maximization.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Leakage Maximizing Pattern Generation (LMPG), Sub-threshold leakage, Band-To-Band Tunneling (BTBT) leakage, Leakage maximization, Weighted max-satisfiability problem, Branch-and-bound heuristic, Gate leakage
2	Shaobo Liu, Qinru Qiu, Qing Wu	Full-chip leakage current estimation based on statistical sampling techniques.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	leakage estimation, statistical sampling, vlsi
2	Tadayoshi Enomoto, Yuki Higuchi	A low-leakage current power 180-nm CMOS SRAM.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Josef Haid, Bernd Zimek, Thomas Leutgeb, Thomas Kunemund	Impact of Leakage Current on Data Retention of RF-powered Devices During Amplitude-Modulation-based Communication.	DATE	2008	DBLP DOI BibTeX RDF
2	Kuen-Yu Tsai, Meng-Fu You, Yi-Chang Lu, Philip C. W. Ng	A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects.	ICCAD	2008	DBLP DOI BibTeX RDF
2	Min-Hsiung Hsieh, Shuen-Lin Jeng	Accelerated Discrete Degradation Models for Leakage Current of Ultra-Thin Gate Oxides.	IEEE Transactions on Reliability	2007	DBLP DOI BibTeX RDF
2	Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas	Modeling Subthreshold Leakage Current in General Transistor Networks.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Jacopo Giorgetti, Giuseppe Scotti, Andrea Simonetti, Alessandro Trifiletti	Analysis of data dependence of leakage current in CMOS cryptographic hardware.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	leakage power consumption, side channel analysis, cryptographic hardware
2	Ashesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu	A Study on Impact of Leakage Current on Dynamic Power.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan	Voltage drop reduction for on-chip power delivery considering leakage current variations.	ICCD	2007	DBLP DOI BibTeX RDF
2	Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami	The effect of temperature on cache size tuning for low energy embedded systems.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	embedded systems, cache memory, low energy, leakage current, temperature-aware design
2	Aveek Sarkar, Shen Lin, Kai Wang	A methodology for analysis and verification of power gated circuits with correlated results.	ISLPED	2007	DBLP DOI BibTeX RDF	RedHawk, standby leakage current, design, verification, analysis, power gate, MTCMOS
2	Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab	Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches.	ASP-DAC	2007	DBLP DOI BibTeX RDF	reconfigurable instant-on system, ultralow-power reconfigurable computing, complementary nanoelectromechanical carbon nanotube switches, coplanar carbon nanotubes, low operation voltages, built-in energy storage, CNEMS, stable on-off state, latching mechanism, nonvolatile memory-mode operation, CMOS transistors, system development, leakage current
2	Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Park	Leakage Minimization Technique for Nanoscale CMOS VLSI.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	nanometer CMOS, cell characterization, gate-tunneling current, input pattern generation, leakage power, subthreshold leakage current
2	Imad A. Ferzli, Farid N. Najm	Analysis and verification of power grids considering process-induced leakage-current variations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Sagar S. Sabade, D. M. H. Walker	Estimation of fault-free leakage current using wafer-level spatial information.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar	A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	Lin Yuan, Gang Qu	A combined gate replacement and input vector control approach for leakage current reduction.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	Javid Jaffari, Mohab Anis	Variability-aware device optimization under ION and leakage current constraints.	ISLPED	2006	DBLP DOI BibTeX RDF	device design, optimization, performance, process variation, leakage current
2	Hyung-Ock Kim, Youngsoo Shin	Analysis and optimization of gate leakage current of power gating circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Yu Wang 0002, Yongpan Liu, Rong Luo, Huazhong Yang, Hui Wang 0004	Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	leakage current reduction, two-phase fine-grain sleep transistor insertion, mixed integer linear programming
2	Afshin Abdollahi, Farzan Fallah, Massoud Pedram	Analysis and Optimization of Static Power Considering Transition Dependency of Leakage Current in VLSI Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
2	Mohab Anis, Mohamed H. Abu-Rahma	Leakage Current Variability in Nanometer Technologies, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
2	Guang-Wan Liao, Ja-Shong Feng, Rung-Bin Lin	A divide-and-conquer approach to estimating minimum/maximum leakage current.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Canh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai	More than two orders of magnitude leakage current reduction in look-up table for FPGAs.	ISCAS	2005	DBLP DOI BibTeX RDF
2	A. Madan, S. C. Bose, P. J. George, Chandra Shekhar	Evaluation of Device Parameters of HfO2/SiO2/Si Gate Dielectric Stack for MOSFETs.	VLSI Design	2005	DBLP DOI BibTeX RDF	Direct Tunneling, gate leakage current, high-K gate stack, MOSFETs
2	Volkan Kursun, Eby G. Friedman	Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits.	ISQED	2004	DBLP DOI BibTeX RDF
2	Peilin Song, Franco Stellari, Alan J. Weger, Tian Xia	A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current.	ITC	2004	DBLP DOI BibTeX RDF
2	John Lach, Jason Brandon, Kevin Skadron	A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAs.	ICCD	2004	DBLP DOI BibTeX RDF
2	Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy	Leakage in nano-scale technologies: mechanisms, impact and design considerations.	DAC	2004	DBLP DOI BibTeX RDF	process variation, leakage current, circuit design
2	Oleg Semenov, Arman Vassighi, Manoj Sachdev	Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta IDDQ Testing.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	MOSFET leakage, reliability, quality, CMOS integrated circuits, I DDQ testing
2	Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester	Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design.	ISQED	2003	DBLP DOI BibTeX RDF
2	Afshin Abdollahi, Farzan Fallah, Massoud Pedram	Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains.	ISQED	2003	DBLP DOI BibTeX RDF
2	Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy	Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling.	DAC	2003	DBLP DOI BibTeX RDF	doping profiles, leakage, tunneling, threshold voltage
2	Hui-Yuan Song, S. Bohidar, R. Iris Bahar, Joel Grodstein	Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current.	ICCD	2003	DBLP DOI BibTeX RDF
2	Nikhil Jayakumar, Sunil P. Khatri	An ASIC design methodology with predictably low leakage, using leakage-immune standard cells.	ISLPED	2003	DBLP DOI BibTeX RDF	standby current, leakage current, standard cells, MTCMOS
2	Cassondra Neau, Kaushik Roy	Optimal body bias selection for leakage improvement and process compensation over different technology generations.	ISLPED	2003	DBLP DOI BibTeX RDF	band-to-band tunneling, leakage components, process compensation, substrate bias, process variation, leakage current, CMOS scaling, body bias
2	Hyo-Sig Won, Kyo-Sun Kim, Kwang-Ok Jeong, Ki-Tae Park, Kyu-Myung Choi, Jeong-Taek Kong	An MTCMOS design methodology and its application to mobile computing.	ISLPED	2003	DBLP DOI BibTeX RDF	CPFF, low power, leakage current, CCS, MTCMOS
2	Afshin Abdollahi, Massoud Pedram, Farzan Fallah	Runtime mechanisms for leakage current reduction in CMOS VLSI circuits1, 2.	ISLPED	2002	DBLP DOI BibTeX RDF
2	Ashish Srivastava, Robert Bai, David Blaauw, Dennis Sylvester	Modeling and analysis of leakage power considering within-die process variations.	ISLPED	2002	DBLP DOI BibTeX RDF	variability, Monte Carlo, leakage current
2	Louis S. Y. Wong, Shohan Hossain, Andre Walker	Leakage current cancellation technique for low power switched-capacitor circuits.	ISLPED	2001	DBLP DOI BibTeX RDF	sample and hold, low power, analog, leakage current, switched-capacitor circuit, amplifier
2	José Pineda de Gyvez, Eric van de Wetering	Average Leakage Current Estimation of CMOS Logic Circuits.	VTS	2001	DBLP DOI BibTeX RDF
2	Daniel Eckerbert, Per Larsson-Edefors	Cycle-true leakage current modeling for CMOS gates.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Yingchieh Ho, Chiachi Chang, Chauchin Su	Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique.	IEEE Trans. on Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	H. C. Srinivasaiah	Implications of Halo Implant Shadowing and Backscattering from Mask Layer Edges on Device Leakage Current in 65nm SRAM.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	E. Miranda, C. Mahata, T. Das, C. K. Maiti	An extension of the Curie-von Schweidler law for the leakage current decay in MIS structures including progressive breakdown.	Microelectronics Reliability	2011	DBLP DOI BibTeX RDF
1	Yi-Hsin Weng, Hui-Wen Tsai, Ming-Dou Ker	Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS process.	Microelectronics Reliability	2011	DBLP DOI BibTeX RDF
1	Guntrade Roll, Matthias Goldbach, Lothar Frey	Leakage current and defect characterization of p+n-source/drain diodes.	Microelectronics Reliability	2011	DBLP DOI BibTeX RDF
1	Jinhui Wang, Na Gong, Ligang Hou, Xiaohong Peng, Ramalingam Sridhar, Wuchen Wu	Leakage current, active power, and delay analysis of dynamic dual Vt CMOS circuits under P-V-T fluctuations.	Microelectronics Reliability	2011	DBLP DOI BibTeX RDF
1	Valdi Rizki Yandri	The estimation of flashover voltage as 20 kV outdoor insulator in tropical environment based on leakage current data.	ICEEI	2011	DBLP DOI BibTeX RDF
1	Abdul Syakur, Hamzah Berahim, Tumiran, Rochmadi	Leakage current measurement of epoxy resin compound with silicon rubber.	ICEEI	2011	DBLP DOI BibTeX RDF
1	Yanan Sun, Volkan Kursun	Leakage current and bottom gate voltage considerations in developing maximum performance 16nm N-channel carbon nanotube transistors.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Jim Aarestad, Dhruva Acharyya, Reza M. Rad, Jim Plusquellic	Detecting Trojans Through Leakage Current Analysis Using Multiple Supply Pad IDDQ s.	IEEE Transactions on Information Forensics and Security	2010	DBLP DOI BibTeX RDF
1	Terdsak Intachot, Nontawat Chuladaycha, Yothin Prempraneerach, Shuichi Nitta	A Current Mode Analysis on Ground Leakage Current Noise Generation in Unbalanced and Balanced Switching Converters.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Soo-Han Choi, Young Hee Park, Chul-Hong Park, Sang Hoon Lee, Moon-Hyun Yoo, Jun Dong Cho, Gyu Tae Kim	Suppression of Edge Effects Based on Analytic Model for Leakage Current Reduction of Sub-40 nm DRAM Device.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, André Inácio Reis, Renato P. Ribas	Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits.	Microelectronics Journal	2010	DBLP DOI BibTeX RDF
1	Alodeep Sanyal, Ashesh Rastogi, Wei Chen, Sandip Kundu	An Efficient Technique for Leakage Current Estimation in Nanoscaled CMOS Circuits Incorporating Self-Loading Effects.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	band-to-band-tunneling leakage, loading effect, Newton-Raphson method, gate leakage, Subthreshold leakage
1	H. J. Hung, J. B. Kuo, D. Chen, C. S. Yeh	Gate tunneling leakage current behavior of 40 nm PD SOI NMOS device considering the floating body effect.	Microelectronics Reliability	2010	DBLP DOI BibTeX RDF
1	E. Atanassova, N. Novkovski, Albena Paskaleva, D. Spassov	Constant current stress-induced leakage current in mixed HfO2-Ta2O5 stacks.	Microelectronics Reliability	2010	DBLP DOI BibTeX RDF
1	Shih-Hsu Huang, Chun-Hua Cheng	Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization.	J. Inf. Sci. Eng.	2010	DBLP BibTeX RDF
1	Jung-Yu Chang, Shen-Iuan Liu	A Phase-Locked Loop With Background Leakage Current Compensation.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Ankit More, Baris Taskin	Leakage current analysis for intra-chip wireless interconnects.	ISQED	2010	DBLP DOI BibTeX RDF
1	Na Gong, Ramalingam Sridhar	Optimization and predication of leakage current characteristics in wide domino OR gates under PVT variation.	SoCC	2010	DBLP DOI BibTeX RDF
1	Jun Seomun, Insup Shin, Youngsoo Shin	Synthesis and implementation of active mode power gating circuits.	DAC	2010	DBLP DOI BibTeX RDF	active leakage, active-mode power gating, low power
1	Ruijing Shen, Sheldon X.-D. Tan, Jinjun Xiong	A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation.	DAC	2010	DBLP DOI BibTeX RDF	statistical analysis, spatial correlation, dynamic power
1	Yongchan Ban, Savithri Sundareswaran, David Z. Pan	Total sensitivity based dfm optimization of standard library cells.	ISPD	2010	DBLP DOI BibTeX RDF	optimization, VLSI, sensitivity, DFM, lithography
1	Tsuyoshi Sakata, Takaaki Okumura, Atsushi Kurokawa, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto, Koutaro Hachiya, Katsuhiro Furukawa, Masakazu Tanaka, Hiroshi Takafuji, Toshiki Kanamoto	An Approach for Reducing Leakage Current Variation due to Manufacturing Variability.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Kawori Takakubo, Toru Eto, Hajime Takakubo	Analysis and Modeling of Leakage Current for Four-Terminal MOSFET in Off-State and Low Leakage Switches.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Khaled R. Heloue, Navid Azizi, Farid N. Najm	Full-Chip Model for Leakage-Current Estimation Considering Within-Die Correlation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	M. Lanza, M. Porti, M. Nafría, X. Aymerich, G. Ghidini, A. Sebastiani	Trapped charge and stress induced leakage current (SILC) in tunnel SiO2 layers of de-processed MOS non-volatile memory devices observed at the nanoscale.	Microelectronics Reliability	2009	DBLP DOI BibTeX RDF
1	M. S. Rahman, E. K. Evangelou, I. I. Androulidakis, A. Dimoulas	Study of stress-induced leakage current (SILC) in HfO2/Dy2O3 high-kappa gate stacks on germanium.	Microelectronics Reliability	2009	DBLP DOI BibTeX RDF
1	Armin Tajalli, Yusuf Leblebici	Leakage Current Reduction Using Subthreshold Source-Coupled Logic.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Franco Stellari, Peilin Song, John Sylvestri, D. Miles, Orazio P. Forlenza, Donato O. Forlenza	On-chip power supply noise measurement using Time Resolved Emission (TRE) waveforms of Light Emission from Off-State Leakage Current (LEOSLC).	ITC	2009	DBLP DOI BibTeX RDF
1	Suwarno, F. Pratomosiwi	Computer Simulation of Leakage Current on Ceramic Insulator under Clean Fog Condition.	Asia International Conference on Modelling and Simulation	2009	DBLP DOI BibTeX RDF
1	Ming-Dou Ker, Po-Yen Chiu, Fu-Yi Tsai, Yeong-Jar Chang	On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro López, José Duato	An hybrid eDRAM/SRAM macrocell to implement first-level data caches.	MICRO	2009	DBLP DOI BibTeX RDF	retention time, static and dynamic memory cells, leakage current
1	Charles Augustine, Behtash Behin-Aein, Xuanyao Fong, Kaushik Roy	A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Shih-Hsu Huang, Chun-Hua Cheng	Timing driven power gating in high-level synthesis.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Statistical modeling and analysis of chip-level leakage power by spectral stochastic method.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar	Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Mark Hempstead, Gu-Yeon Wei, David Brooks	An accelerator-based wireless sensor network processor in 130nm CMOS.	CASES	2009	DBLP DOI BibTeX RDF	accelerator-based, wireless sensor networks, ultra-low power
1	Miodrag Potkonjak, Ani Nahapetian, Michael Nelson, Tammara Massey	Hardware Trojan horse detection using gate-level characterization.	DAC	2009	DBLP DOI BibTeX RDF	Hardware Trojan horses, gate-level characterization, linear programming, manufacturing variability
1	Khawla Alzoubi, Daniel G. Saab, Massood Tabib-Azar	Complementary nano-electromechanical switches for ultra-low power embedded processors.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	nems, cmos, switch, device, ultra-low power
1	Basab Datta, Wayne P. Burleson	Low-power, process-variation tolerant on-chip thermal monitoring using track and hold based thermal sensors.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	sensor, interconnect, temperature, oscillator
1	Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shayan Arani, A. Ege Engin, Chung-Kuan Cheng	Predicting the worst-case voltage violation in a 3D power network.	SLIP	2009	DBLP DOI BibTeX RDF	worst case violation prediction, integer linear programming, leakage, clock gating, power networks
1	Prateek Mishra, Anish Muttreja, Niraj K. Jha	Low-power FinFET circuit synthesis using multiple supply and threshold voltages.	JETC	2009	DBLP DOI BibTeX RDF	Low-power, linear programming, synthesis, TCMS