Search results for "leakage reduction"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Lin Yuan, Gang Qu	Enhanced leakage reduction Technique by gate replacement.	DAC	2005	DBLP DOI BibTeX RDF	MLV, gate replacement, leakage reduction
3	Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin	Implications of technology scaling on leakage reduction techniques.	DAC	2003	DBLP DOI BibTeX RDF	low power, technology scaling, leakage reduction
2	Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie	Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation.	IEEE Trans. Dependable Sec. Comput.	2011	DBLP DOI BibTeX RDF	temperature-aware NBTI modeling, circuit performance degradation, Negative bias temperature instability (NBTI), leakage reduction
2	Kagan Irez, Jiaping Hu, Charles A. Zukowski	Characteristics of MS-CMOS logic in sub-32nm technologies.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	MSCMOS, gate leakage reduction, hs&ls, logic overhead, upsizing, noise margin, input vector, domino, downsizing
2	Sandeep Gupta, Jaya Singh, Abhijit Roy	A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs.	ISQED	2008	DBLP DOI BibTeX RDF	Dual-Vt Technology, Cell-Based Approach, Cell-swapping, Leakage Power
2	Hushrav Mogal, Kia Bazargan	Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction.	ICCAD	2008	DBLP DOI BibTeX RDF
2	Hao Xu, Ranga Vemuri, Wen-Ben Jone	Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW.	ICCD	2008	DBLP DOI BibTeX RDF
2	Frank Sill, Jiaxi You, Dirk Timmermann	Design of mixed gates for leakage reduction.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	mixed gates, leakage current, threshold voltage, gate leakage
2	Hassan Hassan, Mohab Anis, Mohamed I. Elmasry	A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, timing-driven algorithm, MTCMOS FPGA, MTCMOS CAD methodology, subthreshold leakage power reduction, nanometer FPGA, circuit timing information, CMOS process
2	Soumyaroop Roy, Srinivas Katkoori, Nagarajan Ranganathan	A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors.	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Rodrigo Jaramillo-Ramirez, Mohab Anis	A Dual-Threshold FPGA Routing Design for Subthreshold Leakage Reduction.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Jun-Cheol Park, Vincent John Mooney III	Sleepy Stack Leakage Reduction.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos	Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective.	ISQED	2006	DBLP DOI BibTeX RDF
2	Saumil Shah, Puneet Gupta, Andrew B. Kahng	Standard cell library optimization for leakage reduction.	DAC	2006	DBLP DOI BibTeX RDF	gate-length biasing, library optimization, leakage reduction
2	Mohammad Sharifkhani, Manoj Sachdev	A low power SRAM architecture based on segmented virtual grounding.	ISLPED	2006	DBLP DOI BibTeX RDF	static-random access memory, write power reduction, low-power, SRAM, leakage reduction
2	Weiping Liao, Joseph M. Basile, Lei He	Microarchitecture-level leakage reduction with data retention.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
2	Philippe Royannez, Hugh Mair, Franck Dahan, Mike Wagner, Mark Streeter, Laurent Bouetel, Joel Blasquez, H. Clasen, G. Semino, Julie Dong, D. Scott, B. Pitts, Claudine Raibaut, Uming Ko	A design platform for 90-nm leakage reduction techniques.	DAC	2005	DBLP DOI BibTeX RDF	leakage power management, wireless application processor, SoC design
2	Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin	Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif	Approaches to run-time and standby mode leakage reduction in global buses.	ISLPED	2004	DBLP DOI BibTeX RDF	pulsed buses, leakage, repeaters, MTCMOS
2	Sergey Romanovsky, Arun Achyuthan, Sreedhar Natarajan, Wing Leung	Leakage Reduction techniques in a 0.13um SRAM Cell.	VLSI Design	2004	DBLP DOI BibTeX RDF
2	Narender Hanchate, Nagarajan Ranganathan	A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors.	VLSI Design	2004	DBLP DOI BibTeX RDF
2	Saibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal, Chris H. Kim, Kaushik Roy	Gate leakage reduction for scaled devices using transistor stacking.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
2	Seongmoo Heo, Kenneth C. Barr, Mark Hampton, Krste Asanovic	Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines. (PDF / PS)	ISCA	2002	DBLP DOI BibTeX RDF	Dynamic Leakage Reduction
1	Anupama R. Subramaniam, Ritu Singhal, Chi-Chao Wang, Yu Cao	Leakage reduction through optimization of regular layout parameters.	Microelectronics Journal	2012	DBLP DOI BibTeX RDF
1	Elias K. Kokkinis, Joshua D. Reiss, John Mourjopoulos	A Wiener Filter Approach to Microphone Leakage Reduction in Close-Microphone Applications.	IEEE Transactions on Audio, Speech & Language Processing	2012	DBLP DOI BibTeX RDF
1	Maziar Goudarzi, Tohru Ishihara, Hamid Noori	Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies.	T. HiPEAC	2011	DBLP DOI BibTeX RDF
1	Weiqiang Zhang, Li Su, Yu Zhang, Linfeng Li, Jianping Hu	Low-Leakage Flip-Flops Based on Dual-Threshold and Multiple Leakage Reduction Techniques.	Journal of Circuits, Systems, and Computers	2011	DBLP DOI BibTeX RDF
1	Dong-Su Lee, Young-Hyun Jun, Bai-Sun Kong	Simultaneous Reverse Body and Negative Word-Line Biasing Control Scheme for Leakage Reduction of DRAM.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti	Post-Synthesis Circuit Techniques for Runtime Leakage Reduction.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Sheng Li, Ke Chen, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi	CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Sudip Roy, Ajit Pal	A New Technique for Runtime Leakage Reduction and Its Sensitivity and Parametric Yield Analysis Under Effective Channel-Length Variation.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Maziar Goudarzi, Tohru Ishihara	SRAM Leakage Reduction by Row/Column Redundancy Under Random Within-Die Delay Variation.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	J. Deshmukh, K. Khare	Standby leakage reduction in nanoscale CMOS VLSI circuits.	ICWET	2010	DBLP DOI BibTeX RDF
1	Meng Tie, Haiying Dong, Tong Wang, Xu Cheng	Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement.	DATE	2010	DBLP BibTeX RDF
1	Massimo Alioto, Paolo Bennati, Roberto Giorgi	Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Jintao Jiang, Xiaolei Sheng, Jianping Hu	An Adiabatic Content-Addressable Memory Based on Dual Threshold Leakage Reduction Technique.	ISIA	2010	DBLP DOI BibTeX RDF
1	Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino	Aging effects of leakage optimizations for caches.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	memory hierarchy, aging, leakage reduction
1	Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil Dutt	Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	multiple sleep mode, peripheral circuits, sram memory, temperature reduction, leakage power
1	Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma	Leakage reduction, delay compensation using partition-based tunable body-biasing techniques.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	low-power design, process variations, leakage current, Body biasing
1	Mohd. Hasan, A. K. Kureshi, Tughrul Arslan	Leakage Reduction in FPGA Routing Multiplexers.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Armin Tajalli, Yusuf Leblebici	Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori	Compiler-directed leakage reduction in embedded microprocessors.	ICCD	2009	DBLP DOI BibTeX RDF
1	Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar	Adaptive techniques for overcoming performance degradation due to aging in digital circuits.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	José Manuel Velasco, David Atienza, Katzalin Olcoz	Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systems.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	memory exploration, java, embedded systems, garbage collection
1	Andrea Calimera, Enrico Macii, Massimo Poncino	NBTI-aware power gating for concurrent leakage and aging optimization.	ISLPED	2009	DBLP DOI BibTeX RDF	aging, leakage, power-gating, nbti
1	Shuo Wang, Jianwei Dai, El-Sayed Hasaneen, Lei Wang 0003, Faquir Jain	Utilizing quantum dot transistors with programmable threshold voltages for low-power mobile computing.	JETC	2009	DBLP DOI BibTeX RDF	threshold voltage and quantum dot transistor, Low power
1	Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin	Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	scheduling, placement, Reconfigurable computing, leakage, partially dynamical reconfiguration
1	S. Lakshminarayanan, J. Joung, G. Narasimhan, R. Kapre, M. Slanina, J. Tung, M. Whately, C.-L. Hou, W.-J. Liao, S.-C. Lin, P.-G. Ma, C.-W. Fan, M.-C. Hsieh, F.-C. Liu, K.-L. Yeh, W.-C. Tseng, S. W. Lu	Standby power reduction and SRAM cell optimization for 65nm technology.	ISQED	2009	DBLP DOI BibTeX RDF
1	Lei Zhao, Hui Xu, Naomi Seki, Yoshiki Saito, Yohei Hasegawa, Kimiyoshi Usami, Hideharu Amano	Cache Controller Design on Ultra Low Leakage Embedded Processors.	ARCS	2009	DBLP DOI BibTeX RDF
1	Jinhui Wang, Lei Zuo, Na Gong, Daming Gao, Shuqin Geng, Wang Zhang, Ligang Hou, Xiaohong Peng, Wuchen Wu	Estimation for Speed and Leakage Power of Dual Threshold Domino OR Based on Wavelet Neural Networks.	ISNN	2009	DBLP DOI BibTeX RDF	Dual threshold domino OR, Leakage power, Speed, Wavelet Neural Networks
1	Pedro Echeverría Aramendi, José L. Ayala, Marisa López-Vallejo	Power Considerations in Banked CAMs: A Leakage Reduction Approach.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Ja Chun Ku, Yehea I. Ismail	Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi	Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction.	PATMOS	2008	DBLP DOI BibTeX RDF
1	Maziar Goudarzi, Tohru Ishihara	Instruction cache leakage reduction by changing register operands and using asymmetric sram cells.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	asymmetric sram, leakage, instruction cache, register renaming
1	Anupama R. Subramaniam, Ritu Singhal, Chi-Chao Wang, Yu Cao	Design rule optimization of regular layout for leakage reduction in nanoscale design.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Longy O. Anyanwu, Jared Keengwe, Gladys A. Arome	Anonymity Leakage Reduction in Network Latency.	SCSS	2008	DBLP DOI BibTeX RDF
1	Masud H. Chowdhury, Juliana Gjanci, Pervez Khaled	Innovative power gating for leakage reduction.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Linfeng Pan, Minyi Guo, Yanqin Yang, Meng Wang, Zili Shao	A State-Based Predictive Approach for Leakage Reduction of Functional Units.	EUC	2008	DBLP DOI BibTeX RDF
1	Maziar Goudarzi, Tohru Ishihara, Hamid Noori	Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation.	HiPEAC	2008	DBLP DOI BibTeX RDF	process variation, cache memory, Leakage power, power reduction
1	Lei Cheng, Deming Chen, Martin D. F. Wong	A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Input vector control, gate replacement, leakage reduction
1	Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum	Multiple sleep mode leakage control for cache peripheral circuits in embedded processors.	CASES	2008	DBLP DOI BibTeX RDF	multiple sleep mode, peripheral circuits, cache, embedded processor, leakage power
1	Pei-Yu Huang, Chih-Kang Lin, Yu-Min Lee	Full-chip thermal analysis for the early design stage via generalized integral transforms.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Josef Haid, Bernd Zimek, Thomas Leutgeb, Thomas Kunemund	Impact of Leakage Current on Data Retention of RF-powered Devices During Amplitude-Modulation-based Communication.	DATE	2008	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	A Scalable Algorithmic Framework for Row-Based Power-Gating.	DATE	2008	DBLP DOI BibTeX RDF
1	Roberto Giorgi, Paolo Bennati	Reducing Leakage through Filter Cache.	DSD	2008	DBLP DOI BibTeX RDF
1	Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum	ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits.	ICCD	2008	DBLP DOI BibTeX RDF
1	Shuo Wang, Jianwei Dai, El-Sayed Hasaneen, Lei Wang 0003, Faquir Jain	Programmable threshold voltage using quantum dot transistors for low-power mobile computing.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Sudhakar Muddu, Puneet Sharma	Defocus-Aware Leakage Estimation and Control.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Yu Wang 0002, Ku He, Rong Luo, Hui Wang 0004, Huazhong Yang	Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Preetham Lakshmikanthan, Adrian Nunez	VCLEARIT: a VLSI CMOS circuit leakage reduction technique for nanoscale technologies.	SIGARCH Computer Architecture News	2007	DBLP DOI BibTeX RDF
1	Eric Wong, Jacob R. Minz, Sung Kyu Lim	Decoupling-Capacitor Planning and Sizing for Noise and Leakage Reduction.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Harmander Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka	Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Vishal Khandelwal, Ankur Srivastava	Active mode leakage reduction using fine-grained forward body biasing strategy.	Integration	2007	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Swamy Muddu, Puneet Sharma	Detailed placement for leakage reduction using systematic through-pitch variation.	ISLPED	2007	DBLP DOI BibTeX RDF	aCLV, through-pitch, leakage, lithography, detailed placement
1	Hushrav Mogal, Kia Bazargan	Microarchitecture floorplanning for sub-threshold leakage reduction.	DATE	2007	DBLP DOI BibTeX RDF
1	Yifan Zhu, Frank Mueller	DVSleak: combining leakage reduction and voltage scaling in feedback EDF scheduling.	LCTES	2007	DBLP DOI BibTeX RDF	scheduling, real-time systems, dynamic voltage scaling, leakage, feedback control
1	Olga Golubeva, Mirko Loghi, Enrico Macii, Massimo Poncino	Locality-driven architectural cache sub-banking for leakage energy reduction.	ISLPED	2007	DBLP DOI BibTeX RDF	banked cache, memory hierarchy, leakage reduction, architectural optimization
1	Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen	Cache leakage control mechanism for hard real-time systems.	CASES	2007	DBLP DOI BibTeX RDF	cache leakage control policy, hard real-time system
1	Yu Wang 0002, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie	Temperature-aware NBTI modeling and the impact of input vector control on performance degradation.	DATE	2007	DBLP DOI BibTeX RDF
1	Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram	Sizing and placement of charge recycling transistors in MTCMOS circuits.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Lin Yuan, Gang Qu	Simultaneous input vector selection and dual threshold voltage assignment for static leakage minimization.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Jie Gu, Hanyong Eom, Chris H. Kim	Sleep transistor sizing and control for resonant supply noise damping.	ISLPED	2007	DBLP DOI BibTeX RDF	resonant supply noise, sleep transistor, damping
1	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Timing-driven row-based power gating.	ISLPED	2007	DBLP DOI BibTeX RDF	row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
1	Wei Zhang 0002, Bramha Allu	Reducing branch predictor leakage energy by exploiting loops.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	compiler, Branch prediction, leakage energy
1	Kimiyoshi Usami	Overview on Low Power SoC Design Technology.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Houman Homayoun, Alexander V. Veidenbaum	Reducing leakage power in peripheral circuits of L2 caches.	ICCD	2007	DBLP DOI BibTeX RDF
1	Volkan Kursun, Sherif A. Tawfik, Zhiyu Liu	Leakage-Aware Design of Nanometer SoC.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Afshin Nourivand, Chunyan Wang, M. Omair Ahmad	An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson	Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays.	ISQED	2007	DBLP DOI BibTeX RDF
1	Sayeed A. Badrudduza, Giby Samson, Lawrence T. Clark	LCSRAM: A Leakage Controlled Six-transistor Static Random Access Memory Cell with Intrinsically High Read Stability.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester	Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Wei Pei, Wen-Ben Jone, Yiming Hu	Fault Modeling and Detection for Drowsy SRAM Caches.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Kazutoshi Kobayashi, Akihiko Higuchi, Hidetoshi Onodera	A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Johan Schoukens, Yves Rolain, Rik Pintelon	Leakage Reduction in Frequency-Response Function Measurements.	IEEE T. Instrumentation and Measurement	2006	DBLP DOI BibTeX RDF
1	Baozhen Yu, Michael L. Bushnell	A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	power cutoff, standby current, stacking, leakage current, dynamic power
1	Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. Massoud	An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	gate oxide tunneling, low power circuit design, subthreshold leakage, dual threshold voltage
1	Lian Li 0002, Jingling Xue	Trace-Based Data Cache Leakage Reduction at Link Time.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
1	Ja Chun Ku, Yehea I. Ismail	Area optimization for leakage reduction and thermal stability in nanometer scale technologies.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Koushik K. Das, Shih-Hsien Lo, Ching-Te Chuang	High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Harmander Deogun, Dennis Sylvester, Kevin J. Nowka	Fine grained multi-threshold CMOS for enhanced leakage reduction.	ISCAS	2006	DBLP DOI BibTeX RDF