Search results for "logic CAD"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Andrzej Hlawiczka, Michal Kopec	Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	serial seeding, linear hybrid cellular automata, n-cell CA register, p CdSR registers, cellular automata quasi shift register, PCASR, n-bit input sequence, logic testing, cellular automata, integrated circuit testing, automatic test pattern generation, application specific integrated circuits, polynomials, polynomial, logic CAD, cost, TPG, flip-flops, flip-flops, shift registers, pattern generators, integrated circuit economics
1	Lijian Li, Xiaoyang Yu, Cheng-Wen Wu, Yinghua Min	A waveform simulator based on Boolean process.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	waveform simulator, high performance integrated circuits, Boolean functions, logic CAD, timing behavior, Boolean process
1	Masayuki Tsukisaka, Takashi Nanya	A testable design for asynchronous fine-grain pipeline circuits.	PRDC	2000	DBLP DOI BibTeX RDF	asynchronous fine-grain pipeline circuits, dynamic gates, high-performance datapath design, pipeline latches, scan latch libraries, logic testing, logic CAD, SPICE, CMOS technology, scan path, SPICE simulation, testable design
1	Vi Chi Chan, David Lewis	Hierarchical partitioning for field-programmable systems.	ICCAD	1997	DBLP DOI BibTeX RDF	FPGA partitioning problems, circuit structures, field-programmable systems, partitioning tree, recursive bipartitioning algorithm, field programmable gate arrays, VLSI, quality, logic CAD, hierarchical partitioning
1	Zhanping Chen, Kaushik Roy, Tan-Li Chou	Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs.	ICCAD	1997	DBLP DOI BibTeX RDF	Monte Carlo based approach, maximum bounds, minimum bounds, power dissipation estimation, power sensitivity, primary inputs, signal properties, signal switching, uncertain specifications, logic CAD, CMOS logic circuits, power estimation, CMOS circuits, signal probability, statistical technique
1	Chi-Hong Hwang, Allen C.-H. Wu	A predictive system shutdown method for energy saving of event-driven computation.	ICCAD	1997	DBLP DOI BibTeX RDF	VLSI circuit design, delay overhead, event-driven computation, exponential-average approach, low delay penalties, pre-wakeup, prediction-miss correction, predictive system shutdown method, sleep mode operations, system-level power management, VLSI, finite state machine, logic CAD, energy saving, power saving, hit ratio, idle period
1	Patrick Vuillod, Luca Benini, Giovanni De Micheli	Generalized matching from theory to application.	ICCAD	1997	DBLP DOI BibTeX RDF	MCNC 91 benchmark suite, algorithmic optimization, generalized matching, library cells, multi-output network, post-mapping optimization, unconstrained delay minimization, logic CAD, power minimization, delay constraints, area minimization, Boolean relation
1	Karen Panetta Lentz, Elias S. Manolakos, Edward C. Czeck	A multiple domain environment for efficient simulation.	Annual Simulation Symposium	1997	DBLP DOI BibTeX RDF	multiple domain environment, efficient simulation, concurrent simulation methodology, digital logic experimentation, multiple experiment environment, independent experiments, parallel hardware, digital logic simulators, signature paths, multiple experiment algorithms, function list, dynamic interactions, exhaustive simulation problem, Multiple Stuck-at Fault simulations, logic CAD, coverage analysis, digital logic
1	Peggy B. K. Pang, Mark R. Greenstreet	Self-Timed Meshes Are Faster Than Synchronous.	ASYNC	1997	DBLP DOI BibTeX RDF	self-timed meshes, linear speed-up, per-processor performance, simulation, logic CAD
1	Sumit Roy, Prithviraj Banerjee	A Comparison of Parallel Approaches for Algebraic Factorization in Logic Synthesis. (PDF / PS)	IPPS	1997	DBLP DOI BibTeX RDF	algebraic factorization, circuit replication, totally independent factorization, L-shaped partitioning strategy, rectangle interaction, ex1010 circuit, sequential kernel extraction algorithms, SIS sequential circuit synthesis system, quality degradation, parallel algorithms, logic synthesis, logic CAD, circuit partitions, divide-and-conquer strategy
1	Elizabeth M. Rudnick, Janak H. Patel	Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation.	VLSI Design	1997	DBLP DOI BibTeX RDF	serial logic simulation bottleneck, parallel fault simulation, sequential circuit fault simulation algorithms, fault-partitioning approach, test set partitioning, parallel architectures, logic CAD, fault coverage, speedup, benchmark circuits
1	Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng	Incremental logic rectification.	VTS	1997	DBLP DOI BibTeX RDF	incremental logic rectification, incorrect combinational circuit, symbolic BDD techniques, sequence of partial corrections, circuits with multiple errors, general single-gate correction, structural correspondence, ISCAS85 benchmark circuits, error region pruning, specification, implementation, logic CAD, VLSI design, hybrid approach
1	Wanlin Cao, Dhiraj K. Pradhan	Sequential redundancy identification using recursive learning.	ICCAD	1996	DBLP DOI BibTeX RDF	ISCAS benchmarks, c-cycle redundancies, c-cycle redundant faults, redundancy identification algorithm, sequential redundancy identification, state transition information, uncontrollability analysis, logic CAD, FIRES, untestable faults, recursive learning
1	Julien Dunoyer, Nizar Abdallah, Pirouz Bazargan-Sabet	A symbolic simulation approach in resolving signals' correlation.	Annual Simulation Symposium	1996	DBLP DOI BibTeX RDF	signal resolution, signal correlation resolution, symbolic simulation approach, evaluation package, signal transition density, specification levels, first order clue, independent inputs, binary decision diagram concept, algorithms, VLSI, probability, logic CAD, digital simulation, design process, decision theory, circuit analysis computing, integrated circuit design, circuit CAD, digital circuits, subroutines, symbol manipulation, power dissipation, correlation methods, digital integrated circuits, signal probability, probabilistic approach, synthesis tools
1	Christoph Schaffer	Hierarchical architectural design, simulation and evaluation.	ECBS	1996	DBLP DOI BibTeX RDF	hierarchical architectural design, computer design evaluation, tool environment, multistrata systems, multilayer systems, performance evaluation, virtual machines, requirements, computer architecture, logic CAD, system engineering, computer simulation, system theory, system theory, trade-off analysis, architectural design decisions
1	Ayman I. Kayssi	Macromodeling C- and RC-loaded CMOS inverters for timing analysis.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	RC-loaded CMOS inverters, C-loaded CMOS inverters, series-resistor shunt-capacitor circuit, capacitive load case, input wave shape, transistor drive, timing, logic CAD, timing analysis, circuit analysis computing, CMOS logic circuits, circuit simulation, table lookup, macromodels, logic gates, lookup table, integrated circuit modelling
1	Come Rozon	On the Use of VHDL as a Multi-Valued Logic Simulator. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	multi-valued logic simulator, ternary circuits, simulation, VHDL, logic CAD, functionality, circuit analysis computing, hardware description languages, digital circuits, multivalued logic circuits, timing specifications
1	Prathima Agrawal, B. Narendran, Narayanan Shivakumar	Multi-way partitioning of VLSI circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	multi-way partitioning, hierarchical design processes, nets cut metric, VLSI, delays, economics, logic CAD, VLSI layout, integrated circuit layout, VLSI circuits, logic partitioning, minimisation of switching nets, average delay, integrated circuit manufacture, cost metric
1	Arun Balakrishnan, Srimat T. Chakradhar	Retiming with logic duplication transformation: theory and an application to partial scan.	VLSI Design	1996	DBLP DOI BibTeX RDF	logic duplication transformation, partial scan application, RLD configurations, RLD transformation, testability metrics, scan flip-flops, sequential circuit design, linear programming, timing, integer programming, logic design, sequential circuits, logic CAD, polynomial time algorithm, integer linear program, flip-flops, retiming, integrated circuit design, circuit CAD, integrated logic circuits, objective function
1	Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal	Parallel concurrent path-delay fault simulation using single-input change patterns.	VLSI Design	1996	DBLP DOI BibTeX RDF	concurrent path-delay fault simulation, single-input change patterns, singly-testable path-delay faults, random values, rising transitions, falling transitions, sixteen-valued algebra, machine word parallelism, ISCAS '85 benchmarks, ISCAS '89 benchmarks, parallel algorithms, fault diagnosis, logic testing, delays, Boolean functions, sequential circuits, logic CAD, circuit analysis computing, flip-flops, Boolean operations
1	Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal	Improving accuracy in path delay fault coverage estimation.	VLSI Design	1996	DBLP DOI BibTeX RDF	fault coverage estimation, simulated vector pair, exact fault simulation, fixed-length path-segments, fan-in branches, fan-out branches, flagged path-segments, segment lengths, combinational paths, graph theory, fault diagnosis, logic testing, delays, combinational circuits, logic CAD, circuit analysis computing, path delay fault, approximate methods, CPU time
1	Jaswinder Pal Singh, A. Kumar, Sanjeev Kumar	A multiplier generator for Xilinx FPGAs.	VLSI Design	1996	DBLP DOI BibTeX RDF	multiplier generator, Xilinx FPGAs, LUT based FPGA, sequential designs, combinational designs, pipelined designs, IDEAS synthesis system, XC3000 family, XC4000 family, dedicated carry logic, XACT tool, XBLOX tool, field programmable gate arrays, high level synthesis, sequential circuits, combinational circuits, digital arithmetic, logic CAD, pipeline processing, integrated circuit design, circuit CAD, table lookup, multiplying circuits, module generator, carry logic, multiplier designs
1	S. Sundaram, Lalit M. Patnaik	Distributed logic simulation: time-first evaluation vs. event driven algorithms.	VLSI Design	1996	DBLP DOI BibTeX RDF	distributed logic simulation, time-first evaluation algorithm, event driven algorithm, digital circuit simulation, distributed simulation algorithms, parallel algorithms, parallel processing, VLSI, logic CAD, circuit analysis computing, integrated logic circuits, VLSI circuits, parallel logic simulation
1	Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda	Scan insertion criteria for low design impact.	VTS	1996	DBLP DOI BibTeX RDF	scan insertion criteria, design impact, flip-flop ordering, capacitance constraints, layout information, Italtel Design Environment, logic testing, integrated circuit testing, sequential circuits, automatic testing, application specific integrated circuits, logic CAD, flip-flops, integrated circuit design, power dissipation, partial scan, design flow, boundary scan testing, scan chain, capacitance, full scan
1	Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska	Design and performance of CMOS TSPC cells for high speed pseudo random testing.	VTS	1996	DBLP DOI BibTeX RDF	CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists
1	Eric Q. Kang, Eugene Shragowitz	Generic fuzzy logic CAD development tool.	ASP-DAC	1995	DBLP DOI BibTeX RDF
1	Pranav Ashar, Sharad Malik	Fast functional simulation using branching programs.	ICCAD	1995	DBLP DOI BibTeX RDF	compiled code simulation, cycle-based functional simulation, fast functional simulation, functional delay-independent logic simulation, levelized compiled-code, switch level functional simulation, synchronous digital systems, Boolean functions, system design, logic design, logic CAD, decision theory, circuit analysis computing, benchmark circuits, branching programs
1	Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok	Be careful with don't cares.	ICCAD	1995	DBLP DOI BibTeX RDF	specifications, logic design, logic CAD, correctness, replaceability, don't cares
1	Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz	LOT: logic optimization with testability-new transformations using recursive learning.	ICCAD	1995	DBLP DOI BibTeX RDF	EX-OR gates, logic optimization with testability, multi-level logic circuits, tstfx, logic design, combinational circuits, logic CAD, gate level, random-pattern testability, recursive learning
1	Tan-Li Chou, Kaushik Roy	Statistical estimation of sequential circuit activity.	ICCAD	1995	DBLP DOI BibTeX RDF	Markov chain theory, sequential circuit activity, sequential logic circuits, signal activity, transient problem, sequential circuits, logic CAD, Monte Carlo, Monte Carlo methods, Monte Carlo technique
1	Amir H. Farrahi, Majid Sarrafzadeh	System partitioning to maximize sleep time.	ICCAD	1995	DBLP DOI BibTeX RDF	Geo-Part, exploitable sleep time, geometric partitioning heuristic, low-power synthesis, memory refresh circuitry, segment tree data structure, VLSI, logic CAD, integrated circuit design, circuit CAD, circuit optimisation, logic partitioning, partitioning problem, system partitioning
1	Joel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Yosinatori Watanabe	A delay model for logic synthesis of continuously-sized networks.	ICCAD	1995	DBLP DOI BibTeX RDF	algebraic factorings, computational simplicity, continuous device sizing, continuously-sized networks, electrical noise, library cell, mapped network, logic design, logic synthesis, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, delay model, power constraints
1	Sasan Iman, Massoud Pedram	Two-level logic minimization for low power.	ICCAD	1995	DBLP DOI BibTeX RDF	Power Prime Implicants, low power two-level logic minimization, minimum covering problem, minimum power solution, static CMOS circuits, logic design, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, circuit optimisation, minimisation of switching nets
1	Anmol Mathur, K. C. Chen, C. L. Liu	Re-engineering of timing constrained placements for regular architectures.	ICCAD	1995	DBLP DOI BibTeX RDF	Xilinx 3000 FPGA architecture, engineering requirements, regular architectures, timing constrained placements reengineering, FPGAs, field programmable gate arrays, logic CAD, program debugging, systems re-engineering, logic arrays, design flow, gate arrays, design specification, timing performance, design cycle, design debugging
1	Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia	Fast discrete function evaluation using decision diagrams.	ICCAD	1995	DBLP DOI BibTeX RDF	address lookups, cycle-based logic simulation, decision-diagram based function evaluation, fast discrete function evaluation, latch ports, orders-of-magnitude potential speedup, output ports, logic design, memory hierarchy, logic CAD, decision theory, circuit analysis computing, memory bandwidth, table lookup, digital circuits, logic simulators, logic function, function evaluation, multi-valued decision diagrams
1	Sudip K. Nag, Rob A. Rutenbar	Performance-driven simultaneous place and route for island-style FPGAs.	ICCAD	1995	DBLP DOI BibTeX RDF	Xilinx 4000-series FPGAs, island-style FPGAs, performance-driven simultaneous placement/routing, place and route tools, FPGAs, field programmable gate arrays, logic CAD, network routing, circuit layout CAD, industrial designs, circuit layout
1	Irith Pomeranz, Sudhakar M. Reddy	Functional test generation for delay faults in combinational circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	gate-level realizations, logic testing, delays, test generation, test generators, combinational circuits, fault simulated, logic CAD, delay faults, functional fault model, functional test generation
1	Sachin S. Sapatnekar, Weitong Chuang	Power vs. delay in gate sizing: conflicting objectives?	ICCAD	1995	DBLP DOI BibTeX RDF	power-delay tradeoffs, short-circuit power, logic design, logic CAD, integrated circuit design, circuit CAD, optimization problem, circuit optimisation, gate sizing, convex programming, CMOS digital integrated circuits, dynamic power
1	Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn	Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization.	ICCAD	1995	DBLP DOI BibTeX RDF	acyclic pipelines, area-delay tradeoff, clock skew optimization, cycle-borrowing, logic design, combinational circuits, logic CAD, pipeline processing, circuit CAD, circuit optimisation, gate sizing, logic gates, pipelined circuits, timing specifications
1	Hirendu Vaishnav, Massoud Pedram	Delay optimal partitioning targeting low power VLSI circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	clustering, VLSI, partitioning, logic CAD, circuit CAD, integrated logic circuits, power dissipation, VLSI circuits, logic partitioning, delay optimal
1	Pai H. Chou, Ross B. Ortega, Gaetano Borriello	The Chinook hardware/software co-synthesis system.	ISSS	1995	DBLP DOI BibTeX RDF	Chinook hardware/software co-synthesis system, custom logic, design co-simulation, design time constraints, embedded controller design, error-prone tasks, function migration, interface hardware, interface software, system components integration, real-time systems, software tools, logic design, microprocessors, logic CAD, microcontrollers, computer-aided design tools
1	Youngmin Hur, Stephen A. Szygenda	Special purpose array processor for digital logic simulation.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	special purpose array processor, digital logic simulation, large VLSI circuits, compute-intensive tasks, digital analysis, time driven array processor, massively parallel processing element, compiled event-driven technology, nominal transport delay timing analysis, delay time order, levelized circuit, massively parallel PE array, MARS accelerator, VLSI, parallel architectures, delays, timing, fault simulation, logic CAD, digital simulation, circuit analysis computing, special purpose computers, SIMD architecture, hardware cost
1	Glenn Jennings	Accurate ternary-valued compiled logic simulation of complex logic networks by OTDD composition.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	circuit diagrams, ternary-valued compiled logic simulation, complex logic networks, OTDD composition, combinational U inaccuracies, reconvergent fanout, Kleenean strong ternary logic, Ordered Ternary Decision Diagram, standard ISCAS 85 benchmarks, performance evaluation, logic CAD, digital simulation, circuit analysis computing, ternary logic, incompletely-specified functions
1	Krishna Kant	Performance of internal overload controls in large switches.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	internal overload control performance, large switches, switch sizes, call capacity, voice circuits, overload performance, network integrity, peripheral scanning schemes, scheduling, performance evaluation, virtual machines, logic CAD, circuit analysis computing, simulation model, service integrity, buffer sizes, switching circuits
1	C. Rominger, Jean Claude Geffroy	Hazard analysis of structured sequential systems.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	structured sequential systems, time uncertainties, asynchronous sequential systems, nondeterministic phenomena, simulation method, structured systems, fault diagnosis, CAD, logic testing, timing, sequential circuits, logic CAD, asynchronous circuits, digital simulation, time analysis, circuit analysis computing, hazard analysis, asynchronous sequential logic
1	Scott Hauck, Gaetano Borriello	An evaluation of bipartitioning techniques.	ARVLSI	1995	DBLP DOI BibTeX RDF	bipartitioning techniques, VLSI, logic CAD, integrated circuit design, circuit CAD, logic partitioning, logic partitioning, VLSI CAD
1	Louis Monier, Ramsey W. Haddad, Jeremy Dion	Recursive layout generation.	ARVLSI	1995	DBLP DOI BibTeX RDF	BiCMOS digital integrated circuits, recursive layout generation, layout directives, netlist description, hand-drawn layout, synthesized layout, overall layout, dense VLSI, VLSI, logic CAD, circuit layout CAD, microprocessor chips, microprocessor chips, VLSI chips, seamless integration
1	Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng	Automatic synthesis of gate-level timed circuits with choice.	ARVLSI	1995	DBLP DOI BibTeX RDF	gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates
1	Sanjay Rekhi, J. Donald Trotter	HAL: heuristic algorithms for layout synthesis.	ARVLSI	1995	DBLP DOI BibTeX RDF	layout synthesis, graph theory based algorithms, leaf cells, common poly gates, 1-1/2-d layout style, common circuit nodes, transistor sets, symbolic layouts, static dual type, static CMOS circuitry, pullup network, pulldown network, dynamic logic styles, graph theory, network topology, logic CAD, heuristic algorithms, circuit layout CAD, CMOS logic circuits, CMOS circuits, GENIE, run time efficient, layout area
1	Chris J. Myers, Peter A. Beerel, Teresa H. Y. Meng	Technology mapping of timed circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	gate library, C-elements, ATACS, timing, logic design, logic CAD, asynchronous circuits, asynchronous circuits, timing information, AND gates, synthesis tool, OR gates, timed circuits
1	Dhruva R. Chakrabarti, Ajai Jain	An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	hierarchical test generation technique, repetitive subcircuits, hierarchical testing algorithm, bus fault model, high-level subcircuits, high level incompatibility, test generation time, complete fault coverage, computational complexity, fault diagnosis, logic testing, high level synthesis, design for testability, design for testability, ATPG, combinational circuits, combinational circuits, logic CAD, automatic test software, signal flow graphs, state transition graph
1	Hiroshi Date, Michinobu Nakao, Kazumi Hatayama	A parallel sequential test generation system DESCARTES based on real-valued logic simulation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	parallel sequential test generation system, DESCARTES, real-valued logic simulation, redundant fault identification program, algorithmic test generation program, ISCAS '89 benchmark sequential circuits, distributed processing environment oriented system, concurrent accelerative test generation, parallel algorithms, computational complexity, VLSI, fault diagnosis, logic testing, redundancy, design for testability, sequential circuits, logic CAD, VLSI design, stuck-at faults, automatic test generation, synchronous sequential circuits, automatic test software, test quality
1	Eiji Harada, Janak H. Patel	Overhead reduction techniques for hierarchical fault simulation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	overhead reduction techniques, hierarchical fault simulation, simulation overhead, concurrent method, multi-list-traversal method, one-pass fault simulation strategy, characteristic vectors, contiguous concurrent machines, ISCAS benchmark circuits, fault ordering, logic test sequences, fault diagnosis, logic testing, combinational circuits, logic CAD, digital simulation, circuit analysis computing, concurrent engineering, multivalued logic circuits, ULSI, ULSI
1	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Test sequence compaction by reduced scan shift and retiming.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	reduced scan shift, full scan designed circuits, computational complexity, logic testing, transformation, timing, design for testability, sequential circuits, sequential circuit, logic CAD, flip-flops, flip-flops, retiming, computing time, test length, test sequence generation, test sequence compaction
1	Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto	Universal test complexity of field-programmable gate arrays.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	universal test complexity, arbitrary logic circuits, sequential loading, random access loading, programming schemes, block-sliced loading, configuration memory cells, field programmable gate arrays, field-programmable gate array, computational complexity, fault diagnosis, logic testing, design for testability, fault model, logic CAD, table lookup, look-up tables, automatic test software, C-testable
1	Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	A cellular array designed from a Multiple-valued Decision Diagram and its fault tests.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	multiple-valued decision diagram, fault tests, testable cellular arrays, VLSI, fault diagnosis, logic testing, logic CAD, cellular arrays, cellular array, multivalued logic circuits, switch functions, multiple stuck-at faults
1	Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck	Deterministic test generation for non-classical faults on the gate level.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST
1	S. Nandi, Parimal Pal Chaudhuri	Theory and applications of cellular automata for synthesis of easily testable combinational logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	testable combinational logic, combinational logic blocks, test machine, data path synthesis phase, autonomous mode, aliasing error probability, associated lines, test application overheads, test parallelism, simultaneous testing, multiple combinational modules, graph theory, fault diagnosis, logic testing, high level synthesis, test generation, cellular automata, cellular automata, design for testability, combinational circuits, logic CAD, stuck-at faults, shift registers, cost effectiveness, registers, test vectors, test responses, state transition graph
1	Sandeep Pagey	Fast functional testing of delay-insensitive circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	four-phase handshake signalling, Martin's method, distributed circuit, OR/C blocks, generation of test sequences, program flow graph, logic testing, delays, design for testability, logic CAD, asynchronous circuits, functional testing, testing time, self-timed circuits, delay-insensitive circuits, OR gates
1	Sandeep Pagey, Ajay Khoche, Erik Brunvand	DFT for fast testing of self-timed control circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	fast testing, self-timed control circuits, execution paths, simultaneous testing, OCCAM based circuit compiler, OCCAM program, self-timed macro-modules, modified modules, macromodules, fault diagnosis, logic testing, delays, design for testability, DFT, logic CAD, asynchronous circuits, translation, program compilers, automatic test software
1	Hiroaki Ueda, Kozo Kinoshita	Low power design and its testability.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	power reduction tool, power dissipation factor, testability parameters, fault diagnosis, logic testing, delays, probability, design for testability, low power design, logic CAD, testability, fault location, stuck-at faults, CMOS logic circuits, delay faults, CMOS circuit, PORT, automatic test software, redundant faults, transition probability
1	Wen Ching Wu, Chung-Len Lee, Jwu E. Chen	Identification of robust untestable path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	robust untestable path delay faults, path reconvergence of fanouts, ISCAS 85' circuits, total path delay faults, six-valued logic, propagation graph, ROUNTEST program, fault diagnosis, logic testing, delays, partitioning, ATPG, combinational circuits, combinational circuits, automatic testing, logic CAD, multivalued logic, logic partitioning, signal flow graphs, fault identification
1	Shiyi Xu, Gercy P. Dias	Testability forecasting for sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	testability forecasting, transitive closure algorithm, number of test patterns, computational complexity, fault diagnosis, logic testing, logic testing, statistical analysis, design for testability, sequential circuits, sequential circuits, logic CAD, fault coverage, regression models, automatic test software, CPU time, test generation algorithms
1	Seiken Yano	Unified scan design with scannable memory arrays.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	unified scan design, scannable memory arrays, single scan path, scan operation time, scannable register file, fault diagnosis, design for testability, design-for-testability, automatic testing, logic CAD, flip-flops, flip-flops, arrays, shift registers, integrated memory circuits
1	Garth Baulch, David Hemmendinger, Cherrice Traver	Analyzing and verifying locally clocked circuits with the concurrency workbench.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	locally clocked circuits, concurrency workbench, synchronous computational elements, concurrent system modelling, CCS process algebra, formal verification, timing, logic design, process algebra, logic CAD, asynchronous circuits, asynchronous circuits, circuit analysis computing, asynchronous communication
1	Vincenzo Catania, N. Fiorito, Michele Malgeri, Marco Russo	A soft computing approach to hardware software codesign.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	soft computing approach, partitioning phase, genetic algorithms, genetic algorithms, fuzzy logic, fuzzy logic, logic CAD, computer aided software engineering, hardware/software codesign
1	Joseph L. Ganley, James P. Cohoon	Thumbnail rectilinear Steiner trees.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	full-set decomposition algorithm, minimum-length set, thumbnail rectilinear Steiner tree problem, VLSI placement algorithms, geometric partitioning, field programmable gate arrays, field-programmable gate arrays, VLSI, dynamic programming, network topology, logic CAD, trees (mathematics), network routing, circuit layout CAD, global routing, line segments
1	Stanley Habib, Quan Xu	Technology mapping algorithms for sequential circuits using look-up table based FPGAS.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	technology mapping algorithms, FPGAS, routing results, adjacent combinational parts, field programmable gate arrays, delays, sequential circuits, sequential circuits, logic CAD, network routing, flip-flops, flip-flops, circuit layout CAD, table lookup, time delay, look-up table
1	Uwe Hinsberger, Reiner Kolla	Optimal technology mapping for single output cells.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	optimal technology mapping, single output cells, DAG-mapping, minimum delay mapping, duplication-free mapping, logic duplication, AT-tradeoffs, LUT-FPGAs, field programmable gate arrays, delays, Boolean functions, Boolean functions, logic CAD, table lookup, cost functions, circuit optimisation, lookup table
1	Harry Hollander, Bradley S. Carlson, Toby D. Bennett	Synthesis of SEU-tolerant ASICs using concurrent error correction.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	radiation hardening (electronics), SEU-tolerant ASIC synthesis, single error correction/double error detection Hamming code, delay overhead, memory element set partitioning, error correction codes, sequential circuits, sequential circuit, application specific integrated circuits, logic CAD, circuit layout CAD, single event upsets, logic partitioning, Hamming codes, fault tolerant design, area overhead, memory elements, design experiments, concurrent error correction
1	Dimitrios Karayiannis, Spyros Tragoudas	Uniform area timing-driven circuit implementation.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	circuit module, cell library, input-output paths, overall area, timing-driven circuit implementation, computational complexity, heuristics, CAD, delays, timing, sequential circuits, sequential circuits, NP-hard, directed graphs, combinational circuits, combinational circuits, logic CAD, polynomial time algorithm, directed acyclic graphs, circuit CAD, cellular arrays, propagation delay
1	Enrico Macii, Massimo Poncino	Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	worst-case power consumption, symbolic neural networks, gate level description, symbolic domain, algebraic decision diagrams, graph specification, delays, combinational circuits, combinational circuits, logic CAD, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, energy dissipation
1	Enric Pastor, Jordi Cortadella, Oriol Roig	A new look at the conditions for the synthesis of speed-independent circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	gate-level synthesis, gate library constraint, fan-in reduction, VLSI, logic design, logic CAD, integrated circuit design, circuit CAD, integrated logic circuits, circuit optimisation, optimization techniques, speed-independent circuits
1	Frank Poirot, Gerard Tarroux, Ramine Roane	Optimization using implicit techniques for industrial designs.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	implicit techniques, Boolean functions, Boolean functions, logic synthesis, logic CAD, binary decision diagrams, hardware description languages, hardware description languages, industrial designs, circuit optimisation, optimization techniques, design complexity
1	Michael Sheliga, Edwin Hsing-Mean Sha	Bus minimization and scheduling of multi-chip systems.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	bus minimization, multi-chip module design, scheduling, scheduling, logic CAD, polynomial time algorithm, circuit layout CAD, multichip modules, signal flow graphs, signal flow graphs, algorithm efficiency
1	Nestoras Tzartzanis, William C. Athas	Design and analysis of a low-power energy-recovery adder.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	energy-recovery adder, frequency range, VLSI, VLSI, delays, logic CAD, circuit analysis computing, integrated circuit design, adders, CMOS logic circuits, CMOS logic circuits, circuit CAD, SPICE, SPICE simulation, delay time, energy dissipation
1	M. J. van der Westhuizen, R. G. Harley, D. C. Levy, D. R. Woodward	Using EDIF for software generation.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	EDIF, parallel microprocessors, codesign methods, hardware development tools, real-time parallel C code, FPGA, parallel programming, simulated annealing, simulated annealing, software tools, software tool, logic CAD, circuit CAD, C language, scheduling theory, software generation, development systems
1	Jae-Tack Yoo, Erik Brunvand, Kent F. Smith	Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	automatic rapid prototyping, semicustom VLSI circuits, Actel FPGAs, cell-matrix based environment, synchronous pipelined version, asynchronous pipelined version, field programmable gate arrays, field programmable gate arrays, VLSI, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, array multiplier, CMOS IC
1	Habib Youssef, Sadiq M. Sait, Khaled Nassar, Muhammad S. T. Benten	Performance driven standard-cell placement using the genetic algorithm.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	connection length, timing-driven placer, /spl alpha/-criticality, delay performance improvement, genetic algorithms, genetic algorithm, delays, timing, logic CAD, circuit layout CAD, cellular arrays, integrated circuit layout, critical paths, area, propagation delays, wire length, timing performance, IC design, standard-cell placement
1	Zijian Zhou, Xiaoyu Song, Francisco Corella, Eduard Cerny, Michel Langevin	Partitioning transition relations efficiently and automatically.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	automatic partitioning, state transition relations, abstract implicit state enumeration procedure, automatic verification method, graph theory, finite state machines, logic CAD, state estimation, logic partitioning, extended finite state machines, register transfer level designs, multiway decision graphs
1	Jay K. Adams, John Alan Miller, Donald E. Thomas	Execution-time profiling for multiple-process behavioral synthesis. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	execution-time profiling, multiple-process behavioral synthesis, back-annotating, source description, behavioral simulation model, annotated behavioral simulation, high level synthesis, high-level synthesis, timing, timing, logic CAD, digital simulation, circuit analysis computing, hardware design, software profiling, register-transfer level model
1	Minesh B. Amin, Bapiraju Vinnakota	Data parallel fault simulation. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	data parallel fault simulation, compute intensive problem, fault simulation time, fault set partitioning technique, low cost parallel resource, logic gate level, parallel programming, fault diagnosis, logic testing, logic CAD, circuit analysis computing, workstations, logic partitioning, multiple processors
1	Anand Chavan, Shiu-Kai Chin, Shahid Ikram, Jang Dae Kim, Juin-Yeu Zu	Extending VLSI design with higher-order logic. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	Cambridge Higher-Order Logic theorem-prover, microprogram sequencer, Am2910, VLSI, formal verification, formal verification, logic testing, theorem proving, logic design, logic CAD, VLSI design, higher-order logic, theorem-prover, design environment, instruction-set architecture, VLSI CAD
1	Franco Fummi, Donatella Sciuto, M. Serro	Synthesis for testability of large complexity controllers. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	large complexity controllers, industrial design environments, top-down methodology, hierarchical descriptions, irredundant circuits, optimized gate-level descriptions, testable descriptions, specification, high level synthesis, finite state machines, finite state machines, design for testability, design for testability, VHDL, automatic testing, logic CAD, hardware description languages, FSM, synthesis for testability, logic gates
1	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	design for hierarchical testability, gate-level sequential test generation, controller data path circuits, large data path bit-widths, minimal test hardware, system-level test set, logic testing, high level synthesis, high level synthesis, integrated circuit testing, design for testability, design for testability, automatic testing, logic CAD, integrated circuit design, behavioral synthesis, logic gates, register-transfer level design, RTL circuits
1	Glenn Holt, Akhilesh Tyagi	EPNR: an energy-efficient automated layout synthesis package. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	EPNR, energy-efficient automated layout synthesis package, MCNC Logic Synthesis '93 benchmarks, VPNR, VLSI energy minimization problems, VLSI, logic testing, placement, logic CAD, circuit layout CAD, global routing, logic arrays, standard cells, channel routing
1	Jainendra Kumar, Noel R. Strader, Jeff Freeman, Michael Miller	Emulation verification of the Motorola 68060. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	emulation verification, Motorola 68060, hardware logic emulation, configurable hardware, circuit verification, pseudo-random verification vectors, software application programs, formal verification, microprocessors, reconfigurable architectures, logic CAD, digital simulation, circuit analysis computing, RTL, hardware description languages, hardware description language, microprocessor chips, HDL, gate-level
1	Manish Pandey, Alok Jain, Randal E. Bryant, Derek L. Beatty, Gary York, Samir Jain	Extraction of finite state machines from transistor netlists by symbolic simulation. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	finite state machine extraction, transistor netlists, clock level finite state machines, gate level representation, circuit clocking, output timing, simulation patterns, next state, output function, equivalent FSM, static storage structures, time multiplexed inputs, time multiplexed outputs, finite state machines, logic design, logic CAD, circuit analysis computing, FSMs, symbolic simulation, symbolic simulator, Ordered Binary Decision Diagrams
1	Gitanjali Swamy, Robert K. Brayton, Vigyan Singhal	Incremental methods for FSM traversal. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	FSM traversal, formal verification, formal verification, finite state machines, finite state machine, logic design, directed graphs, logic CAD, incremental algorithms, digital systems, reachable states, incremental methods
1	Kaushik De, John A. Chandy, Sumit Roy, Steven Parkes, Prithviraj Banerjee	Parallel algorithms for logic synthesis using the MIS approach. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	combinational logic synthesis, VLSI system design, ProperMIS, portable parallel algorithm, parallel algorithms, parallel algorithms, parallel architectures, logic design, combinational circuits, logic synthesis, logic CAD
1	Timothy J. McBrayer, Philip A. Wilsey	Process combination to increase event granularity in parallel logic simulation. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	event granularity, VHDL description, parallel processing, logic CAD, circuit analysis computing, logic circuits, logic circuits, symmetric multiprocessors, logic simulation, digital system design, parallel logic simulation, parallel logic simulators
1	Luben Boianov, Innes Jelly	Distributed logic circuit simulation on a network of workstations.	PDP	1995	DBLP DOI BibTeX RDF	logic circuit simulation, distributed digital logic simulation, logical simulation algorithms, distributed processing, logic CAD, digital simulation, Parallel Virtual Machine, digital circuits
1	Arun Balakrishnan, Srimat T. Chakradhar	Partial scan design for technology mapped circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	technology mapped circuits, scan flip-flops selection, multiple memory elements, library block, integer linear program formulation, production VLSI circuits, VLSI, graph theory, linear programming, design for testability, integer programming, logic design, logic CAD, VLSI design, flip-flops, integrated circuit design, circuit CAD, integrated logic circuits, functional specifications, partial scan design
1	U. K. Bhattacharyya, I. Sen Gupta, S. Shyama Nath, P. Dutta	PLA based synthesis and testing of hazard free logic.	VLSI Design	1995	DBLP DOI BibTeX RDF	PLA based synthesis, hazard free logic, multilevel network, supergate partitioning, multi-output circuits, testing, logic testing, design for testability, combinational circuits, logic CAD, testability, programmable logic arrays, logic partitioning, combinational networks, hazards and race conditions
1	Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli	A new switching-level approach to multiple-output functions synthesis.	VLSI Design	1995	DBLP DOI BibTeX RDF	switching-level, multiple-output functions synthesis, transistor level, randomly generated functions, logic CAD, timing constraints, circuit layout CAD, CMOS logic circuits, multivalued logic circuits, integrated circuit layout, minimisation of switching nets, area minimization, figures of merit
1	Manjit Borah, Mary Jane Irwin, Robert Michael Owens	Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering.	VLSI Design	1995	DBLP DOI BibTeX RDF	power consumption minimisation, static CMOS circuits, input reordering, high fan-out gates, power constrained module generator, PowerSizer, logic CAD, circuit layout CAD, CMOS logic circuits, logic circuits, minimisation, arithmetic circuits, circuit optimisation, integrated circuit layout, transistor sizing
1	William L. Bradley, Ranga Vemuri	Transformations for functional verification of synthesized designs.	VLSI Design	1995	DBLP DOI BibTeX RDF	low-level functional verification, synthesized designs, clocking mechanisms, provably equivalent model, hierarchical network of modules, reduced state set, de-phase transform, align transform, algorithm, formal verification, transforms, transforms, logic CAD, clocks, hierarchical system, reachable states
1	Srimat T. Chakradhar	Optimum retiming of large sequential circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	optimum retiming, large sequential circuits, unit delay model, optimum clock period, path graph, VLSI, linear programming, delays, timing, integer programming, sequential circuits, logic CAD, integer linear program, flip-flops, circuit CAD, fast algorithm, integrated logic circuits, circuit optimisation, VLSI circuits, linear program relaxation
1	Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri	Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture.	VLSI Design	1995	DBLP DOI BibTeX RDF	multi-output logic module, cellular automata array, design turn-around time, field programmability, rapid circuit realization, logic blocks, AND-XOR based logic, library based technology mapping technique, MCNC benchmarks, field programmable gate arrays, VLSI, cellular automata, logic CAD, testability, technology mapping, multivalued logic circuits, FPGA architecture
1	Alain Guyot, Luis A. Montalvo, A. Houelle, Habib Mehrez, N. Vaucher	Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers.	VLSI Design	1995	DBLP DOI BibTeX RDF	layout synthesis, radix-2 dividers, pseudo-radix-4 dividers, redundant number notation, carry-propagation-free addition/subtraction, VLSI, logic CAD, circuit layout CAD, CMOS logic circuits, VLSI implementation, integrated circuit layout, redundant number systems, dividing circuits, digit-recurrence division