Search results for "logic circuits"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
5	José Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh	Optimization of combinational and sequential logic circuits for low power using precomputation.	ARVLSI	1995	DBLP DOI BibTeX RDF	sequential logic circuits, low power optimisation, logic optimization technique, precomputation architectures, logic synthesis methods, transmission gates, transparent latches, switching activity reduction, power dissipation reduction, VLSI, logic design, sequential circuits, combinational circuits, integrated circuit design, CMOS logic circuits, circuit optimisation, precomputation, combinational logic circuits, clock cycle
5	Takao Waho	Resonant Tunneling Transistor and Its Application to Multiple-Valued Logic Circuits. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	resonant tunnelling transistors, resonant tunneling transistors, multiple-valued logic circuits, multiple stable states, coupled-quantum-well, monostable-multistable logic circuits, multivalued logic circuits, resonant tunneling diodes, circuit stability
4	Alvernon Walker, Algernon P. Henry, Parag K. Lala	An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF	bridging faults detection, CMOS domino logic circuits, dynamic power supply current monitoring, CMOS logic circuits, transient current
4	Niraj K. Jha	Multiple Stuck-Open Fault Detection in CMOS Logic Circuits.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	multiple stuck-open fault detection, logic testing, CMOS logic circuits, logic circuits, CMOS integrated circuits, integrated logic circuits, two-pattern tests
3	Hao Chen, Jie Han	Stochastic computational models for accurate reliability evaluation of logic circuits.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	stochastic computation, stochastic computational model, fault tolerance, logic circuits, reliability evaluation
3	Zhifang Li, Wenjian Luo, Xufa Wang	A Stepwise Dimension Reduction Approach to Evolutionary Design of Relative Large Combinational Logic Circuits.	ICES	2008	DBLP DOI BibTeX RDF	Evolutionary Algorithm, Evolvable Hardware, Combinational Logic Circuits
3	Wieland Fischer, Berndt M. Gammel	Masking at Gate Level in the Presence of Glitches.	CHES	2005	DBLP DOI BibTeX RDF	random masking, masked logic circuits, Cryptanalysis, side-channel attacks, DPA, power analysis, logic circuits, digital circuits, masking, glitches
3	Valeriy Vyatkin	Event-Driven Traversal of Logic Circuits for Re-evaluation of Boolean Functions in Reactive Systems.	Ershov Memorial Conference	2003	DBLP DOI BibTeX RDF	Boolean computation, Logic circuits, Incremental computation
3	Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Amin Ahsan Ali, Mohammad Musa Salehin Akon	A Technique for Logic Design of Voltage-Mode Pass Transistor Based Multi-Valued Multiple-Output Logic Circuits. (PDF / PS)	ISMVL	2003	DBLP DOI BibTeX RDF	Multi-valued logic (MVL), TMOS logic circuits, Support set, Residual, Literals
3	Ki-Seok Chung, Taewhan Kim, C. L. Liu	G-vector: A New Model for Glitch Analysis in Logic Circuits.	VLSI Signal Processing	2001	DBLP DOI BibTeX RDF	synthesis, power estimation, logic circuits, glitches
3	Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang	Charge sharing fault analysis and testing for CMOS domino logic circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	charge sharing fault analysis, CMOS domino logic circuits, domino logic design, sensitivity measurement, domino gate, fault diagnosis, logic testing, delays, delay, automatic testing, CMOS logic circuits, logic gates, test vectors
3	Seiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy	Enhanced untestable path analysis using edge graphs.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	untestable path analysis, edge graphs, partial path sensitization, edge graph, logic testing, logic circuits, logic circuits, path delay fault testing
3	Georgios I. Papadimitriou, Amalia N. Miliou, Andreas S. Pomportsis	Optical Logic Circuits: A New Approach to the Control of Fiber Optic LANs. (PDF / PS)	LCN	1998	DBLP DOI BibTeX RDF	WDM Star Networks, Centralized Protocols, Optical Logic Circuits, Optically Controlled Optical Networks
3	Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David Blaauw	Library-less synthesis for static CMOS combinational logic circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	library-less synthesis, resynthesized circuits, size-wise CMOS circuit optimization, static CMOS combinational logic circuits, structural CMOS circuit optimization, transistor level technique, CMOS logic circuits, design space, optimal design, circuit performance
3	Mostafa H. Abd-El-Barr, M. N. Hasan	New MVL-PLA Structures Based on Current-Mode CMOS Technology. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	MVL-PLA structures, current-mode CMOS technology, PLA structures, min, tsum, constants, r-valued one-variable functions, type-C PLA, type-A PLA, type-B PLA, cyclic generator blocks, programmable logic arrays, programmable logic arrays, CMOS logic circuits, cycle, multivalued logic circuits, multivalued logic circuits, current-mode logic
3	Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen	Fanout fault analysis for digital logic circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	fanout fault analysis, digital logic circuits, combinational benchmark circuits, sequential benchmark circuits, target faults, fault diagnosis, logic testing, test generation, sequential circuits, combinational circuits, fault simulation, fault collapsing
3	Alessandro Bogliolo, Maurizio Damiani, Piero Olivo, Bruno Riccò	Reliability evaluation of combinational logic circuits by symbolic simulation.	VTS	1995	DBLP DOI BibTeX RDF	mcnc benchmark circuits, fault-tolerant combinational logic circuits, circuit functionality, fault indicators, control variables, BDD-based symbolic simulation, undetectable multiple faults, VLSI, VLSI, combinational circuits, logic CAD, digital simulation, circuit analysis computing, reliability evaluation, integrated circuit reliability
3	William C. Athas, Nestoras Tzartzanis	Energy recovery for low-power CMOS.	ARVLSI	1995	DBLP DOI BibTeX RDF	bootstrap circuits, low-power CMOS, energy-recovery techniques, voltage swing, transition time, MOS device parameters, adder designs, VLSI, mathematical model, bootstrapping, adders, CMOS logic circuits, CMOS logic circuits, power dissipation, integrated circuit modelling, SOI
3	Timothy J. McBrayer, Philip A. Wilsey	Process combination to increase event granularity in parallel logic simulation. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	event granularity, VHDL description, parallel processing, logic CAD, circuit analysis computing, logic circuits, logic circuits, symmetric multiprocessors, logic simulation, digital system design, parallel logic simulation, parallel logic simulators
3	S. Sakurai, Takafumi Aoki, Tatsuo Higuchi	Wire-Free Computing Circuits Using Optical Wave-Casting. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	wire-free computing circuits, optical wave-casting, interconnection problems, information carriers, wire-free logic circuits, fully parallel visual processing system, parallel processing, parallel processing, multiprocessor interconnection networks, logic circuits
3	Shoujue Wang, Xunwei Wu, Hongjuan Feng	The High-Speed Ternary Logic Gates Based on the Multiple beta Transistors. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	high speed ternary logic gates, multiple /spl beta/ transistors, multiple emitter transistor, current gain, linear AND/OR gates, multi valued literal circuits, high speed multi valued logic circuits, multivalued logic circuits, logic gates, ternary logic, transistors
3	Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal	An efficient automatic test generation system for path delay faults in combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	automatic test generation system, test pattern generation system, nonrobust tests, nine-value logic system, multiple backtrace procedure, path selection method, logic testing, delays, integrated circuit testing, fault detection, ATPG, combinational circuits, combinational circuits, automatic testing, fault location, multivalued logic, logic circuits, integrated logic circuits, path delay faults, robust tests
3	Xiaoqing Wen, Kozo Kinoshita	A Testable Design of Logic Circuits under Highly Observable Condition.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	highly observable condition, fault tolerant computing, logic testing, integrated circuit testing, combinational circuit, stuck-at faults, logic circuits, integrated logic circuits, combinatorial circuits, stuck-open faults, testable design
2	Mihir R. Choudhury, Kartik Mohanram	Reliability Analysis of Logic Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
2	Natasa Miskov-Zivanov, Diana Marculescu	A systematic approach to modeling and analysis of transient faults in logic circuits.	ISQED	2009	DBLP DOI BibTeX RDF
2	Mihir R. Choudhury, Kartik Mohanram	Timing-driven optimization using lookahead logic circuits.	DAC	2009	DBLP DOI BibTeX RDF	logic synthesis, timing optimization, lookahead
2	Guoliang He, Naixue Xiong, Athanasios V. Vasilakos, Yuanxiang Li, Zhongzhi Shi	Automated Design of Logic Circuits with a Increasable Evolution Approach.	HPCC	2009	DBLP DOI BibTeX RDF
2	Koustav Bhattacharya, Nagarajan Ranganathan	RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits.	VLSI Design	2009	DBLP DOI BibTeX RDF
2	Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta	Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors.	NanoNet	2009	DBLP DOI BibTeX RDF	low-energy circuits, single electron transistors, binary decision diagram logic circuits
2	Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes	Probabilistic transfer matrices in symbolic reliability analysis of logic circuits.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	fault tolerance, Symbolic analysis
2	Tomasz S. Czajkowski, Stephen Dean Brown	Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Kazuteru Namba, Hideo Ito	Path Delay Fault Test Set for Two-Rail Logic Circuits.	PRDC	2008	DBLP DOI BibTeX RDF
2	Tomasz S. Czajkowski, Stephen Dean Brown	Functionally linear decomposition and synthesis of logic circuits for FPGAs.	DAC	2008	DBLP DOI BibTeX RDF	decomposition, logic synthesis, linearity, Gaussian elimination
2	David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller	Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits.	DATE	2008	DBLP DOI BibTeX RDF
2	Mihir R. Choudhury, Kartik Mohanram	Approximate logic circuits for low overhead, non-intrusive concurrent error detection.	DATE	2008	DBLP DOI BibTeX RDF
2	Massimo Alioto, Massimo Poli, Santina Rocchi	A general model for differential power analysis attacks to static logic circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Kazuteru Namba, Hideo Ito	Delay Fault Testability on Two-Rail Logic Circuits.	DFT	2008	DBLP DOI BibTeX RDF
2	Sin Man Cheang, Kin-Hong Lee, Kwong-Sak Leung	Applying Genetic Parallel Programming to Synthesize Combinational Logic Circuits.	IEEE Trans. Evolutionary Computation	2007	DBLP DOI BibTeX RDF
2	Cecília Reis, José António Tenreiro Machado, J. Boaventura Cunha, Eduardo José Solteiro Pires	Evolutionary computation in the design of logic circuits.	SMC	2007	DBLP DOI BibTeX RDF
2	Tejaswi Gowda, Sarma B. K. Vrudhula, Goran Konjevod	Combinational equivalence checking for threshold logic circuits.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	nano devices, EDA, equivalence checking, threshold logic
2	Ben Choi, K. Tipnis	New Components for Building Fuzzy Logic Circuits.	FSKD	2007	DBLP DOI BibTeX RDF
2	Mihir R. Choudhury, Kartik Mohanram	Accurate and scalable reliability analysis of logic circuits.	DATE	2007	DBLP DOI BibTeX RDF
2	Jin Wang, Chang Hao Piao, Chong Ho Lee	Implementing Multi-VRC Cores to Evolve Combinational Logic Circuits in Parallel.	ICES	2007	DBLP DOI BibTeX RDF	Intrinsic evolvable hardware, scalability, parallel evolutionary algorithm, incremental evolution
2	Shuguang Zhao, Licheng Jiao	Multi-objective evolutionary design and knowledge discovery of logic circuits based on an adaptive genetic algorithm.	Genetic Programming and Evolvable Machines	2006	DBLP DOI BibTeX RDF	Evolutionary design of circuits, Knowledge discovery, Evolvable hardware, Multi-objective genetic algorithm, Adaptive genetic algorithm
2	Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy	Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Vivek V. Shende, Stephen S. Bullock, Igor L. Markov	Synthesis of quantum-logic circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Ali Chehab, Saurabh Patel, Rafic Z. Makki	Scaling of iDDT Test Methods for Random Logic Circuits.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	dynamic power supply current, design for current testability, resistive opens, resistive bridges, very deep sub-micron technologies, VDSM, fault simulation
2	Ji-Yong Jeong, Gil-Su Kim, Jong-Pil Son, Woo-Jin Rim, Soo-Won Kim	Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits.	PATMOS	2006	DBLP DOI BibTeX RDF
2	Alexander Khitun, Kang L. Wang	Nano Logic Circuits with Spin Wave Bus.	ITNG	2006	DBLP DOI BibTeX RDF	logic devices, spin waves, Spintronics
2	Song Peng, Rajit Manohar	Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	asynchronous circuits, yield, defect tolerance, 3D integration, self-reconfiguration
2	Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy	Synthesis of skewed logic circuits.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Skewed logic, optimization, synthesis, power
2	C. K. Tang, Parag K. Lala, James Patrick Parkerson	A Technique for Designing Totally Self-Checking Domino Logic Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
2	Marcus Liwicki, Lars Knipping	Recognizing and Simulating Sketched Logic Circuits.	KES	2005	DBLP DOI BibTeX RDF
2	Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky	Designing logic circuits for probabilistic computation in the presence of noise.	DAC	2005	DBLP DOI BibTeX RDF	nanodevices, reliability, Markov random fields, emerging technologies, noise immunity, probabilistic computing, subthreshold operation
2	W. B. Toms, David A. Edwards	Efficient synthesis of speed-independent combinational logic circuits.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Muhammad Arsalan, Maitham Shams	Charge-Recovery Power Clock Generators for Adiabatic Logic Circuits.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada	Electric field for detecting open leads in CMOS logic circuits by supply current testing.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Yuanzhong Wan, Maitham Shams	Delay modeling of CMOS/CPL logic circuits.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Simon McGregor	How Do Evolved Digital Logic Circuits Generalise Successfully?	ECAL	2005	DBLP DOI BibTeX RDF
2	Shuguang Zhao, Jianxun Zhao, Licheng Jiao	Adaptive Genetic Algorithm Based Approach for Evolutionary Design and Multi-objective Optimization of Logic Circuits.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
2	Emanuele Stomeo, Tatiana Kalganova, Cyrille Lambert, N. Lipnitsakya, Y. Yatskevich	On Evolution of Relatively Large Combinational Logic Circuits.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
2	Phillip W. Moore, Ganesh K. Venayagamoorthy	Evolving Combinational Logic Circuits Using a Hybrid Quantum Evolution and Particle Swarm Inspired Algorithm.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
2	B. Ali, A. E. A. Almaini, Tatiana Kalganova	Evolutionary Algorithms and Theirs Use in the Design of Sequential Logic Circuits.	Genetic Programming and Evolvable Machines	2004	DBLP DOI BibTeX RDF	genetic algorithm, sequential circuits, evolvable hardware, state assignment
2	Davide Appello, Alessandra Fudoli, Katia Giarda, Vincenzo Tancorre, Emil Gizdarski, Ben Mathew	Understanding Yield Losses in Logic Circuits.	IEEE Design & Test of Computers	2004	DBLP DOI BibTeX RDF
2	Daniel J. Deleganes, Micah Barany, George Geannopoulos, Kurt Kreitzer, Anant P. Singh, Sapumal Wijeratne	Low voltage swing logic circuits for a Pentium 4 processor integer core.	DAC	2004	DBLP DOI BibTeX RDF	LVS, Pentium® 4 processor, integer core, low voltage swing, sense-amp, microprocessor, rotator, adder
2	Li Ding 0002, Pinaki Mazumder	A novel technique to improve noise immunity of CMOS dynamic logic circuits.	DAC	2004	DBLP DOI BibTeX RDF	domino logic style, negative differential resistance, noise-tolerant design, digital integrated circuits, dynamic circuits
2	Davide Appello, Alessandra Fudoli, Katia Giarda, Emil Gizdarski, Ben Mathew, Vincenzo Tancorre	Yield Analysis of Logic Circuits.	VTS	2004	DBLP DOI BibTeX RDF
2	Carlos A. Coello Coello, Erika Hernández Luna, Arturo Hernández Aguirre	A Comparative Study of Encodings to Design Combinational Logic Circuits Using Particle Swarm Optimization.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
2	Erika Hernández Luna, Carlos A. Coello Coello, Arturo Hernández Aguirre	On the Use of a Population-Based Particle Swarm Optimizer to Design Combinational Logic Circuits.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
2	Stephen H. Unger	Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors.	IEEE Design & Test of Computers	2003	DBLP DOI BibTeX RDF
2	Kartik Mohanram, Nur A. Touba	Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits.	ITC	2003	DBLP DOI BibTeX RDF
2	Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy	Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling.	DAC	2003	DBLP DOI BibTeX RDF	doping profiles, leakage, tunneling, threshold voltage
2	Kartik Mohanram, Nur A. Touba	Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits.	DFT	2003	DBLP DOI BibTeX RDF
2	Carlos A. Coello Coello, Erika Hernández Luna, Arturo Hernández Aguirre	Use of Particle Swarm Optimization to Design Combinational Logic Circuits.	ICES	2003	DBLP DOI BibTeX RDF
2	Carlos A. Coello Coello, Enrique Alba, Gabriel Luque, Arturo Hernández Aguirre	Comparing Different Serial and Parallel Heuristics to Design Combinational Logic Circuits.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
2	Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy	Synthesis of Selectively Clocked Skewed Logic Circuits. (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF
2	Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi, Takeomi Tamesada	Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits.	DELTA	2002	DBLP DOI BibTeX RDF	adiabatic logic circuit, power supply circuit, CMOS, dynamic circuit, low power circuit
2	Kazumi Hatayama, Michinobu Nakao, Yasuo Sato	At-Speed Built-in Test for Logic Circuits with Multiple Clocks.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
2	R. Martel, V. Derycke, J. Appenzeller, Shalom J. Wind, Ph. Avouris	Carbon nanotube field-effect transistors and logic circuits.	DAC	2002	DBLP DOI BibTeX RDF	FET, SWNT, Schottky barrier, field-effect transistor, circuits, carbon nanotube, nanoelectronics, logic gate, inverter, semiconductor
2	Naotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui	PODEM Based on Static Testability Measures and Dynamic Testability Measures for Multiple-Valued Logic Circuits. (PDF / PS)	ISMVL	2002	DBLP DOI BibTeX RDF	Static Testability Measures, Dynamic Testability Measures, Test Generation, Multiple-Valued Logic, PODEM
2	Noboru Takagi, Kyoichi Nakashima	Logic for Static Hazard Detection of Multiple-Valued Logic Circuits with Tsum, Min, and Literals. (PDF / PS)	ISMVL	2002	DBLP DOI BibTeX RDF
2	Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey	Techniques for Estimation of Design Diversity for Combinational Logic Circuits.	DSN	2001	DBLP DOI BibTeX RDF
2	Keerthi Heragu, Manish Sharma, Rahul Kundu, R. D. (Shawn) Blanton	Testing of Dynamic Logic Circuits Based on Charge Sharing.	VTS	2001	DBLP DOI BibTeX RDF
2	Elena Dubrova, Jon C. Muzio	Easily Testable Multiple-Valued Logic Circuits Derived from Reed-Muller Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Reed-Muller circuit, easily testable circuit, stuck-at fault, Multiple-valued function
2	Alexis De Vos, Bart Desoete, A. Adamski, Piotr Pietrzak, M. Sibínski, T. Widerski	Design of Reversible Logic Circuits by Means of Control Gates.	PATMOS	2000	DBLP DOI BibTeX RDF
2	Hussain Al-Asaad, John P. Hayes	ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits.	VTS	2000	DBLP DOI BibTeX RDF	error and fault simulation, error modeling, Design validation, critical path tracing
2	Carlos A. Coello Coello, Rosa Laura Zavala Gutierrez, Benito Mendoza García, Arturo Hernández Aguirre	Ant Colony System for the Design of Combinational Logic Circuits.	ICES	2000	DBLP DOI BibTeX RDF
2	Carlos A. Coello Coello, Arturo Hernández Aguirre, Bill P. Buckles	Evolutionary Multiobjective Design of Combinational Logic Circuits.	Evolvable Hardware	2000	DBLP DOI BibTeX RDF
2	James C. Ellenbogen	Advances Toward Molecular-Scale Electronic Digital Logic Circuits: A Review and Prospectus.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	nanocomputer architectures, molecular circuit designs, molecular adder, nanoelectronics, molecular electronics
2	Toshio Baba	Development of Quantum Functional Devices for Multiple-Valued Logic Circuits. (PDF / PS)	ISMVL	1999	DBLP DOI BibTeX RDF
2	Ugur Kalay, Marek A. Perkowski, Douglas V. Hall	Highly Testable Boolean Ring Logic Circuits. (PDF / PS)	ISMVL	1999	DBLP DOI BibTeX RDF	Boolean Ring Circuits, Easily Testable Multiple-Valued Logic Circuits, Binary Implementation of MVL Circuits
2	Patrick Fay, Gary H. Bernstein, David H. Chow, J. Schulman, Pinaki Mazumder, W. Williamson, B. K. Gilbert	Integration of InAs/AlSb/GaSb Resonant Interband Tunneling Diodes with Heterostructure Field-Effect Transistors for Ultra-High-Speed Digital Circuit Applications.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	resonant tunneling diode (RTD), resonant interband tunneling diode (RITD), heterostructure field-effect transistor (HFET), ultra-high-speed logic circuits
2	Luca Benini, Patrick Vuillod, Giovanni De Micheli	Iterative remapping for logic circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
2	Teruhiko Yamada, Tsuneto Hanashima, Yasuhiro Suemori, Masaaki Maezawa	On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
2	S. M. Aziz, Joarder Kamruzzaman	Fault Characterization of Low Capacitance Full-Swing BiCMOS Logic Circuits.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
2	Kaamran Raahemifar, Majid Ahmadi	A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF
2	L. Richard Carley, Akshay Aggarwal, Ram K. Krishnamurthy	Decreasing low-voltage manufacturing-induced delay variations with adaptive mixed-voltage-swing circuits.	ISLPED	1998	DBLP DOI BibTeX RDF	low power CMOS logic, low voltage logic circuits, manufacturing variations, mixed-swing CMOS logic
2	Antonio Lioy, Enrico Macii, Massimo Poncino, Massimo Rossello	Accurate Entropy Calculation for Large Logic Circuits Based on Output Clustering.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
2	Toshio Baba, Tetsuya Uemura	Multiple-Junction Surface Tunnel Transistors for Multiple-Valued Logic Circuits . (PDF / PS)	ISMVL	1997	DBLP DOI BibTeX RDF
2	Andreas Herrfeld, Siegbert Hentschke	Quatemary Dynamic Differential Logic with Application to Fuzzy-Logic Circuits. (PDF / PS)	ISMVL	1997	DBLP DOI BibTeX RDF