Search results for "logic design"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Takahiro Hozumi, Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	Multiple-Valued Logic Design Using Multiple-Valued EXOR. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	multiple-valued EXOR, sum operation, multiple valued sum of products expression, binary EXOR of MINs expressions, three valued EXOR of MINs expression, three valued two variable functions, multiple valued EXOR of MINs expressions, MAX of MINs, TSUM of MINs expressions, logic design, neural nets, multivalued logic, logic minimization, minimisation of switching nets, neural computing, multiple valued logic design, multiple-valued logic design
3	Vladimir Mateev, Svilena Todorova, Angel Smrikarov	Test system in digital logic design virtual laboratory: tasks delivery.	CompSysTech	2007	DBLP DOI BibTeX RDF	digital logic design, knowledge testing system, eLearning, virtual laboratory
3	Paul Pukite, Luke Ludwig	Generic discrete event simulations using DEGAS: application to logic design and digital signal processing.	SIGAda	2007	DBLP DOI BibTeX RDF	scheduling, ada, concurrency, discrete-event simulation, logic design, behavioral modeling, design automation, GNAT
3	Lech Józwiak	Information Relationships and Measures in Application to Logic Design. (PDF / PS)	ISMVL	1999	DBLP DOI BibTeX RDF	relationships and measures, logic design, information, information modeling, digital systems, functional decomposition
3	Reiner Hähnle	Proof theory of many-valued logic--linear optimization--logic design: connections and interactions.	Soft Comput.	1997	DBLP DOI BibTeX RDF	logic design, mixed integer programming, many-valued logic
3	Susanto Rahardja, Bogdan J. Falkowski	Family of Complex Hadamard Transforms: Relationship with Other Transforms and Complex Composite Spectra. (PDF / PS)	ISMVL	1997	DBLP DOI BibTeX RDF	complex Hadamard transforms, complex composite spectra, binary logic design, complex Hadamard matrices, convolution operation, complex convolution, Boolean functions, codings, Hadamard transforms, multiple-valued logic design
3	Noboru Takagi, Kyoichi Nakashima, Masao Mukaidono	A Necessary and Sufficient Condition for Lukasiewicz Logic Functions. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	Lukasiewicz logic functions, Lukasiewicz multiple-valued logic, Lukasiewicz implication, logic design, multivalued logic, negation, multiple-valued functions, multiple-valued logic design
3	Kumar N. Lalgudi, Marios C. Papaefthymiou	Efficient retiming under a general delay model.	ARVLSI	1995	DBLP DOI BibTeX RDF	retiming algorithm, general delay model, edge-triggered circuits, load-dependent gate delays, register delays, integer linear programming constraints, integer phonotonic programming formulation, linear programming, delays, timing, integer programming, logic design, logic design, logic circuits, clock skew, propagation delays, interconnect delays
2	Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas	Efficient Reversible Logic Design of BCD Subtractors.	Transactions on Computational Science	2009	DBLP DOI BibTeX RDF	BCD subtractors, BCD adders, Reversible logic
2	Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. Massoud	Dual-threshold pass-transistor logic design.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dual threshold, pass transistor, low power, leakage
2	Vlado Glavinic, Mihael Kukec, Sandi Ljubic	Digital Design Mobile Virtual Laboratory Implementation: A Pragmatic Approach.	HCI	2009	DBLP DOI BibTeX RDF	digital logic design, m-devices, touch sensitive screen, m-learning, virtual laboratories
2	Börje Karlsson, Simone Diniz Junqueira Barbosa, Antonio L. Furtado, Marco A. Casanova	A Plot-Manipulation Algebra to Support Digital Storytelling.	ICEC	2009	DBLP DOI BibTeX RDF	algebraic formalisms, logic design, storytelling, narratology, plots
2	Abdullah Y. Al-Zoubi, Sabina Jeschke, Nicole Natho, Jarir Nsour, Olivier Pfeiffer	Integration of an online digital logic design lab for it education.	SIGITE Conference	2008	DBLP DOI BibTeX RDF	digital electronics, sequential logic, combinational logic, labview, remote labs, it education
2	Kenneth J. Goldman, Paul Gross, Cinda Heeren, Geoffrey L. Herman, Lisa C. Kaczmarczyk, Michael C. Loui, Craig B. Zilles	Identifying important and difficult concepts in introductory computing courses using a delphi process: selective compression of unicode arrays in java.	SIGCSE	2008	DBLP DOI BibTeX RDF	discrete math, programming fundamentals, logic design, curriculum, delphi, concept inventory
2	Samuel C. Lee, Loyd R. Hook IV	Logic and Computer Design in Nanospace.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	hypercube, Logic Design, Sequential circuits, nanocomputer
2	Anish Muttreja, Niket Agarwal, Niraj K. Jha	CMOS logic design with independent-gate FinFETs.	ICCD	2007	DBLP DOI BibTeX RDF
2	Samuel C. Lee, Loyd Reed Hook	Logic Design of Nano Sequential Machines.	CCECE	2006	DBLP DOI BibTeX RDF
2	Sushil J. Louis	Genetic learning for combinational logic design.	Soft Comput.	2005	DBLP DOI BibTeX RDF	Genetic algorithms, Similarity, Case-based-reasoning
2	Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press	Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality.	DATE	2005	DBLP DOI BibTeX RDF
2	Arijit Raychowdhury, Kaushik Roy	A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs.	ISMVL	2004	DBLP DOI BibTeX RDF
2	Daniel H. Y. Teng, Ronald J. Bolton	A Self-Restored Current-Mode CMOS Multiple-Valued Logic Design Technique and its Applications.	ISMVL	2004	DBLP DOI BibTeX RDF
2	Denis V. Popel	Conquering Uncertainty in Multiple-Valued Logic Design.	Artif. Intell. Rev.	2003	DBLP DOI BibTeX RDF	machine learning, knowledge representation, information theory, discretization, multiple-valued logic, decision diagrams
2	Norihiro Fujii, Shûichi Yukita, Nobuhiko Koike, Tosiyasu L. Kunii	Top-Down eLearning Tools for Hardware Logic Design.	CW	2003	DBLP DOI BibTeX RDF
2	Craig A. Lindley, Mirjam Eladhari	Causal Normalization: A Methodology for Coherent Story Logic Design in Computer Role-Playing Games.	Computers and Games	2002	DBLP DOI BibTeX RDF
2	Hussain Al-Asaad, John P. Hayes	Logic Design Validation via Simulation and Automatic Test Pattern Generation.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	test generation, logic design, fault simulation, error modeling, design validation
2	Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang	Charge sharing fault analysis and testing for CMOS domino logic circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	charge sharing fault analysis, CMOS domino logic circuits, domino logic design, sensitivity measurement, domino gate, fault diagnosis, logic testing, delays, delay, automatic testing, CMOS logic circuits, logic gates, test vectors
2	Radomir S. Stankovic	Some remarks on terminology in spectral techniques for logic design: Walsh transform and Hadamard matrices.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
2	Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu	A graph representation for programmable logic arrays to facilitate testing and logic design.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
2	Pramit Chavda, James Jacob, Vishwani D. Agrawal	Optimizing Logic Design Using Boolean Transforms.	VLSI Design	1998	DBLP DOI BibTeX RDF	multi-level synthesis, Boolean functions, logic design, logic synthesis
2	Pi-Yu Chung, Ibrahim N. Hajj	Diagnosis and correction of multiple logic design errors in digital circuits.	IEEE Trans. VLSI Syst.	1997	DBLP DOI BibTeX RDF
2	Lech Józwiak	On the use of term trees for effective and efficient test pattern generation.	EUROMICRO	1997	DBLP DOI BibTeX RDF	term trees, structural automatic test pattern generation, fault discovery, structural fault model, term tree based ATPG algorithm, nonredundant faults, minimal test set, circuit redundancy, logic design, fault model, data representation, automatic test software
2	Tsutomu Sasao, Jon T. Butler	Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions. (PDF / PS)	ISMVL	1997	DBLP DOI BibTeX RDF	best sum-of-products expressions, worst sum-of-products expressions, logic design algorithms, product terms, multiple-valued variables, upper bound, switching functions, switching functions, multiple-valued functions
2	Seokjin Kim, Ramalingam Sridhar	A local clocking approach for self-timed datapath designs.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	self-timed datapath designs, local clock control circuit, synchronous datapaths, asynchronous environment, locally-clocked multiplier, asynchronous system implementation, timing, logic design, logic design, digital arithmetic, asynchronous circuits, multiplying circuits
2	Luis F. G. Sarmenta, Gill A. Pratt, Stephen A. Ward	Rational clocking [digital systems design]. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	rational clocking, independently-clocked digital subsystems, finite probability, phase relationship, delays, delays, logic design, logic design, synchronisation, clocks, minimisation of switching nets, digital systems design, synchronization failure
2	A. Pal, R. K. Gorai, V. V. S. S. Raju	Synthesis of multiplexer network using ratio parameters and mapping onto FPGAs.	VLSI Design	1995	DBLP DOI BibTeX RDF	multiplexing equipment, multiplexer network, ratio parameters, Actel ACT1, MCNC benchmark problems, field programmable gate arrays, FPGAs, VLSI, Boolean functions, Boolean functions, logic design, iterative methods, combinational circuits, combinational circuits, logic CAD, multiplexing, search space, tree network, iterative approach
2	Pi-Yu Chung, Yi-Min Wang, Ibrahim N. Hajj	Logic design error diagnosis and correction.	IEEE Trans. VLSI Syst.	1994	DBLP DOI BibTeX RDF
2	Eric M. Schwarz, Michael J. Flynn	Parallel High-Radix Nonrestoring Division.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	parallel high-radix nonrestoring division, quotient estimation, generalized partial remainder, carry propagate adder, high-radix division, logic design, logic design, latency, computer arithmetic, digital arithmetic, combinatorial algorithm, SRT division
2	Philip A. Lawson	Integrating an Educational Simulation into a Logic Design Course.	ICCAL	1992	DBLP DOI BibTeX RDF
2	Jon T. Butler, Kriss A. Schueller	On the Equivalence of Cost Functions in the Design of Circuits by Costtable.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	design of circuits by cost-table, least-cost realization, minimal realization, logic design, logic design, equivalence, cost functions
2	Hiroshi Nakamura, Masaya Nakai, Shinji Kono, Masahiro Fujita, Hidehiko Tanaka	Logic Design Assistence Using Temporal Logic Based Language Tokio.	LP	1989	DBLP DOI BibTeX RDF
2	Magdy S. Abadir, Jack Ferguson, Tom E. Kirkland	Logic design verification via test generation.	IEEE Trans. on CAD of Integrated Circuits and Systems	1988	DBLP DOI BibTeX RDF
2	Shinji Nakamura, Kai-Yu Chu	A Single Chip Parallel Multiplier by MOS Technology.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	single chip parallel multiplier, MOS technology, five-counter cell, logic design level, full adder cell design, logic design, integrated logic circuits, multiplying circuits, design optimization, field effect integrated circuits
2	Louise Trevillyan, William H. Joyner Jr., C. Leonard Berman	Global Flow Analysis in Automatic Logic Design.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	PLA's, Automatic logic design, global flow analysis, compilers, control logic
2	Yahiko Kambayashi	Logic Design of Programmable Logic Arrays.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	two-level circuit, Incompletely specified logic function, reduction of the number of inputs, logic design, programmable logic array, multiple-output function
2	Edward J. McCluskey	Logic Design of Multivalued I2L Logic Circuits.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	switching algebra, multilevel I2L, logic design, multivalued logic, Combinational networks
2	Yacoub M. El-Ziq, Stephen Y. H. Su	Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	diagnosable networks, easily testable networks, field-effect transistors, logic design automation, metal-oxide semiconductor, Boolean functions, logic synthesis, testability, combinational logic, combinational networks, statistical data, computer algorithm
1	Daesung Lee 0002, W. Scott Lee, Chen Chen, Farzan Fallah, J. Provine, Soogine Chong, John Watkins, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra	Combinational Logic Design Using Six-Terminal NEM Relays.	IEEE Trans. on CAD of Integrated Circuits and Systems	2013	DBLP DOI BibTeX RDF
1	Zarko Stanisavljevic, Vladimir Pavlovic, Bosko Nikolic, Jovan Djordjevic	SDLDS - System for Digital Logic Design and Simulation.	IEEE Trans. Education	2013	DBLP DOI BibTeX RDF
1	Christopher M. Kellett	A Project-Based Learning Approach to Programmable Logic Design and Computer Architecture.	IEEE Trans. Education	2012	DBLP DOI BibTeX RDF
1	Jacek Tkacz, Marian Adamski	Logic design of structured configurable controllers.	NESEA	2012	DBLP DOI BibTeX RDF
1	Zarko Stanisavljevic, Bosko Nikolic, Jovan Djordjevic	A Module for Automatic Assessment and Verification of Students' Work in Digital Logic Design.	ECBS	2012	DBLP DOI BibTeX RDF
1	Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama	Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit.	ISCAS	2012	DBLP DOI BibTeX RDF
1	Lancelot Garcia-Leyva, Dennis Andrade, Sergio Gómez, Antonio Calomarde, Francesc Moll, Antonio Rubio	New redundant logic design concept for high noise and low voltage scenarios.	Microelectronics Journal	2011	DBLP DOI BibTeX RDF
1	Piotr Debiec, Marcin Byczuk	Teaching Discrete and Programmable Logic Design Techniques Using a Single Laboratory Board.	IEEE Trans. Education	2011	DBLP DOI BibTeX RDF
1	Michael Kirkedal Thomsen, Holger Bock Axelsen, Robert Glück	A Reversible Processor Architecture and Its Reversible Logic Design.	RC	2011	DBLP DOI BibTeX RDF
1	William M. Jones, D. Brian Larkins	Integrating digital logic design and assembly programming using FPGAs in the classroom.	ACM Southeast Regional Conference	2011	DBLP DOI BibTeX RDF
1	Norul Huda Yusof, Rosilah Hassan	Flash notes and easy electronic software (EES): New technique to improve Digital Logic Design learning.	ICEEI	2011	DBLP DOI BibTeX RDF
1	Primoz Pecar, Iztok Lebar Bajec	The Key Elements of Logic Design in Ternary Quantum-Dot Cellular Automata.	UC	2011	DBLP DOI BibTeX RDF
1	Amit Acharyya, Koushik Maharatna, Bashir M. Al-Hashimi, Hasitha Tudugalle	Simplified logic design methodology for fuzzy membership function based robust detection of maternal modulus maxima location: A low complexity Fetal ECG extraction architecture for mobile health monitoring systems.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Sergio Antoy, Michael Hanus	New Functional Logic Design Patterns.	WFLP	2011	DBLP DOI BibTeX RDF
1	Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman	Memristor-based IMPLY logic design procedure.	ICCD	2011	DBLP DOI BibTeX RDF
1	Chin-Hsing Cheng, Po-Jen Cheng, Ming-Tzong Wu	Fuzzy logic design of self-tuning switching power supply.	Expert Syst. Appl.	2010	DBLP DOI BibTeX RDF
1	Kwang-Jow Gan, Dong-Shong Liang, Yan-Wun Chen	Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Tao Feng, Noh-Jin Park, Minsu Choi, Nohpill Park	Reliability Modeling and Analysis of Clockless Wave Pipeline Core for Embedded Combinational Logic Design.	IEEE T. Instrumentation and Measurement	2010	DBLP DOI BibTeX RDF
1	Koji Sakui, Tetsuo Endoh	A compact and low power logic design for multi-pillar vertical MOSFETs.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Hamed F. Dadgour, Muhammad M. Hussain, Casey Smith, Kaustav Banerjee	Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS.	DAC	2010	DBLP DOI BibTeX RDF	energy-efficient electronics, laterally-actuated NEMS, nano-electro-mechanical switches, steep-subthreshold switch, logic design, process variation
1	Geoffrey L. Herman, Michael C. Loui, Craig B. Zilles	Creating the digital logic concept inventory.	SIGCSE	2010	DBLP DOI BibTeX RDF	assessment, logic design, curriculum, concept inventory
1	Hadi Hosseini, Gerhard W. Dueck	Toffoli Gate Implementation Using the Billiard Ball Model.	ISMVL	2010	DBLP DOI BibTeX RDF	Toffoli Gates, Billiard Ball Model, Logic Design, Reversible Logic
1	Yasaman Sanaee, Gerhard W. Dueck	ESOP-Based Toffoli Network Generation with Transformations.	ISMVL	2010	DBLP DOI BibTeX RDF	Toffoli Gates, Logic Design, Reversible Logic, ESOP
1	Karin Weigelt, Mike Hambsch, Gabor Karacs, Tino Zillger, Arved C. Hübler	Labeling the World: Tagging Mass Products with Printing Processes.	IEEE Pervasive Computing	2010	DBLP DOI BibTeX RDF	memory control and access, design styles, printed electronics, printing processes, ubiquitous computing, logic design, hardware, hardware, computer systems organization, memory structures, special-purpose and application-based systems, ROM, semiconductor memories
1	Jie-Hong Roland Jiang, Chih-Chun Lee, Alan Mishchenko, Chung-Yang Huang	To SAT or Not to SAT: Scalable Exploration of Functional Dependency.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	optimization, logic design, Automatic synthesis, design aids
1	Mingjie Lin, Ilia A. Lebedev, John Wawrzynek	High-throughput bayesian computing machine with reconfigurable hardware.	FPGA	2010	DBLP DOI BibTeX RDF	reconfigurable hardware, bayesian computing
1	Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala	Design of self correcting radiation hardened digital circuits using decoupled ground bus.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	self-repairing circuits, soft errors, radiation hardening
1	Fang-Ming Yu	A self-tuning fuzzy logic design for perturbed time-delay systems with nonlinear input.	Expert Syst. Appl.	2009	DBLP DOI BibTeX RDF
1	Douglas Densmore, J. Christopher Anderson	Combinational Logic Design in Synthetic Biology.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Alon Gluska, Lior Libis	Shortening the verification cycle with synthesizable abstract models.	DAC	2009	DBLP DOI BibTeX RDF	verification, logic design, abstract modeling
1	David Bañeres, Jordi Cortadella, Michael Kishinevsky	Timing-driven N-way decomposition.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	logic design, decomposition, timing optimization
1	Richard M. Salter, John L. Donaldson	Abstraction and extensibility in digital logic simulation software.	SIGCSE	2009	DBLP DOI BibTeX RDF	simulation, abstraction, logic design
1	Kuan Jen Lin, Yi Tang Chiu, Shan Chien Fang	Design Optimization and Automation for Secure Cryptographic Circuits.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Cheng-Hong Li, Luca P. Carloni	Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Claudio Moraga, Héctor Allende	Walsh Matrices in the Design of Industrial Experiments.	EUROCAST	2009	DBLP DOI BibTeX RDF
1	Xiaojun Ma, Jing Huang, Cecilia Metra, Fabrizio Lombardi	Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates.	J. Electronic Testing	2009	DBLP DOI BibTeX RDF	Array testing, Nanotechnology, Emerging technology, Reversible computing, QCA
1	Héctor Pettenghi, Maria J. Avedillo, José M. Quintana	Using multi-threshold threshold gates in RTD-based logic design: A case study.	Microelectronics Journal	2008	DBLP DOI BibTeX RDF
1	Saket Srivastava, Sanjukta Bhanja	Integrating a Nanologic Knowledge Module Into an Undergraduate Logic Design Course.	IEEE Trans. Education	2008	DBLP DOI BibTeX RDF
1	Issam W. Damaj	Logic Design.	Wiley Encyclopedia of Computer Science and Engineering	2008	DBLP DOI BibTeX RDF
1	David A. Poplawski, Zachary Kurmas	JLS: a pedagogically targeted logic design and simulation tool.	ITiCSE	2008	DBLP DOI BibTeX RDF	jls, simulation, digital logic
1	Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas	Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	leakage estimation, logic design, cmos gates
1	Claas Cornelius, Frank Sill, Hagen Sämrow, Jakob Salzmann, Dirk Timmermann, Diógenes Cecilio da Silva Jr.	Encountering gate oxide breakdown with shadow transistors to increase reliability.	SBCCI	2008	DBLP DOI BibTeX RDF	gate oxide breakdown, modeling, redundancy, logic design, nanotechnology, organic computing, transistor
1	Osnat Keren	Reduction of Average Path Length in Binary Decision Diagrams by Spectral Methods.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Logic Design, Spectral methods, Automatic synthesis
1	Faqir Zarrar Yousaf, Christian Bauer, Christian Wietfeld	An accurate and extensible mobile IPv6 (xMIPV6) simulation model for OMNeT++.	SimuTools	2008	DBLP DOI BibTeX RDF	C++ discrete event simulation model, OMNeT++, MIPv6, protocol simulation
1	James Moscola, John W. Lockwood, Young H. Cho	Reconfigurable content-based router using hardware-accelerated language parser.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	parser hardware, XML, pattern matching, Parsing, regular expressions, content-based routing
1	Werner Friesenbichler, Thomas Panhofer, Martin Delvai	Improving Fault Tolerance by Using Reconfigurable Asynchronous Circuits.	DDECS	2008	DBLP DOI BibTeX RDF
1	Saurabh Jain, W. Robert Daasch, David Armbrust	Analyzing the Impact of Fault Tolerant BIST for VLSI Design.	DFT	2008	DBLP DOI BibTeX RDF
1	Jin-Wei Tioh, Rashmi Bahuguna, Nathan A. VanderHorn, Mani Mina, Robert J. Weber, Arun K. Somani	Reprogrammable high-speed platform : Bridging the gap between research, education and engineering.	EIT	2008	DBLP DOI BibTeX RDF
1	Bipul Chandra Paul, Shinobu Fujita, Masaki Okajima	ROM based logic (RBL) design: High-performance and low-power adders.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Michael Wieckowski, Martin Margala	A portless SRAM Cell using stunted wordline drivers.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Jiun-Kuan Wu, Tsung-Yi Wu, Liang-Ying Lu, Kuang-Yao Chen	IR Drop Reduction via a Flip-Flop Resynthesis Technique.	ISQED	2008	DBLP DOI BibTeX RDF	Peak Current Reduction, IR Drop, Clock Skew Scheduling
1	P. B. Alipour	Logic, Design & Organization of PTVD-SHAM; A Parallel Time Varying & Data Super-helical Access Memory	CoRR	2007	DBLP BibTeX RDF
1	Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press	Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality	CoRR	2007	DBLP BibTeX RDF
1	Igor Lemberski	Avoiding Hazards for Speed-Independent Logic Design.	World Congress on Engineering	2007	DBLP BibTeX RDF