Search results for "logic function"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	A. K. Jain, Mostafa H. Abd-El-Barr, R. J. Bolton	Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	current-mode CMOS multiple-valued logic function realization, heuristic based programs, sum of product form expression, HAMLET, Gold heuristic, current mode CMOS, multiple valued logic function realization, direct cover algorithm, logic design, random sample, multivalued logic, CMOS logic circuits, heuristic programming, MVL function
2	Mozammel H. A. Khan, Nafisa K. Siddika, Marek A. Perkowski	Minimization of Quaternary Galois Field Sum of Products Expression for Multi-Output Quaternary Logic Function Using Quaternary Galois Field Decision Diagram.	ISMVL	2008	DBLP DOI BibTeX RDF
2	Denis V. Popel, Anita Dani	Sierpinski Gaskets for Logic Functions Representation. (PDF / PS)	ISMVL	2002	DBLP DOI BibTeX RDF	Sierpinski gasket, fractal, minimization, logic function, ESOP
2	Arturo Hernández Aguirre, Bill P. Buckles, Carlos A. Coello Coello	A Genetic Programming Approach to Logic Function Synthesis by Means of Multiplexers.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
2	Kazuo Kawakubo, Koji Tanaka, Hiromi Hiraishi	Formal Verification Of Self-Testing Properties Of Combinational Circuits.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	self-testing properties, logic function manipulation, decision function, output code words, self-checking logic, mutiple-input multiple-output circuit, fault tolerance, formal verification, combinational circuits, combinational circuits, binary decision diagrams, stuck-at faults, satisfiability problem, characteristic functions, Berger code
2	Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia	Fast discrete function evaluation using decision diagrams.	ICCAD	1995	DBLP DOI BibTeX RDF	address lookups, cycle-based logic simulation, decision-diagram based function evaluation, fast discrete function evaluation, latch ports, orders-of-magnitude potential speedup, output ports, logic design, memory hierarchy, logic CAD, decision theory, circuit analysis computing, memory bandwidth, table lookup, digital circuits, logic simulators, logic function, function evaluation, multi-valued decision diagrams
1	Stefan Kolodzinski, Edward Hrynkiewicz	Decomposition of multi-output logic function in Reed-Muller spectral domain.	DDECS	2011	DBLP DOI BibTeX RDF
1	Hamid Reza Pourshaghaghi, Reza Ahmadi, Mohammad-Reza Jahed Motlagh, Behnam Kia	Experimental Realization of a Reconfigurable Three Input, One Output Logic Function Based on a Chaotic Circuit.	I. J. Bifurcation and Chaos	2010	DBLP DOI BibTeX RDF
1	Shuqin Zhong, Zhi Ma, Yajie Xu	Constructing quantum error correcting code via logic function.	SCIENCE CHINA Information Sciences	2010	DBLP DOI BibTeX RDF
1	Ian Stewart, Wenying Feng, Selim G. Akl	Tuning Neural Networks by Both Connectivity and Size.	ITNG	2010	DBLP DOI BibTeX RDF	Genetic algorithm, neural network, fitness function, logic function, hidden node
1	Yu-Chen Chen, Hou-Yu Pang, Kuen-Wen Lin, Rung-Bin Lin, Hui-Hsiang Tung, Shih-Chieh Su	Via configurable three-input lookup-tables for structured ASICs.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	via-configurable, layout, look-up-table, vlsi, structured ASIC
1	Ashok Kumar Palaniswamy, Manoj Kumar Goparaju, Spyros Tragoudas	Scalable identification of threshold logic functions.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	threshold logic gates
1	Marek A. Bawiec, Maciej Nikodem	Boolean logic function synthesis for generalised threshold gate circuits.	DAC	2009	DBLP DOI BibTeX RDF	GTG, NDR, nanoscale devices, logic synthesis
1	Stefan Kolodzinski, Edward Hrynkiewicz	An utilisation of Boolean differential calculus in variables partition calculation for decomposition of logic functions.	DDECS	2009	DBLP DOI BibTeX RDF
1	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Logic Mapping in Crossbar-Based Nanoarchitectures.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Takaaki Mizuki, Hitoshi Tsubata, Takao Nishizeki	Minimizing AND-EXOR Expressions for Multiple-Valued Two-Input Logic Functions.	TAMC	2009	DBLP DOI BibTeX RDF
1	Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal	Architecture-specific packing for virtex-5 FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	optimization, performance, FPGAs, field-programmable gate arrays, power, placement, packing
1	Yu Hu, Zhe Feng 0002, Lei He, Rupak Majumdar	Robust FPGA resynthesis based on fault-tolerant Boolean matching.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Guolin Huang, Weiming Wang, Fenggen Jia	An Extensible IPv6 Router Based On ForCES.	ICNSC	2008	DBLP DOI BibTeX RDF
1	Hosam A. Aleem, Ferda Mavituna, David H. Green	A Galois Field Approach to Modelling Gene Expression Regulation.	ISMVL	2008	DBLP DOI BibTeX RDF	Gene Expression, Galois Field, Genetic Code, Reed-Muller Expansion
1	Mozammel H. A. Khan	Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits.	ISMVL	2008	DBLP DOI BibTeX RDF
1	Tomasz S. Czajkowski, Stephen Dean Brown	Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Paul Beckett	A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Wang Pengjun, Lu Jingang, Xu Jian	Application of Neuron MOS in multiple-valued logic.	Neural Computing and Applications	2008	DBLP DOI BibTeX RDF	Neuron MOS transistor, Multiple-valued D/A converter, Multiple-valued A/D converter
1	Mel Breuer	Tesla and AND gates.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	Nikola Tesla, radar, logic function, radio, AND gate
1	Sarah E. Murphy, Erik DeBenedictis, Peter M. Kogge	General floorplan for reversible quantum-dot cellular automata.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	reversible computing, quantum-dot cellular automata
1	Pengyuan Yu, Patrick Schaumont	Secure FPGA circuits using controlled placement and routing.	CODES+ISSS	2007	DBLP DOI BibTeX RDF
1	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Postplacement rewiring by exhaustive search for functional symmetries.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	VLSI, placement, rewiring
1	Nishant Patil, Jie Deng, H.-S. Philip Wong, Subhasish Mitra	Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits.	DAC	2007	DBLP DOI BibTeX RDF
1	Ricardo Cunha, Henri Boudinov, Luigi Carro	Quaternary Look-Up Tables Using Voltage-Mode CMOS Logic Design.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Dimitrios Kagaris, Themistoklis Haniotakis	A Methodology for Transistor-Efficient Supergate Design.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Xuesong Yan, Wei Wei, Qingzhong Liang, Chengyu Hu, Yuan Yao	Designing Electronic Circuits by Means of Gene Expression Programming II.	ICES	2007	DBLP DOI BibTeX RDF
1	Yong-Kab Kim, Woo-Soon Kim, Yue Soon Choi, Jong Goo Park	Implementation of Brillouin-Active Fiber for Low Threshold Optical Logic and Memory Based Neural Networks in Smart Structures.	ISNN	2007	DBLP DOI BibTeX RDF
1	Ricardo C. Goncalves da Silva, Henri Boudinov, Luigi Carro	A cell library for low power high performance CMOS voltage-mode quaternary logic.	SBCCI	2006	DBLP DOI BibTeX RDF	quaternary logic design, voltage-mode, multi-valued logic
1	Wang Pengjun, Yu Junjun, Xu Jian	Design of Clocked Transmission Gate Adiabatic Logic Circuit Based on the 3ECEAC.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Y. Bénédic, Jean Mercklé	Optimization of Binary-Output CNNs: First Step of an Analytical Design Process.	IJCNN	2006	DBLP DOI BibTeX RDF
1	Benjamas Tongprasit, Tadashi Shibata	Power-balanced reconfigurable floating-gate-MOS logic circuit for tamper resistant VLSI.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Pan Zhongliang, Chen Ling, Liu Shouqiang, Guangzhao Zhang	Neural Network Approach for Multiple Fault Test of Digital Circuit.	ISDA	2006	DBLP DOI BibTeX RDF
1	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De	Formal derivation of optimal active shielding for low-power on-chip buses.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Yong-Kab Kim, Soonja Lim, Dong-Hyun Kim	Effect of Steady and Relaxation Oscillation Using Controlled Chaotic Instabilities in Brillouin Fibers Based Neural Network.	ICNC	2006	DBLP DOI BibTeX RDF
1	Yong-Kab Kim, Soonja Lim, ChangKug Kim	Effect of Steady and Relaxation Oscillations in Brillouin-Active Fiber Structural Sensor Based Neural Network in Smart Structures.	ISNN	2006	DBLP DOI BibTeX RDF
1	Christian Piguet, Christian Schuster, Jean-Luc Nagel	Static and Dynamic Power Reduction by Architecture Selection.	PATMOS	2006	DBLP DOI BibTeX RDF
1	Guoqiang Hang	Adiabatic CMOS gate and adiabatic circuit design for low-power applications.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Susan Cotterell, Frank Vahid	A logic block enabling logic configuration by non-experts in sensor networks.	CHI Extended Abstracts	2005	DBLP DOI BibTeX RDF	eBlocks, embedded computing systems, sensor networks, boolean logic, truth table
1	Jing Huang, Mariam Momenzadeh, Luca Schiano, Marco Ottavi, Fabrizio Lombardi	Tile-based QCA design using majority-like logic primitives.	JETC	2005	DBLP DOI BibTeX RDF	processing-by-wire, emerging technologies, QCA
1	Krzysztof S. Berezowski, Sarma B. K. Vrudhula	Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series.	DSD	2005	DBLP DOI BibTeX RDF
1	Felipe Ribeiro Schneider, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis	Exact lower bound for the number of switches in series to implement a combinational logic cell.	ICCD	2005	DBLP DOI BibTeX RDF
1	Yen-Tai Lai, Yung-Chuan Jiang, Hong-Ming Chu	BDD decomposition for mixed CMOS/PTL logic circuit synthesis.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Sing-Rong Li, Pinaki Mazumder, Kyounghoon Yang	On the functional failure and switching time analysis of the MOBILE circuit [monostable-bistable logic element].	ISCAS	2005	DBLP DOI BibTeX RDF
1	Mitchell A. Thornton	The Karhunen-Loève Transform of Discrete MVL Functions.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Richard Hobson, Scott Wakelin	An Area-Efficient High-Speed AES S-Box Method.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Krishna Prasad Raghuraman, Haibo Wang, Spyros Tragoudas	A Novel Approach to Minimizing Reconfiguration Cost for LUT-Based FPGAs.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Shinobu Nagayama, Tsutomu Sasao	On the optimization of heterogeneous MDDs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown	FPGA Logic Synthesis Using Quantified Boolean Satisfiability.	SAT	2005	DBLP DOI BibTeX RDF
1	Joonhwan Yi, John P. Hayes	The Coupling Model for Function and Delay Faults.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	test generation, fault modeling, delay faults, functional faults
1	Yoshinori Yamamoto	Extended regular ternary logic functions and majority functions capable of synthesizing any ternary logic function.	Systems and Computers in Japan	2004	DBLP DOI BibTeX RDF
1	Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy	High-level area and power-up current estimation considering rich cell library.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Shinobu Nagayama, Tsutomu Sasao	Minimization of memory size for heterogeneous MDDs.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Debayan Bhaduri, Sandeep K. Shukla	NANOPRISM: a tool for evaluating granularity vs. reliability trade-offs in nano architectures.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	CTMR, defect-tolerant architecture, nanotechnology, granularity, TMR, PRISM
1	Maged Ghoneima, Yehea I. Ismail	Formal derivation of optimal active shielding for low-power on-chip buses.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura	A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades.	ISMVL	2004	DBLP DOI BibTeX RDF
1	Pawel Kerntopf, Marek A. Perkowski, Mozammel H. A. Khan	On Universality of General Reversible Multiple-Valued Logic Gates.	ISMVL	2004	DBLP DOI BibTeX RDF
1	D. Michael Miller, Gerhard W. Dueck, Dmitri Maslov	A Synthesis Method for MVL Reversible Logi.	ISMVL	2004	DBLP DOI BibTeX RDF
1	Haque Mohammad Munirul, Michitaka Kameyama	Ultra-Fine-Grain Field-Programmable VLSI Using Multiple-Valued Source-Coupled Logic.	ISMVL	2004	DBLP DOI BibTeX RDF
1	Shinobu Nagayama, Tsutomu Sasao	On the Minimization of Average Path Lengths for Heterogeneous MDDs.	ISMVL	2004	DBLP DOI BibTeX RDF
1	Shih-Lien Lu	Speeding Up Processing with Approximation Circuits.	IEEE Computer	2004	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey	Efficient Design Diversity Estimation for Combinational Circuits.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	common-mode failures, reliability, fault-tolerant computing, dependability, Error detection, design diversity
1	Noboru Takagi, Hiroaki Kikuchi, Masao Mukaidono	Applications of Fuzzy Logic Functions to Knowledge Discovery in Databases.	T. Rough Sets	2004	DBLP DOI BibTeX RDF
1	Yunjian Jiang, Slobodan Matic, Robert K. Brayton	Generalized cofactoring for logic function evaluation.	DAC	2003	DBLP DOI BibTeX RDF	code generation, logic simulation
1	Mutlu Avci, Tülay Yildirim	A coding method for 123 decision diagram pass transistor logic circuit synthesis.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Yoshinori Yamamoto	An extension of ternary majority function and its application to evolvable system. (PDF / PS)	ISMVL	2003	DBLP DOI BibTeX RDF
1	Maurizio Damiani, Andrei Y. Selchenko	Boolean Technology Mapping Based on Logic Decomposition.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Kun-Lin Tsai, Feipei Lai, Shanq-Jang Ruan, Szu-Wei Chaung	State Reordering for Low Power Combinational Logic.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
1	Fei Li, Lei He, Joseph M. Basile, Rakesh Patel, Hema Ramamurthy	High Level Area and Current Estimation.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Ricardo Augusto da Luz Reis	Power and Timing Driven Physical Design Automation.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Turgay Temel, Avni Morgul	Multi-valued logic function implementation with novel current-mode logic gates.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Kazuya Shimizu, Masaya Takamura, Takanori Shirai, Noriyoshi Itazaki, Kozo Kinoshita	Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits.	DELTA	2002	DBLP DOI BibTeX RDF	Clock-delayed domino circuit, Fault simulation, crosstalk fault
1	K. Aoyama	A reconfigurable logic circuit based on threshold elements with a controlled floating gate.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada	Logic synthesis for PLA with 2-input logic elements.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Kuo-Hsing Cheng, Shun-Wen Cheng	Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization.	VLSI Design	2002	DBLP DOI BibTeX RDF	full-swing logic, Low power design, VLSI design, hybrid logic, prime implicant
1	Hiroaki Kikuchi	Identification of Incompletely Specified Fuzzy Unate Logic Function.	ISMVL	2001	DBLP BibTeX RDF
1	Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey	Techniques for Estimation of Design Diversity for Combinational Logic Circuits.	DSN	2001	DBLP DOI BibTeX RDF
1	Huo-Hsing Cheng, Ven-Chieh Hsieh	A new logic synthesis and optimization procedure.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Frank Grassert, Dirk Timmermann	Dynamic single phase logic with self-timed stages for power reduction in pipeline circuit designs.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura	Implementation of Multiple-Output Functions Using PQMDDs. (PDF / PS)	ISMVL	2000	DBLP DOI BibTeX RDF	Multiple-output logic function, PMDD, PQMDD, MDD, BDD
1	Lijian Li, Xiaoyang Yu, Cheng-Wen Wu, Yinghua Min	A waveform simulator based on Boolean process.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	waveform simulator, high performance integrated circuits, Boolean functions, logic CAD, timing behavior, Boolean process
1	Takahiro Hozumi, Osamu Kakusho, Kazuharu Yamato	An Evolutionary Computing Approach to Multilevel Logic Synthesis Using Various Logic Operations. (PDF / PS)	ISMVL	2000	DBLP DOI BibTeX RDF	multilevel circuits, various operations, genetic algorithm, logic synthesis
1	Svetlana N. Yanushkevich, Denis V. Popel, Vlad P. Shmerko, V. Cheushev, Radomir S. Stankovic	Information Theoretic Approach to Minimization of Polynomial Expressions over GF(4). (PDF / PS)	ISMVL	2000	DBLP DOI BibTeX RDF	multiple-valued logic functions, information theory measures, decision trees, minimization
1	Subhasish Mitra, Edward J. McCluskey	Word Voter: A New Voter Design for Triple Modular Redundant Systems.	VTS	2000	DBLP DOI BibTeX RDF	Word-Voter, TMR-Simplex, data integrity, Triple Modular redundancy (TMR), Voter
1	Paul Tafertshofer, Andreas Ganz, Kurt Antreich	IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	Tsutomu Sasao	Totally Undecomposable Functions: Applications to Efficient Multiple-Valued Decompositions. (PDF / PS)	ISMVL	1999	DBLP DOI BibTeX RDF	LUT-based FPGA, Multiple-valued logic function, Functional decomposition, Symmetric function
1	Paul Tafertshofer, Andreas Ganz	SAT based ATPG using fast justification and propagation in the implication graph.	ICCAD	1999	DBLP BibTeX RDF
1	Yukihiro Iguchi, Munehiro Matsuura, Tsutomu Sasao, Atsumu Iseno	Realization of Regular Ternary Logic Functions.	ASP-DAC	1999	DBLP DOI BibTeX RDF
1	Alberto Macii, Enrico Macii, Giuseppe Odasso, Massimo Poncino, Riccardo Scarsi	Regression-Based Macromodeling for Delay Estimation of Behavioral Components.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
1	W. Quddus, Abhijit Jas, Nur A. Touba	Configuration self-test in FPGA-based reconfigurable systems.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Edgar "Dan" Olson	Supplementary Symmetrical Logic Circuit Structure. (PDF / PS)	ISMVL	1999	DBLP DOI BibTeX RDF	fully active, self sustaining
1	Debaleena Das, Nur A. Touba	A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based Reconfigurable Systems.	VLSI Design	1999	DBLP DOI BibTeX RDF
1	Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya	Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions.	DATE	1998	DBLP DOI BibTeX RDF	simple disjunctive decomposition, symmetric variables, multi-level logic circuit, ordered binary decision diagram
1	Peter Dahlgren	Switch-level bridging fault simulation in the presence of feedbacks.	ITC	1998	DBLP DOI BibTeX RDF
1	Stanislaw J. Piestrak	Design of encoders and self-testing checkers for some systematic unidirectional error detecting codes. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF	systematic unidirectional error detecting code, t-UED Bose-Lin code, burst UED code, multi-output threshold circuit, encoder, automatic testing, logic function, Berger code, hardware complexity, self-testing checker