Search results for "logic partitioning"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Scott Hauck, Gaetano Borriello	An evaluation of bipartitioning techniques.	ARVLSI	1995	DBLP DOI BibTeX RDF	bipartitioning techniques, VLSI, logic CAD, integrated circuit design, circuit CAD, logic partitioning, logic partitioning, VLSI CAD
2	Raj S. Mitra, Partha S. Roop, Anupam Basu	Implementation of design functions by available devices: a new algorithm.	VLSI Design	1995	DBLP DOI BibTeX RDF	design functions, available devices, function behaviors, mapping process, VLSI, VLSI, CAD, finite state machines, finite state machines, logic CAD, circuit CAD, logic partitioning, logic partitioning
1	Harika Manem, Garrett S. Rose	The effects of logic partitioning in a majority logic based CMOS-NANO FPGA.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	cmos-nano, fpga
1	Benjamin Carrión Schäfer, Taewhan Kim	Hotspots Elimination and Temperature Flattening in VLSI Circuits.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	David Bañeres, Jordi Cortadella, Michael Kishinevsky	Dominator-based partitioning for delay optimization.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	logic design, timing optimization, logic partitioning
1	Hyung Gyu Lee, Sungyuep Nam, Naehyuck Chang	Cycle-accurate Energy Measurement and High-Level Energy Characterization of FPGAs.	ISQED	2003	DBLP DOI BibTeX RDF
1	Paul Chang, Brion L. Keller, Sarala Paliwal	Effective parallel processing techniques for the generation of test data for a logic built-in self test system.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	logic built-in self test, complex processor, simulation time, random stimulus generation, signature computation, Pseudo-Random Pattern Generators, serial compression, response data, serial pattern dependency, parallel processing, parallel processing, logic testing, partitioning, built-in self test, integrated circuit testing, automatic test pattern generation, signatures, parallel simulation, microprocessor chips, logic simulation, logic simulation, post processing, logic partitioning, test data
1	Morgan Enos, Scott Hauck, Majid Sarrafzadeh	Evaluation and optimization of replication algorithms for logic bipartitioning.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Scott Hauck, Gaetano Borriello	An evaluation of bipartitioning techniques.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
1	Prathima Agrawal, B. Narendran, Narayanan Shivakumar	Multi-way partitioning of VLSI circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	multi-way partitioning, hierarchical design processes, nets cut metric, VLSI, delays, economics, logic CAD, VLSI layout, integrated circuit layout, VLSI circuits, logic partitioning, minimisation of switching nets, average delay, integrated circuit manufacture, cost metric
1	S. Nandi, Santanu Chattopadhyay, Parimal Pal Chaudhuri	Programmable cellular automata based testbed for fault diagnosis in VLSI circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	programmable cellular automata, polynomial algebraic tools, faulty signatures, multiple attractor, fault dictionary size, cascadable structure, VLSI, fault diagnosis, fault diagnosis, logic testing, partitions, cellular automata, integrated circuit testing, automatic testing, VLSI circuits, logic partitioning, signature analyzer
1	Krishna B. Rajan, David E. Long, Miron Abramovici	Increasing testability by clock transformation (getting rid of those darn states).	VTS	1996	DBLP DOI BibTeX RDF	clock transformation, sequential test generation, darn states, easy-to-reach states, logic testing, partitioning, design for testability, sequential circuits, DFT, fault coverage, testability, flip-flops, flip-flops, clocks, logic partitioning
1	A. Singla, T. M. Conte	Bipartitioning for Hybrid FPGA-Software Simulatio.	VLSI Design	1996	DBLP DOI BibTeX RDF
1	Amir H. Farrahi, Majid Sarrafzadeh	System partitioning to maximize sleep time.	ICCAD	1995	DBLP DOI BibTeX RDF	Geo-Part, exploitable sleep time, geometric partitioning heuristic, low-power synthesis, memory refresh circuitry, segment tree data structure, VLSI, logic CAD, integrated circuit design, circuit CAD, circuit optimisation, logic partitioning, partitioning problem, system partitioning
1	Hirendu Vaishnav, Massoud Pedram	Delay optimal partitioning targeting low power VLSI circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	clustering, VLSI, partitioning, logic CAD, circuit CAD, integrated logic circuits, power dissipation, VLSI circuits, logic partitioning, delay optimal
1	Frank Vahid, Daniel D. Gajski	Clustering for improved system-level functional partitioning.	ISSS	1995	DBLP DOI BibTeX RDF	N-way partitioning, fast heuristics, hardware components, highly-optimizing heuristics, multiple system components, reduced runtimes, system-level functional partitioning, clustering, formal specification, quality, VHDL, software components, merging, logic partitioning
1	Wen Ching Wu, Chung-Len Lee, Jwu E. Chen	Identification of robust untestable path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	robust untestable path delay faults, path reconvergence of fanouts, ISCAS 85' circuits, total path delay faults, six-valued logic, propagation graph, ROUNTEST program, fault diagnosis, logic testing, delays, partitioning, ATPG, combinational circuits, combinational circuits, automatic testing, logic CAD, multivalued logic, logic partitioning, signal flow graphs, fault identification
1	Zuan Zhang	An approach to hierarchy model checking via evaluating CTL hierarchically.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	hierarchy model checking, CTL specifications, computational complexity, formal specification, formal verification, Symbolic Model Checking, formal logic, CTL, logic partitioning, hierarchical systems, Computational Tree Logic, local properties
1	Harry Hollander, Bradley S. Carlson, Toby D. Bennett	Synthesis of SEU-tolerant ASICs using concurrent error correction.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	radiation hardening (electronics), SEU-tolerant ASIC synthesis, single error correction/double error detection Hamming code, delay overhead, memory element set partitioning, error correction codes, sequential circuits, sequential circuit, application specific integrated circuits, logic CAD, circuit layout CAD, single event upsets, logic partitioning, Hamming codes, fault tolerant design, area overhead, memory elements, design experiments, concurrent error correction
1	Zijian Zhou, Xiaoyu Song, Francisco Corella, Eduard Cerny, Michel Langevin	Partitioning transition relations efficiently and automatically.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	automatic partitioning, state transition relations, abstract implicit state enumeration procedure, automatic verification method, graph theory, finite state machines, logic CAD, state estimation, logic partitioning, extended finite state machines, register transfer level designs, multiway decision graphs
1	Minesh B. Amin, Bapiraju Vinnakota	Data parallel fault simulation. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	data parallel fault simulation, compute intensive problem, fault simulation time, fault set partitioning technique, low cost parallel resource, logic gate level, parallel programming, fault diagnosis, logic testing, logic CAD, circuit analysis computing, workstations, logic partitioning, multiple processors
1	Steven Parkes, Prithviraj Banerjee, Janak H. Patel	A parallel algorithm for fault simulation based on PROOFS . (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	fault partitioning, dynamic partitioning schemes, compute intensive task, integrated circuit design process, rapid design turn around, ProperPROOFS, parallel extension, PROOFS fault simulation package, distributed method, fault redistribution, ISCAS-89 benchmark set, high performance serial fault simulation applications, parallel algorithms, parallel algorithm, parallel architectures, parallel architectures, fault diagnosis, logic testing, sequential circuits, sequential circuits, circuit analysis computing, logic partitioning
1	U. K. Bhattacharyya, I. Sen Gupta, S. Shyama Nath, P. Dutta	PLA based synthesis and testing of hazard free logic.	VLSI Design	1995	DBLP DOI BibTeX RDF	PLA based synthesis, hazard free logic, multilevel network, supergate partitioning, multi-output circuits, testing, logic testing, design for testability, combinational circuits, logic CAD, testability, programmable logic arrays, logic partitioning, combinational networks, hazards and race conditions
1	B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh	A new methodology for the design of low-cost fail safe circuits and networks.	VLSI Design	1995	DBLP DOI BibTeX RDF	low-cost fail safe circuits, safety critical electronic systems, input-output encoding problems, output encoding technique, low-cost design, systematic framework, graph theory, design methodology, encoding, combinational circuits, combinational circuits, graph embedding, graceful degradation, logic partitioning
1	Khushro Shahookar, Pinaki Mazumder	Genetic multiway partitioning.	VLSI Design	1995	DBLP DOI BibTeX RDF	genetic multiway partitioning, result quality, binary chromosome, bit-mask operations, net cut evaluation, MCNC benchmark circuits, cut size, genetic algorithms, VLSI, VLSI, CAD, software tools, software tool, logic CAD, mutation, circuit CAD, crossover, cellular arrays, cost function, circuit optimisation, logic partitioning, multiple objectives, bipartitioning
1	Jin-Tai Yan, Pei-Yung Hsiao	A new fuzzy-clustering-based approach for two-way circuit partitioning.	VLSI Design	1995	DBLP DOI BibTeX RDF	fuzzy-clustering-based approach, two-way circuit partitioning, circuit netlist, undirected edge-weighted graph, tree net model, clustering distance, area information, area-balanced constraints, circuit benchmarks, VLSI, simulated annealing, network topology, trees (mathematics), fuzzy set theory, logic partitioning, fuzzy c-means clustering, fuzzy memberships
1	Xinli Gu	RT level testability-driven partitioning.	VTS	1995	DBLP DOI BibTeX RDF	testability-driven partitioning, RT level designs, hard-to-test points, testability analysis algorithm, normal mode, design function, test mode, acyclic partition, BIST technique, fault diagnosis, logic testing, built-in self test, integrated circuit testing, design for testability, ATPG, automatic testing, logic CAD, fault coverage, logic partitioning, test application time, data path, testability measurements, DFT techniques
1	Samir Lejmi, Bozena Kaminska, Bechir Ayari	Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	segmentation cells, segmentation edges, logic testing, partitioning, timing, sequential circuits, sequential circuits, iterative methods, circuit analysis computing, retiming, iterative algorithm, circuit optimisation, logic partitioning, logic optimization, resynthesis, synchronous circuits, pseudo-exhaustive testing
1	David E. Long, Mahesh A. Iyer, Miron Abramovici	Identifying sequentially untestable faults using illegal states.	VTS	1995	DBLP DOI BibTeX RDF	sequentially untestable faults, illegal states, FILL algorithm, FUNI algorithm, functional partitioning procedure, incremental building, fault diagnosis, logic testing, test generator, integrated circuit testing, sequential circuits, automatic testing, binary decision diagrams, synchronous sequential circuit, logic partitioning, partial solution
1	Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara	Compact test generation for bridging faults under I/sub DDQ/ testing.	VTS	1995	DBLP DOI BibTeX RDF	compact test generation, bit-adders, logic testing, partitioning, integrated circuit testing, fault location, stuck-at faults, CMOS logic circuits, bridging faults, logic partitioning, I/sub DDQ/ testing
1	K. De, P. Banerjee	PREST: a system for logic partitioning and resynthesis for testability.	IEEE Trans. VLSI Syst.	1993	DBLP DOI BibTeX RDF
1	Chien-In Henry Chen, Joel T. Yuen	Logic partitioning to pseudo-exhaustive test for BIST design.	ICCAD	1993	DBLP DOI BibTeX RDF
1	Kaushik De, Prithviraj Banerjee	Logic Partitioning and Resynthesis for Testability.	ITC	1991	DBLP DOI BibTeX RDF
1	Chet A. Palesko, Lex A. Akers	Logic Partitioning for Minimizing Gate Arrays.	IEEE Trans. on CAD of Integrated Circuits and Systems	1983	DBLP DOI BibTeX RDF
1	Tadakatsu Ishiga, Tokinori Kozawa, Shoji Sato	A logic partitioning procedure by interchanging clusters.	DAC	1975	DBLP BibTeX RDF
1	Maurice Hanan, Angelo Mennone, Peter K. Wolff Sr.	Iterative-Interactive Technique for Logic Partitioning.	IBM Journal of Research and Development	1974	DBLP BibTeX RDF
1	Maurice Hanan, Angelo Mennone, Peter K. Wolff Sr.	An interactive man-machine approach to the computer logic partitioning problem.	DAC	1974	DBLP BibTeX RDF
1	A. J. Stone	Logic partitioning.	DAC	1966	DBLP DOI BibTeX RDF