Search results for "logic simulators"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Karen Panetta Lentz, Elias S. Manolakos, Edward C. Czeck	A multiple domain environment for efficient simulation.	Annual Simulation Symposium	1997	DBLP DOI BibTeX RDF	multiple domain environment, efficient simulation, concurrent simulation methodology, digital logic experimentation, multiple experiment environment, independent experiments, parallel hardware, digital logic simulators, signature paths, multiple experiment algorithms, function list, dynamic interactions, exhaustive simulation problem, Multiple Stuck-at Fault simulations, logic CAD, coverage analysis, digital logic
2	Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia	Fast discrete function evaluation using decision diagrams.	ICCAD	1995	DBLP DOI BibTeX RDF	address lookups, cycle-based logic simulation, decision-diagram based function evaluation, fast discrete function evaluation, latch ports, orders-of-magnitude potential speedup, output ports, logic design, memory hierarchy, logic CAD, decision theory, circuit analysis computing, memory bandwidth, table lookup, digital circuits, logic simulators, logic function, function evaluation, multi-valued decision diagrams
2	Timothy J. McBrayer, Philip A. Wilsey	Process combination to increase event granularity in parallel logic simulation. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	event granularity, VHDL description, parallel processing, logic CAD, circuit analysis computing, logic circuits, logic circuits, symmetric multiprocessors, logic simulation, digital system design, parallel logic simulation, parallel logic simulators
1	Morteza Fayyazi, Laurent Kirsch	Efficient simulation of oscillatory combinational loops.	DAC	2010	DBLP DOI BibTeX RDF	oscillatory combinational loops, emulation, functional verification
1	Bo D. Wang, Yuhao Zhu, Yangdong Deng	Distributed time, conservative parallel logic simulation on GPUs.	DAC	2010	DBLP DOI BibTeX RDF	CMB algorithm, gate-level simulation, GPU, discrete event simulation
1	Zachary Kurmas	Improving student performance using automated testing of simulated digital logic circuits.	ITiCSE	2008	DBLP DOI BibTeX RDF	JLS, simulation, testing, digital logic
1	Chin-Lung Chuang, Wei-Hsiang Cheng, Dong-Jung Lu, Chien-Nan Jimmy Liu	Hybrid Approach to Faster Functional Verification with Full Visibility.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	simulator, emulator, visibility, hybrid, functional verification, debugging environment
1	Chin-Lung Chuang, Dong-Jung Lu, Chien-Nan Jimmy Liu	A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
1	Mariko Sakamoto, Larry Brisson, Akira Katsuno, Aiichiro Inoue, Yasunori Kimura	Reverse Tracer: A Software Tool for Generating Realistic Performance Test Programs.	HPCA	2002	DBLP DOI BibTeX RDF	Multi-user Interactive Workload, System Level Performance, Instruction Trace, Software Tool, Logic Simulator, Hardware Design, Performance Test
1	C. Baena, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos J. Jiménez, Manuel Valencia	Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level.	PATMOS	2002	DBLP DOI BibTeX RDF
1	Lorena Anghel, Michael Nicolaidis	Cost Reduction and Evaluation of a Temporary Faults Detecting Technique.	DATE	2000	DBLP DOI BibTeX RDF
1	Damian Dalton	Analysis of an Associative Array Parallel Logic Simulator. (PDF / PS)	ICPP Workshops	1999	DBLP DOI BibTeX RDF
1	Walling R. Cyre	Executing Conceptual Graphs.	ICCS	1998	DBLP DOI BibTeX RDF
1	Jainendra Kumar	Prototyping the M68060 for Concurrent Verification.	IEEE Design & Test of Computers	1997	DBLP DOI BibTeX RDF
1	Karen Panetta Lentz, Elias S. Manolakos, Edward C. Czeck, Jamie A. Heller	Multiple Experiment Environments for Testing.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	concurrent fault simulation, multiple stuck-at, interactive experimentation, scenario
1	Jianmin Li, Chung-Kuan Cheng	Routability improvement using dynamic interconnect architecture.	FCCM	1995	DBLP DOI BibTeX RDF
1	Jainendra Kumar, Noel R. Strader, Jeff Freeman, Michael Miller	Emulation verification of the Motorola 68060. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	emulation verification, Motorola 68060, hardware logic emulation, configurable hardware, circuit verification, pseudo-random verification vectors, software application programs, formal verification, microprocessors, reconfigurable architectures, logic CAD, digital simulation, circuit analysis computing, RTL, hardware description languages, hardware description language, microprocessor chips, HDL, gate-level
1	Randal E. Bryant	A Methodology for Hardware Verification Based on Logic Simulation.	J. ACM	1991	DBLP DOI BibTeX RDF
1	Prathima Agrawal, William J. Dally	A hardware logic simulation system.	IEEE Trans. on CAD of Integrated Circuits and Systems	1990	DBLP DOI BibTeX RDF
1	Dan Adler	A Dynamically-Directed Switch Model for MOS Logic Simulation.	DAC	1988	DBLP BibTeX RDF
1	Edward P. Stabler, H. Bingol	Boolean Comparison by Simulation.	DAC	1987	DBLP DOI BibTeX RDF
1	George Varghese, Anthony Lauck	Hashed and Hierarchical Timing Wheels: Data Structures for the Efficient Implementation of a Timer Facility.	SOSP	1987	DBLP DOI BibTeX RDF
1	Kenneth F. Wong, Mark A. Franklin, Roger D. Chamberlain, B. L. Shing	Statistics on logic simulation.	DAC	1986	DBLP DOI BibTeX RDF
1	Vighneswara Row Mokkarala, Antony Fan, Ravi Apte	A unified approach to simulation and timing verification at the functional level.	DAC	1985	DBLP DOI BibTeX RDF
1	Will Sherwood	A hybrid scheduling technique for hierarchical logic simulators or "Close Encounters of the Simulated Kind".	DAC	1979	DBLP BibTeX RDF