Search results for "logic testing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Arabi Keshk, Yukiya Miura, Kozo Kinoshita	Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	circuit oscillations, transistor level networks, feedback oscillation, Byzantine General's problems, logic threshold, logic testing, logic testing, integrated circuit testing, fault coverage, fault location, bridging fault, CMOS circuits, CMOS digital integrated circuits, test vector
2	Noritaka Kobayashi, Tatsuhiro Tsuchiya, Tohru Kikuno	Applicability of Non-Specification-Based Approaches to Logic Testing for Software.	DSN	2001	DBLP DOI BibTeX RDF	factor covering design, software testing, logic testing, mutation analysis, boolean specification
2	Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen	Peak-power reduction for multiple-scan circuits during test application.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	peak-power reduction, multiple scan chain based circuits, peak periodicity, peak width, power waveforms, scan-based circuits, delay buffers, interleaving scan technique, data output, logic testing, logic testing, delays, integrated circuit testing, application specific integrated circuits, SOC, boundary scan testing
2	Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang	Novel techniques for improving testability analysis.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	closed-form formulation, implication reasoning, TAIR, tree-structured circuit, logic testing, logic testing, controllability, controllability, built-in self test, automatic test pattern generation, BIST, observability, observability, stuck-at fault, shift registers, testability analysis, test patterns
2	Mukund Sivaraman, Andrzej J. Strojwas	Diagnosis of parametric path delay faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	parametric path delay faults, chip failure, fabrication process parameter values, path sensitization mechanism, path delay conditions, ISCAS'89 benchmark circuits, path segment, circuit failure, fault diagnosis, logic testing, logic testing, delays, probability, probability, statistical analysis, statistical analysis, integrated circuit testing, failure analysis, diagnosability, delay fault testing, IC testing, production testing
2	Nur A. Touba, Edward J. McCluskey	Test point insertion based on path tracing.	VTS	1996	DBLP DOI BibTeX RDF	probabilistic techniques, primary inputs, insertion methods, VLSI, VLSI, fault diagnosis, logic testing, logic testing, probability, built-in self test, timing, integrated circuit testing, BIST, automatic testing, fault coverage, test point insertion, path tracing, circuit-under-test
2	Shiyi Xu, Gercy P. Dias	Testability forecasting for sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	testability forecasting, transitive closure algorithm, number of test patterns, computational complexity, fault diagnosis, logic testing, logic testing, statistical analysis, design for testability, sequential circuits, sequential circuits, logic CAD, fault coverage, regression models, automatic test software, CPU time, test generation algorithms
2	Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges	Statistical estimation of delay fault detectabilities and fault grading.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	delay fault detectabilities, fault grading, STAFAN, transition observabilities, fanout stems, fanout free region, gate line transition controllabilities, VLSI, fault diagnosis, logic testing, logic testing, statistical analysis, fault coverage, benchmark circuits, statistical estimation
2	Shih-Yuang Su, Cheng-Wen Wu	Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	sequential faults, ILA, M-testability, constant-length test sequence, pipelined array multiplier, sequential fault testing, logic testing, logic testing, sequential circuits, test pattern generation, logic arrays, combinatorial circuits, test vectors, C-testability, iterative logic arrays, iterative logic array
1	Garrett Kent Kaminski, Paul Ammann	Applications of Optimization to Logic Testing.	ICST Workshops	2010	DBLP DOI BibTeX RDF
1	Rajat Subhra Chakraborty, Francis G. Wolff, Somnath Paul, Christos A. Papachristou, Swarup Bhunia	MERO: A Statistical Approach for Hardware Trojan Detection.	CHES	2009	DBLP DOI BibTeX RDF
1	Garrett Kent Kaminski, Gregory Williams 0002, Paul Ammann	Reconciling perspectives of software logic testing.	Softw. Test., Verif. Reliab.	2008	DBLP DOI BibTeX RDF
1	Laung-Terng Wang, Charles E. Stroud, Kwang-Ting (Tim) Cheng	Logic Testing.	Wiley Encyclopedia of Computer Science and Engineering	2008	DBLP DOI BibTeX RDF
1	Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia	On-Demand Transparency for Improving Hardware Trojan Detectability.	HOST	2008	DBLP DOI BibTeX RDF
1	Mikhail Kharlamov, Alexey Polovinkin, Ekaterina Kondrateva, Alexey Lobachev	Beyond Brute Force: Testing Financial Software.	IT Professional	2008	DBLP DOI BibTeX RDF
1	Jason G. Brown, R. D. (Shawn) Blanton	A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	fault diagnostic accuracy, nanofabrication, regular architectures, nanoFabric, fault diagnosis, logic testing, reconfigurability, integrated circuit testing, fault coverage, nanoelectronics, high defect densities
1	Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi	Using the inter- and intra-switch regularity in NoC switch testing.	DATE	2007	DBLP DOI BibTeX RDF
1	Stéphane Ducasse, Tudor Gîrba, Roel Wuyts	Object-Oriented Legacy System Trace-based Logic Testing.	CSMR	2006	DBLP DOI BibTeX RDF	testing, logic programming, legacy systems, dynamic information
1	Mehdi Baradaran Tahoori	Application-Dependent Testing of FPGAs.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita	Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	scan tree, logic testing, design for testability, sequential circuit
1	Stephen Pateras	Security vs. Test Quality: Fully Embedded Test Approaches Are the Key to Having Both.	ITC	2004	DBLP DOI BibTeX RDF
1	Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi	A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide.	MTV	2004	DBLP DOI BibTeX RDF
1	Scott Davidson	A practical look at ATPG.	IEEE Design & Test of Computers	2004	DBLP DOI BibTeX RDF
1	Krishnendu Chakrabarty, Markus Seuring	Space compaction of test responses using orthogonal transmission functions [logic testing].	IEEE T. Instrumentation and Measurement	2003	DBLP DOI BibTeX RDF
1	Rubin A. Parekhji	Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Noritaka Kobayashi, Tatsuhiro Tsuchiya, Tohru Kikuno	Non-specification-based approaches to logic testing for software.	Information & Software Technology	2002	DBLP DOI BibTeX RDF
1	Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada	Test Time Reduction for I DDQ Testing by Arranging Test Vectors.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
1	Antonio Zenteno, Víctor H. Champac, Joan Figueras	Detectability Conditions of Full Opens in the Interconnections.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	logic testing, IDDQ testing, opens, defect modeling
1	Tsuyoshi Shinogi, Tomokazu Kanbayashi, Tomohiro Yoshikawa, Shinji Tsuruoka, Terumine Hayashi	Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG Systems.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
1	Ameet Bagwe, Rubin A. Parekhji	Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	fault coverage enhancement, embedded core based systems, test constraints, Texas Instruments TMS320C27xx, memory wrapper logic, fault diagnosis, logic testing, integrated circuit testing, application specific integrated circuits, functional testing, digital signal processing chips, fault analysis
1	Ismet Bayraktaroglu, Alex Orailoglu	Accumulation-based concurrent fault detection for linear digital state variable systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	concurrent fault detection, linear digital state variable systems, algorithmic fault detection scheme, accumulation-based approach, fault diagnosis, logic testing, error detection, error detection, linear systems, digital filters, digital signal processing chips, digital systems, area overhead
1	Paul Chang, Brion L. Keller, Sarala Paliwal	Effective parallel processing techniques for the generation of test data for a logic built-in self test system.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	logic built-in self test, complex processor, simulation time, random stimulus generation, signature computation, Pseudo-Random Pattern Generators, serial compression, response data, serial pattern dependency, parallel processing, parallel processing, logic testing, partitioning, built-in self test, integrated circuit testing, automatic test pattern generation, signatures, parallel simulation, microprocessor chips, logic simulation, logic simulation, post processing, logic partitioning, test data
1	Wu-Tung Cheng	Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	test logic, deep Sub-Micron technologies, scan-based ATPG, test application cost, test development, VLSI, CAD, logic testing, built-in self test, system on chip, SoC, automatic test pattern generation, automatic test pattern generation, ATPG, BIST, VLSI design, integrated circuit design, circuit CAD, VLSI testing, embedded memories, test quality, integrated circuit economics
1	Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer	A new framework for static timing analysis, incremental timing refinement, and timing simulation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	incremental timing refinement, signal arrival, target fault, test generation efficiency, logic testing, delays, timing, test generation, integrated circuit testing, computation, automatic test pattern generation, ATPG, static timing analysis, delay model, timing simulation
1	Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang	Charge sharing fault analysis and testing for CMOS domino logic circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	charge sharing fault analysis, CMOS domino logic circuits, domino logic design, sensitivity measurement, domino gate, fault diagnosis, logic testing, delays, delay, automatic testing, CMOS logic circuits, logic gates, test vectors
1	Chen-Huan Chiang, Sandeep K. Gupta	BIST TPG for SRAM cluster interconnect testing at board level.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
1	Marie-Lise Flottes, Christian Landrault, A. Petitqueux	Design for sequential testability: an internal state reseeding approach for 100 % fault coverage.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	sequential testability, internal state reseeding, observation points, minimum DFT insertion, non-scan approach, fault efficiency, 100 percent, fault diagnosis, logic testing, controllability, controllability, design for testability, logic design, sequential circuits, automatic test pattern generation, ATPG, observability, fault coverage, flip-flops, at-speed testing, benchmark circuits, CPU time, partial reset
1	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	An adjacency-based test pattern generator for low power BIST design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, adjacency-based test pattern generator, low power BIST design, pseudo-random TPG, test-per-clock BIST, peak power consumption, total energy consumption, strongly connected circuits, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, test length
1	Emil Gizdarski, Hideo Fujiwara	Spirit: satisfiability problem implementation for redundancy identification and test generation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	Boolean satisfiability method, SPIRIT, ATPG system, logic testing, computability, automatic test pattern generation, combinational circuits, combinational circuits, test pattern generation, test sets
1	Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda	High speed IDDQ test and its testability for process variation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	high speed IDDQ test, charge current, gate load capacitances, test input vector application, CMOS IC production, logic testing, integrated circuit testing, process variation, testability, CMOS logic circuits, production testing
1	F. Hayat, Thomas W. Williams, Rohit Kapur, D. Hsu	DFT closure.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	area requirement, power requirement, timing closure flow, logic testing, SoC, integrated circuit testing, design for testability, automatic testing, application specific integrated circuits, ASIC, testability
1	Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita	Test sequence compaction for sequential circuits with reset states.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	reset states, test compaction method, single stuck-at fault assumption, unremovable vectors, fault-dropping fault simulation, nonfault-dropping fault simulation, reset signal, test subsequences, logic testing, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, fault simulation, vectors, logic simulation, logic simulation, benchmark circuits, test vectors, signal detection, test sequence compaction
1	Hiromi Hiraishi	Verification of deadlock free property of high level robot control.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	deadlock free property, high level robot control, verification algorithm, task control architecture, concurrent robot control processes, symbolic model verifier, symbolic model checking algorithm, robots, formal verification, logic testing, concurrency control, message passing, symbol manipulation, safety properties, liveness properties
1	Junichi Hirase, Shinichi Yoshimura	Faster processing for microprocessor functional ATPG.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	microprocessor functional ATPG, fault coverage improvement, short test pattern, processing speed increase, logic testing, integrated circuit testing, automatic test pattern generation, identification, test pattern generation, functional testing, microprocessor chips, instruction sets, instruction sets, microprocessor tests
1	Andrzej Hlawiczka, Michal Kopec	Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	serial seeding, linear hybrid cellular automata, n-cell CA register, p CdSR registers, cellular automata quasi shift register, PCASR, n-bit input sequence, logic testing, cellular automata, integrated circuit testing, automatic test pattern generation, application specific integrated circuits, polynomials, polynomial, logic CAD, cost, TPG, flip-flops, flip-flops, shift registers, pattern generators, integrated circuit economics
1	Der-Cheng Huang, Wen-Ben Jone	An efficient parallel transparent diagnostic BIST.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	parallel transparent diagnostic BIST, built-in self-diagnosis method, multiple embedded memory arrays, transparent diagnostic interface, redundant read/write/shift operations, march algorithm, TDiagRSMarch algorithm, low hardware overhead, test time reduction, diagnostic efficiency, parallel algorithms, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic testing, test coverage, integrated memory circuits
1	Michiko Inoue, Emil Gizdarski, Hideo Fujiwara	A class of sequential circuits with combinational test generation complexity under single-fault assumption.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	combinational test generation complexity, internally balanced structures, combinational test generation, separable primary inputs, undetectability, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic test pattern generation, combinational circuits, test sequence, single stuck-at-faults, multiple stuck-at faults, single-fault
1	Seiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy	Enhanced untestable path analysis using edge graphs.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	untestable path analysis, edge graphs, partial path sensitization, edge graph, logic testing, logic circuits, logic circuits, path delay fault testing
1	Ding-Ming Kwai, Hung-Wen Chang, Hung-Jen Liao, Ching-Hua Chiao, Yung-Fa Chou	etection of SRAM cell stability by lowering array supply voltage.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cell stability detection, array supply voltage reduction, design-for-test technique, static random access memory, memory array, test mode, detection capability, logic testing, integrated circuit testing, design for testability, CMOS technology, SRAM chips, CMOS memory circuits, DFT technique, circuit stability, 0.18 micron
1	Michael J. Liebelt, Cheng-Chew Lim	A method for determining whether asynchronous circuits are self-checking.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, TSC, low noise properties, semi-modular asynchronous circuit, output stuck-at-faults, low power, fault diagnosis, logic testing, integrated circuit testing, design for testability, asynchronous circuits, testability, totally self-checking, integrated circuit noise
1	Jin-Cherng Lin, Pu-Lin Yeh	Using genetic algorithms for test case generation in path testing.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	survival of the fittest theory, operator sequences, genetic algorithms, genetic algorithms, real-time systems, logic testing, SIMILARITY, automatic test pattern generation, test case generation, fitness function, program execution, path testing
1	Eric MacDonald, Nur A. Touba	Testing domino circuits in SOI technology.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	silicon-on-insulator, SOI technology, dynamic circuit styles, fault modeling analysis, overall fault coverage, parasitic bipolar leakage, CMOS logic, logic testing, integrated circuit testing, automatic testing, fault simulation, CMOS logic circuits, leakage currents, domino circuits
1	Toshiyuki Maeda, Kozo Kinoshita	Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction
1	Yiorgos Makris, Jamison Collins, Alex Orailoglu	Fast hierarchical test path construction for DFT-free controller-datapath circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	fast hierarchical test path construction, DFT-free controller-datapath circuits, transparency based scheme, locally generated vectors, global design test, influence tables, valid control state sequences, module testing, fault coverage levels, vector counts, logic testing, test generation, automatic test pattern generation, ATPG, computational cost reduction
1	Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara	Single-control testability of RTL data paths for BIST.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test
1	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu	Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	distribution-graph based approach, extended tree growing technique, power-constrained block-test scheduling, unequal-length block-test scheduling, power dissipation constraints, test concurrency, assigned power dissipation limits, balanced test power dissipation, least mean square error function, global priority function, system-level test scheduling algorithm, scheduling, VLSI, fault diagnosis, logic testing, high level synthesis, integrated circuit testing, automatic test pattern generation, trees (mathematics), least mean squares methods
1	Irith Pomeranz, Sudhakar M. Reddy	Reducing test application time for full scan circuits by the addition of transfer sequences.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	transfer sequences, primary input vectors, scan-in operation, scan-out operation, static compaction procedure, compaction levels, fault diagnosis, logic testing, design for testability, fault detection, automatic testing, boundary scan testing, test set, test application time, full scan circuits
1	Irith Pomeranz, Sudhakar M. Reddy	On the feasibility of fault simulation using partial circuit descriptions.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	partial circuit description, gate-level circuits, subcircuits, logic testing, fault simulation, fault simulation, memory requirements
1	Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian	TOF: a tool for test pattern generation optimization of an FPGA application oriented test.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	TOF tool, test pattern generation optimization, FPGA application oriented test, application-oriented test procedure, RAM-based FPGAs, AC nonredundant fault coverage, circuit netlist, TPG optimisation tool, field programmable gate arrays, logic testing, optimisation, integrated circuit testing, automatic test pattern generation, ATPG
1	Ming-Der Shieh, Hsin-Fu Lo, Ming-Hwa Sheu	High-speed generation of LFSR signatures.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	high-speed generation, LFSR signatures, compaction simulation, single-input signature register, equivalent multiple-input implementation, finite field theory, high-speed signature computations, lookahead technique, internal-XOR LFSR, external-XOR LFSR, performance evaluation, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, BIST, linear feedback shift register, binary sequences, subsequences
1	Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy	Fsimac: a fault simulator for asynchronous sequential circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	Fsimac, gate-level fault simulator, Muller C-elements, complex domino gates, high-speed design, min-max timing analysis, min-max rime stamps, CA-BIST, waveform model, logic testing, built-in self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuck-at faults, iterations, delay faults, combinational logic, feedback loops, pseudo-random tests, gate-delay faults, asynchronous sequential circuits
1	Wei-Lun Wang, Kuen-Jong Lee	Accelerated test pattern generators for mixed-mode BIST environments.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	accelerated test pattern generators, mixed-mode BIST, pseudorandom patterns, deterministic patterns, scan-based built-in self-test, multiple sub-chains, multiple sequence generator, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, linear feedback shift registers, cost, test pattern generator, shift registers, test application time, scan chain, mixed analogue-digital integrated circuits, clock cycle, integrated circuit economics
1	Hsin-Po Wang, Jon Turino	DFT and BIST techniques for the future.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	multimillion gate system-on-chip, multinational design, logic testing, built-in self test, design for testability, quality, BIST, economics, DFT, integrated circuit design, time to market, production testing, IC design, integrated circuit economics
1	Shiyi Xu, Wei Cen	Forecasting the efficiency of test generation algorithms for digital circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	efficiency forecasting, testability parameters, genetic algorithms, genetic algorithms, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic test pattern generation, ATPG, combinational circuits, combinational circuits, digital circuits, VLSI circuits, digital integrated circuits, test generation algorithms
1	Ruofan Xu, Michael S. Hsiao	Embedded core testing using genetic algorithms.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	gate level implementation, user defined logic, random inputs, high level benchmarks, wrapper size, genetic algorithms, genetic algorithms, fault diagnosis, logic testing, controllability, controllability, high level synthesis, automatic test pattern generation, observability, observability, application specific integrated circuits, fault coverage, SOC, test application time, test patterns, embedded core testing, internal state
1	Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama	Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic.	PRDC	2000	DBLP DOI BibTeX RDF	dual-rail differential logic, multiple-valued current-mode circuits, asynchronous-control circuit, logic testing, asynchronous circuits, self-checking circuit, current-mode logic, current-mode circuits
1	Irith Pomeranz, Sudhakar M. Reddy	Fault diagnosis based on parameters of output responses.	PRDC	2000	DBLP DOI BibTeX RDF	output responses parameters, unmodeled faults, fault diagnosis, fault diagnosis, logic testing, sequential circuits, dictionaries, synchronous sequential circuits, diagnostic resolution
1	Masayuki Tsukisaka, Takashi Nanya	A testable design for asynchronous fine-grain pipeline circuits.	PRDC	2000	DBLP DOI BibTeX RDF	asynchronous fine-grain pipeline circuits, dynamic gates, high-performance datapath design, pipeline latches, scan latch libraries, logic testing, logic CAD, SPICE, CMOS technology, scan path, SPICE simulation, testable design
1	Wen-Feng Chang, Cheng-Wen Wu	Low-Cost Modular Totally Self-Checking Checker Design for m-out-of-n Code.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Fault tolerance, logic testing, on-line testing, totally-self-checking checker, m-out-of-n code
1	Markus Rudack, Dirk Niggemeyer	Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM. (PDF / PS)	DFT	1999	DBLP DOI BibTeX RDF
1	Brian Chess, Tracy Larrabee	Logic Testing of Bridging Faults in CMOS Integrated Circuits.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	realistic faults, fault models, fault simulation, test pattern generation, Bridging faults
1	Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita	Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Teruhiko Yamada, Tsuneto Hanashima, Yasuhiro Suemori, Masaaki Maezawa	On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Wei-Kang Huang, Fred J. Meyer, Xiao-Tao Chen, Fabrizio Lombardi	Testing configurable LUT-based FPGA's.	IEEE Trans. VLSI Syst.	1998	DBLP DOI BibTeX RDF
1	Tzuhao Chen, Ibrahim N. Hajj	GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment.	ICCAD	1997	DBLP DOI BibTeX RDF	GOLDENGATE, digital VLSI circuits, electrical-level simulation, event-driven technique, logic/I/sub DDQ/ testing, logic testing, sequential circuits, combinational circuits, bridging fault simulator
1	Christos A. Papachristou, Mikhail Baklashov	A test synthesis technique using redundant register transfers.	ICCAD	1997	DBLP DOI BibTeX RDF	behavioral variables, conditional statements, redundant register transfers, structural signals, test synthesis technique, testability metrics, graph theory, logic testing, controllability, high level synthesis, VHDL, observability, fault coverage, data path, hardware overhead, behavioral descriptions
1	Dominik Stoffel, Wolfgang Kunz	Record & play: a structural fixed point iteration for sequential circuit verification.	ICCAD	1997	DBLP DOI BibTeX RDF	circuit resynthesis, circuit retiming, combinational verification techniques, instruction queue, iterative circuit array, local circuit transformation, sequential circuit verification, sequential logic equivalence checking, structural fixed point iteration, time frame equivalence, logic testing, finite state machine, logic design
1	David Ashen, Fred J. Meyer, Nohpill Park, Fabrizio Lombardi	Testing of programmable logic devices (PLD) with faulty resources. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF	faulty resources, routing resources, built-in self-test schemes, parity chain, one-dimensional arrays, active routing devices, interconnection channels, input/output lines, logic testing, fault model, fault coverage, multiple faults, programmable logic devices, programmable logic devices
1	Zdenek Kotásek, F. Zboril	RT level testability analysis to reduce test application time.	EUROMICRO	1997	DBLP DOI BibTeX RDF	register transfer level testability analysis, RTL element classification, RTL circuit transformation, labelled directed graph, PROLOG environment, implementation principles, logic testing, test application time reduction
1	Rolf Drechsler, Martin Keim, Bernd Becker	Fault Simulation in Sequential Multi-Valued Logic Networks. (PDF / PS)	ISMVL	1997	DBLP DOI BibTeX RDF	sequential multi-valued logic networks, multi-valued logic networks, logic testing, sequential circuits, fault models, fault simulator, random pattern testability
1	Richard M. Chou, Kewal K. Saluja	Sequential Circuit Testing: From DFT to SFT.	VLSI Design	1997	DBLP DOI BibTeX RDF	design-for-testability methods, SFT techniques, large sequential circuits, logic testing, automatic test pattern generation, ATPG, synthesis-for-testability, sequential circuit testing, DFT techniques
1	Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee	Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation.	VLSI Design	1997	DBLP DOI BibTeX RDF	simulation-based test generation, distributed memory MIMD machines, shared memory MIMD machines, parallel search strategies, logic testing, fault coverage, NP-complete problems, VLSI circuits, parallel genetic algorithms, sequential circuit test generation
1	K. De	Test methodology for embedded cores which protects intellectual property.	VTS	1997	DBLP DOI BibTeX RDF	core I/Os, ASIC I/O inaccessibility, partial netlist generation, ASIC level test generation, gate testing, core scan chain, selective boundary scan, coreware design paradigm, logic testing, heuristic algorithm, structural analysis, intellectual property protection, embedded cores, test methodology
1	Irith Pomeranz, Sudhakar M. Reddy	On n-detection test sequences for synchronous sequential circuits343.	VTS	1997	DBLP DOI BibTeX RDF	n-detection test sequences, stuck-at fault detection, test generation procedures, logic testing, fault simulation, synchronous sequential circuits, defect coverages
1	Irith Pomeranz, Sudhakar M. Reddy	EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage.	VTS	1997	DBLP DOI BibTeX RDF	EXTEST, test generation procedure, logic testing, fault coverage, synchronous sequential circuits, test sequences
1	Michael L. Bushnell, John Giraldi	A Functional Decomposition Method for Redundancy Identification and Test Generation.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	redundancy identification, logic testing, automatic test generation, backtracing
1	Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki	Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	DFT circuit, test generation, pass-transistor logic, stuck-on fault
1	Sandeep Bhatia, Tushar Gheewala, Prab Varma	A Unifying Methodology for Intellectual Property and Custom Logic Testing.	ITC	1996	DBLP DOI BibTeX RDF
1	Minesh B. Amin, Bapiraju Vinnakota	Zamlog: a parallel algorithm for fault simulation based on Zambezi.	ICCAD	1996	DBLP DOI BibTeX RDF	Zambezi, Zamlog, sequential circuit fault simulator, uniprocessor simulator, parallel algorithm, logic testing, fault simulation, test sets, multiprocessor simulation
1	David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah	Timing verification of sequential domino circuits.	ICCAD	1996	DBLP DOI BibTeX RDF	domino gates, sequential domino circuits, static timing verification, logic testing, input signals
1	Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs	Identification of unsettable flip-flops for partial scan and faster ATPG.	ICCAD	1996	DBLP DOI BibTeX RDF	ISCAS89 circuits, deterministic test generation, difficult-to-set hip-hops, hip-hops, state elements, state justification, transformed circuits, unsettable flip-flops identification, logic testing, ATPG, partial scan, sequential circuits test generation
1	Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee	VERILAT: verification using logic augmentation and transformations.	ICCAD	1996	DBLP DOI BibTeX RDF	VERILAT, formal logic verification, implication-based methods, logic augmentation, logic transformations, logic testing
1	Kuen-Jong Lee, Jing-Jou Tang	Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	efficient modeling techniques, enhanced test generation performance, fault modeling technique, inter-gate faults, threshold determination method, SPICE like accuracy, digital logic gates, logic testing, fault simulation, CMOS logic circuits, bridging faults, IDDQ testing, CMOS circuits
1	Ghassan Al Hayek, Yves Le Traon, Chantal Robach	Considering Test Economics in the Process of Hardware/Software Partitioning.	EUROMICRO	1996	DBLP DOI BibTeX RDF	hardware/software testing, specifications, logic testing, estimate, testability, co-design, mutation-test, hardware/software partitioning, test economics
1	Rolf Drechsler	Verification of Multi-Valued Logic Networks. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	multi-valued logic networks verification, ordered multi-valued decision diagrams, two-valued circuits, formal verification, heuristics, logic testing, directed graphs, directed acyclic graph, multivalued logic circuits, functional equivalence
1	Mou Hu	Design of One-Vector Testable Binary Systems Based on Ternary Logic. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	ternary circuits, MOS circuit, logic testing, built-in self-test, design for testability, multiple-valued logic
1	Vishwani D. Agrawal, David Lee	Characteristic polynomial method for verification and test of combinational circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	combinational circuit test, randomly selected integers, input variables, integer-valued transform functions, fixed domain, multiple samples, randomly selected real numbers, output logic, logic testing, probability, Boolean functions, Boolean functions, combinational circuits, polynomials, error probability, characteristic polynomial
1	Tapan J. Chakraborty, Vishwani D. Agrawal	Design for high-speed testability of stuck-at faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	design for high-speed testability, stuck-at fault detection, signal transition, timing hazard, multivalue algebra, dh-robust test, sequential feedback, reconvergent fanout, cycle-free sequential circuit, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, partial scan, test generation algorithm, critical path delay
1	Debesh Kumar Das, Bhargab B. Bhattacharya	Does retiming affect redundancy in sequential circuits?	VLSI Design	1996	DBLP DOI BibTeX RDF	combinational redundancy, sequential redundancy, fault diagnosis, logic testing, timing, redundancy, test generation, design for testability, sequential circuits, sequential circuit, fault, retiming, logic optimization, operation speed
1	Sunil R. Das, N. Goel, Wen-Ben Jone, Amiya R. Nayak	Syndrome signature in output compaction for VLSI BIST.	VLSI Design	1996	DBLP DOI BibTeX RDF	syndrome signature, output compaction, VLSI BIST, input patterns, n-input combinational circuit, primary syndrome, subsyndromes, subfunctions, single-output circuit, multiple output, VLSI, logic testing, data compression, built-in self test, integrated circuit testing, combinational circuits, switching functions, exhaustive testing