Search results for "loop unrolling"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Mounira Bachir, Sid Ahmed Ali Touati, Albert Cohen	Post-pass periodic register allocation to minimise loop unrolling degree.	LCTES	2008	DBLP DOI BibTeX RDF	embedded code optimisation, periodic register allocation, software pipelining, loop unrolling
3	Jack W. Davidson, Sanjay Jinturkar	Aggressive Loop Unrolling in a Retargetable Optimizing Compiler.	CC	1996	DBLP DOI BibTeX RDF	Code improving transformations, Compiler optimizations, Loop transformations, Loop unrolling
2	Frank Hannig, Hritam Dutta, Jürgen Teich	Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning.	ARCS	2009	DBLP DOI BibTeX RDF
2	Ozana Silvia Dragomir, Todor Stefanov, Koen Bertels	Loop unrolling and shifting for reconfigurable architectures.	FPL	2008	DBLP DOI BibTeX RDF
2	Monica Magalhães Pereira, Sílvio R. F. de Araújo, Bruno Cruz de Oliveira, Ivan Saraiva Silva	Using traditional loop unrolling to fit application on a new hybrid reconfigurable architecture.	SAC	2008	DBLP DOI BibTeX RDF	stream-based, optimization, performance, reconfigurable architecture
2	Srikanth Kurra, Neeraj Kumar Singh, Preeti Ranjan Panda	The impact of loop unrolling on controller delay in high level synthesis.	DATE	2007	DBLP DOI BibTeX RDF
2	Betul Buyukkurt, Zhi Guo, Walid A. Najjar	Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs.	ARC	2006	DBLP DOI BibTeX RDF
2	Sarah Thompson, Alan Mycroft	Bit-level partial evaluation of synchronous circuits.	PEPM	2006	DBLP DOI BibTeX RDF	partial evaluation, loop unrolling, synchronous circuits
2	Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon	Automatic Task Scheduling / Loop Unrolling using Dedicated RTR Controllers in Coarse Grain Reconfigurable Architectures.	IPDPS	2005	DBLP DOI BibTeX RDF
2	João M. P. Cardoso, Pedro C. Diniz	Modeling Loop Unrolling: Approaches and Open Issues.	SAMOS	2004	DBLP DOI BibTeX RDF
2	Litong Song, Krishna M. Kavi	What can we gain by unfolding loops?	SIGPLAN Notices	2004	DBLP DOI BibTeX RDF	loop peeling, loop quasi invariant code motion, quasi-index variable, quasi-invariant variable, loop unrolling
2	Gayathri Krishnamurthy, Elana D. Granston, Eric Stotzer	Affinity-based cluster assignment for unrolled loops.	ICS	2002	DBLP DOI BibTeX RDF	affinity-based clustering (ABC) algorithms, homogeneous clusters, partitioned register files, software pipelining, loop optimizations, loop scheduling, VLIW architectures, loop unrolling, cluster assignment
2	F. Jesús Sánchez, Antonio González	The Effectiveness of Loop Unrolling for Modulo Scheduling in Clustered VLIW Architectures. (PDF / PS)	ICPP	2000	DBLP DOI BibTeX RDF
2	Michel J. Daydé, Iain S. Duff	The RISC BLAS: a blocked implementation of level 3 BLAS for RISC processors.	ACM Trans. Math. Softw.	1999	DBLP DOI BibTeX RDF	matrix-matrix kernels, blocking, loop-unrolling, level 3 BLAS, RISC processors
2	Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha	Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions.	ICCAD	1997	DBLP DOI BibTeX RDF	control-flow intensive, scheduling, parallelism, pipelining, loop unrolling
2	Seongbae Park, SangMin Shim, Soo-Mook Moon	Evaluation of Scheduling Techniques on a SPARC-based VLIW Testbed.	MICRO	1997	DBLP BibTeX RDF	SPARC-based VLIW testbed, VLIW microprocessors, Very Long Instruction Word microprocessors, all-path speculation, gcc-generated optimized SPARC code, high-performance VLIW code, nongreedy enhanced pipeline scheduling, nonspeculative operations, profile-based all-path speculation, restricted speculative loads, scheduling compiler, speculative operations, trace-based speculation, performance, compiler, computer architecture, parallel machines, software pipelining, loop unrolling, renaming, memory disambiguation, copies, scheduling techniques
2	Akira Koseki, Hideaki Komatsu, Yoshiaki Fukazawa	A method for estimating optimal unrolling times for nested loops.	ISPAN	1997	DBLP DOI BibTeX RDF	reuse of data, benchmark tests, parallelization, parallelism, heuristic algorithm, heuristic programming, nested loops, loop unrolling
2	Michael E. Wolf, Dror E. Maydan, Ding-Kai Chen	Combining Loop Transformations Considering Caches and Scheduling.	MICRO	1996	DBLP BibTeX RDF	cache tiling, fission, loop interchange, outer loop unrolling, fusion, instruction scheduling
2	Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor	A comparative evaluation of software techniques to hide memory latency.	HICSS	1995	DBLP DOI BibTeX RDF	comparative software evaluation, software oriented techniques, superscalar machines, superpipelined machines, software cache prefetching, data fetch request, software controlled prefetching, aggressive prefetching, memory bandwidth requirements, bus traffic, performance, parallel machines, program compilers, processor scheduling, software performance evaluation, software pipelining, pipeline processing, microarchitecture, cache storage, instruction set architecture, memory latency, loop unrolling, static scheduling, conditional branches
1	Johann Steinbrecher, Weijia Shang	On Optimizing the Longest Common Subsequence Problem by Loop Unrolling Along Wavefronts.	PDP	2012	DBLP DOI BibTeX RDF
1	Yosi Ben-Asher, Jawad Haj-Yihia	Computing the correct Increment of Induction Pointers with application to loop unrolling.	Journal of Systems Architecture - Embedded Systems Design	2010	DBLP DOI BibTeX RDF
1	Giridhar Sreenivasa Murthy, Mahesh Ravishankar, Muthu Manikandan Baskaran, Ponnuswamy Sadayappan	Optimal loop unrolling for GPGPU programs.	IPDPS	2010	DBLP DOI BibTeX RDF
1	Ozana Silvia Dragomir, Todor Stefanov, Koen Bertels	Optimal Loop Unrolling and Shifting for Reconfigurable Architectures.	TRETS	2009	DBLP DOI BibTeX RDF
1	Paul Lokuciejewski, Peter Marwedel	Combining Worst-Case Timing Models, Loop Unrolling, and Static Loop Analysis for WCET Minimization.	ECRTS	2009	DBLP DOI BibTeX RDF	WCET minimization, WCET-driven optimizations, High-Level Optimizations, compiler, WCET
1	Mounira Bachir, David Gregg, Sid Ahmed Ali Touati	Using the Meeting Graph Framework to Minimise Kernel Loop Unrolling for Scheduled Loops.	LCPC	2009	DBLP DOI BibTeX RDF
1	Like Yan, Gang Wang, Tianzhou Chen	The input-aware dynamic adaptation of area and performance for reconfigurable accelerator.	FPGA	2009	DBLP DOI BibTeX RDF	dynamic adaption, reconfigurable system, loop unrolling, loop accelerator
1	Nachiket Kapre, André DeHon	Accelerating SPICE Model-Evaluation using FPGAs.	FCCM	2009	DBLP DOI BibTeX RDF	Analog Circuit Simulator, VLIW Scheduling, Floating-Point, Spice, Loop Unrolling, Spatial Computation
1	Sudipta Kundu, Zachary Tatlock, Sorin Lerner	Proving optimizations correct using parameterized program equivalence.	PLDI	2009	DBLP DOI BibTeX RDF	compiler optimization, correctness, translation validation
1	Yosi Ben-Asher, Nadav Rotem	The effect of unrolling and inlining for Python bytecode optimizations.	SYSTOR	2009	DBLP DOI BibTeX RDF	optimizations, Python, bytecode, dynamic languages
1	Liu Peng, Richard Seymour, Ken-ichi Nomura, Rajiv K. Kalia, Aiichiro Nakano, Priya Vashishta, Alexander Loddoch, Michael Netzband, William R. Volz, Chap C. Wong	High-order stencil computations on multicore clusters.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Sheng Ma, Libo Huang, Zhiying Wang, Kui Dai	Implementation of OpenVG Path and Paint Algorithms on Synchronous Data Triggered Architecture with Optimization.	NAS	2009	DBLP DOI BibTeX RDF
1	Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivastava	Code Transformations for TLB Power Reduction.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Mohammed Fellahi, Albert Cohen	Software Pipelining in Nested Loops with Prolog-Epilog Merging.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Boyana Norris, Albert Hartono, Elizabeth R. Jessup, Jeremy G. Siek	Generating Empirically Optimized Composed Matrix Kernels from MATLAB Prototypes.	ICCS	2009	DBLP DOI BibTeX RDF	empirical performance tuning, code generation, MATLAB
1	Peter Gottschling, Andrew Lumsdaine	Integrating semantics and compilation: using c++ concepts to develop robust and efficient reusable libraries.	GPCE	2008	DBLP DOI BibTeX RDF	semantic verification, optimization, c++, concepts, loop unrolling, semantic properties
1	Li Wang, Xuejun Yang, Jingling Xue, Yu Deng, Xiaobo Yan, Tao Tang, Quan Hoang Nguyen	Optimizing scientific application loops on stream processors.	LCTES	2008	DBLP DOI BibTeX RDF	streaming, prefetching, graph coloring, data reuse, loop optimization, stream processor, software-managed cache
1	Pingjing Lu, Yonggang Che, Zhenghua Wang	An Effective Iterative Compilation Search Algorithm for High Performance Computing Applications.	HPCC	2008	DBLP DOI BibTeX RDF
1	Hojin Kee, Newton Petersen, Jacob Kornerup, Shuvra S. Bhattacharyya	Systematic generation of FPGA-based FFT implementations.	ICASSP	2008	DBLP DOI BibTeX RDF
1	Jing Du, Fujiang Ao, Xuejun Yang	MV-FT: Efficient Implementation for Matrix-Vector Multiplication on FT64 Stream Processor.	ICDS	2008	DBLP DOI BibTeX RDF
1	Mila Dalla Preda, Roberto Giacobazzi, Enrico Visentini	Hiding Software Watermarks in Loop Structures.	SAS	2008	DBLP DOI BibTeX RDF
1	Nicholas Nethercote, Doug Burger, Kathryn S. McKinley	Convergent Compilation Applied to Loop Unrolling.	T. HiPEAC	2007	DBLP DOI BibTeX RDF
1	Johann Großschädl, Stefan Tillich, Christian Rechberger, Michael Hofmann, Marcel Medwed	Energy evaluation of software implementations of block ciphers under memory constraints.	DATE	2007	DBLP DOI BibTeX RDF	energy optimization, code size reduction, symmetric cipher, lightweight cryptography, memory footprint
1	JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally	Register pointer architecture for efficient embedded processors.	DATE	2007	DBLP DOI BibTeX RDF
1	Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, Uma Srinivasan, Craig B. Zilles	Hardware atomicity for reliable software speculation.	ISCA	2007	DBLP DOI BibTeX RDF	Java, optimization, checkpoint, atomicity, speculation, isolation
1	Johann Großschädl, Stefan Tillich, Alexander Szekely	Performance Evaluation of Instruction Set Extensions for Long Integer Modular Arithmetic on a SPARC V8 Processor.	DSD	2007	DBLP DOI BibTeX RDF
1	Pan Yu, Tulika Mitra	Disjoint Pattern Enumeration for Custom Instructions Identification.	FPL	2007	DBLP DOI BibTeX RDF
1	Suhyun Kim, Soo-Mook Moon	Rotating Register Allocation for Enhanced Pipeline Scheduling.	PACT	2007	DBLP DOI BibTeX RDF
1	Viral K. Parikh, Poras T. Balsara, Oren Eliezer, Jaimin Mehta	A Low Area and Low Power Digital Band-Pass Sigma-Delta Modulator for Wireless Transmitters.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Martin Holzer 0002, Bastian Knerr, Markus Rupp	Design Space Exploration with Evolutionary Multi-Objective Optimisation.	SIES	2007	DBLP DOI BibTeX RDF
1	Yaobin Wang, Hong An, Bo Liang, Li Wang, Ming Cong, Yongqing Ren	Balancing Thread Partition for Efficiently Exploiting Speculative Thread-Level Parallelism.	APPT	2007	DBLP DOI BibTeX RDF
1	Joonseok Park, Pedro C. Diniz	Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations.	ARC	2007	DBLP DOI BibTeX RDF	scalar replacement, loop splitting, loop interchange, Field Programmable Gate Arrays (FPGA), Reconfigurable Computing, data reuse
1	Miao Wang, Guiming Wu, Zhiying Wang	Instruction Selection for Subword Level Parallelism Optimizations for Application Specific Instruction Processors.	ISPA	2007	DBLP DOI BibTeX RDF
1	Karine Heydemann, François Bodin, Peter M. W. Knijnenburg, Laurent Morin	UFS: a global trade-off strategy for loop unrolling for VLIW architectures.	Concurrency and Computation: Practice and Experience	2006	DBLP DOI BibTeX RDF
1	Gennette Gill, John Hansen, Montek Singh	Loop pipelining for high-throughput stream computation using self-timed rings.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Abhishek Das, William J. Dally, Peter R. Mattson	Compiling for stream processing.	PACT	2006	DBLP DOI BibTeX RDF	SRF allocation, Stream Operation Precedence (SOP) graph, StreamC, coarse-grained operations, producer-consumer locality, scoreboard slot assignment, stream scheduling, strip-mining, software-pipelining, task level parallelism, stream programming model
1	Sung-Chul Han, Franz Franchetti, Markus Püschel	Program generation for the all-pairs shortest path problem.	PACT	2006	DBLP DOI BibTeX RDF	Floyd-Warshall algorithm, SIMD vectorization, empirical search, tiling, blocking
1	Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi	Compile-time area estimation for LUT-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Reconfigurable computing, compiler optimization, resource estimation
1	Konrad Malkowski, Ingyu Lee, Padma Raghavan, Mary Jane Irwin	On improving performance and energy profiles of sparse scientific applications.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Bertrand A. Maher, Aaron Smith, Doug Burger, Kathryn S. McKinley	Merging Head and Tail Duplication for Convergent Hyperblock Formation.	MICRO	2006	DBLP DOI BibTeX RDF
1	Alireza Hodjat, Ingrid Verbauwhede	Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	crypto-processor, security, VLSI, cryptography, Advanced Encryption Standard (AES), ASIC, hardware architectures
1	Jae-Jin Lee, Gi-Yong Song	High-Level Synthesis Using SPARK and Systolic Array.	ARC	2006	DBLP DOI BibTeX RDF
1	Simon Hammond, David Lacey	Loop Transformations in the Ahead-of-Time Optimization of Java Bytecode.	CC	2006	DBLP DOI BibTeX RDF
1	Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung Paek	Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs.	EUC Workshops	2006	DBLP DOI BibTeX RDF
1	Mun-Kyu Lee, Jung Ki Min, Seok Hun Kang, Sang-Hwa Chung, Howon Kim, Dong Kyue Kim	Efficient Implementation of Pseudorandom Functions for Electronic Seal Protection Protocols.	WISA	2006	DBLP DOI BibTeX RDF	electronic seal, RFID, AES, message authentication code, pseudorandom function
1	Jeremy R. Johnson, Werner Krandick, Anatole D. Ruslanov	Architecture-aware classical Taylor shift by 1.	ISSAC	2005	DBLP DOI BibTeX RDF	ILP scheduling, Taylor shift, delayed carry propagation, multiprecision arithmetic, register tiling, high-performance computing, code generation, memory hierarchy, polynomials, performance tuning, loop unrolling
1	Kamen Yotov, Keshav Pingali, Paul Stodghill	Think globally, search locally.	ICS	2005	DBLP DOI BibTeX RDF
1	N. Emad, O. Hamdi-Larbi, Z. Mahjoub	On sparse matrix-vector product optimization.	AICCSA	2005	DBLP DOI BibTeX RDF
1	Mark Stephenson, Saman P. Amarasinghe	Predicting Unroll Factors Using Supervised Classification.	CGO	2005	DBLP DOI BibTeX RDF
1	Woongki Baek, Jihong Kim	Load-store reordering for low-power multimedia data transfers.	ISCAS	2005	DBLP DOI BibTeX RDF
1	J. Lahti, Jari K. Juntunen, Olli Lehtoranta, Timo D. Hämäläinen	Algorithmic optimization of H.264/AVC encoder.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Chia-Hsien Liu, Tay-Jyi Lin, Chie-Min Chao, Pi-Chen Hsiao, Li-Chun Lin, Shin-Kai Chen, Chao-Wei Huang, Chih-Wei Liu, Chein-Wei Jen	Hierarchical instruction encoding for VLIW digital signal processors.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Jongmyon Kim, D. Scott Wills, Linda M. Wills	Architectural Enhancements for Color Image and Video Processing on Embedded Systems.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
1	Canqun Yang, Xuejun Yang, Jingling Xue	Improving the Performance of GCC by Exploiting IA-64 Architectural Features.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
1	Ken Naono, Toshiyuki Imamura	An Evaluation Towards Automatically Tuned Eigensolvers.	LSSC	2005	DBLP DOI BibTeX RDF
1	Yanwei Niu, Ziang Hu, Kenneth E. Barner, Guang R. Gao	Performance Modelling and Optimization of Memory Access on Cellular Computer Architecture Cyclops64.	NPC	2005	DBLP DOI BibTeX RDF
1	Gregorio Bernabé, José M. García, José González	Reducing 3D Fast Wavelet Transform Execution Time Using Blocking and the Streaming SIMD Extensions.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	Streaming SIMD extensions, reuse, vectorization, video compression, blocking, 3D wavelet transform
1	Yunyang Dai, Qing Li, Qi Zhang, C. C. Jay Kuo	SIMD - efficient loop unrolling design for embedded multimedia applications.	ICME	2004	DBLP BibTeX RDF
1	Takahiro Katagiri, Kenji Kise, Hiroki Honda, Toshitsugu Yuba	Effect of auto-tuning with user's knowledge for numerical software.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	eigensolver, performance modeling, parameter optimization, auto-tuning, numerical library
1	Zhao-Hui Du, Chu-Cheow Lim, Xiao-Feng Li, Chen Yang, Qingyu Zhao, Tin-Fook Ngai	A cost-driven compilation framework for speculative parallelization of sequential programs.	PLDI	2004	DBLP DOI BibTeX RDF	cost-driven compilation, speculative parallel threading, loop transformation, thread-level speculation, speculative multithreading, speculative parallelization
1	Sumit Gupta, Rajesh K. Gupta, Nikil D. Dutt, Alexandru Nicolau	Coordinated parallelizing compiler optimizations and high-level synthesis.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	dynamic CSE, parallelizing transformations, presynthesis, embedded systems, high-level synthesis, Code motions, common subexpression elimination
1	Surendra Byna, Xian-He Sun, William Gropp, Rajeev Thakur	Predicting memory-access cost based on data-access patterns.	CLUSTER	2004	DBLP DOI BibTeX RDF
1	Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alexandru Nicolau	Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow.	DATE	2004	DBLP DOI BibTeX RDF
1	Huibin Shi, Chris Bailey	Investigating Available Instruction Level Parallelism for Stack Based Machine Architectures.	DSD	2004	DBLP DOI BibTeX RDF
1	Alireza Hodjat, Ingrid Verbauwhede	A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA.	FCCM	2004	DBLP DOI BibTeX RDF
1	David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee	Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF
1	Yosi Ben-Asher, Daniel Citron, Gadi Haber	Overlapping Memory Operations with Circuit Evaluation in Reconfigurable Computing.	IPDPS	2004	DBLP DOI BibTeX RDF
1	Michael Wolfe	Supercompilers, the AMD Opteron, and Your Cell Phone.	IPDPS	2004	DBLP DOI BibTeX RDF
1	Alireza Hodjat, Ingrid Verbauwhede	Minimum Area Cost for a 30 to 70 Gbits/s AES Processor.	ISVLSI	2004	DBLP DOI BibTeX RDF
1	Sumio Morioka, Akashi Satoh	A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Peter Sanders, Sebastian Winkel	Super Scalar Sample Sort.	ESA	2004	DBLP DOI BibTeX RDF
1	Qingda Lu, Xiaoyang Gao, Sriram Krishnamoorthy, Gerald Baumgartner, J. Ramanujam, P. Sadayappan	Empirical Performance-Model Driven Data Layout Optimization.	LCPC	2004	DBLP DOI BibTeX RDF
1	Litong Song, Yuhua Zhang, Krishna M. Kavi	Loop Transformation Techniques To Aid In Loop Unrolling and Multithreading.	ISCA PDCS	2003	DBLP BibTeX RDF
1	Jeyarajan Thiyagalingam, Olav Beckmann, Paul H. J. Kelly	Improving the Performance of Morton Layout by Array Alignment and Loop Unrolling: Reducing the Price of Naivety.	LCPC	2003	DBLP DOI BibTeX RDF
1	Mikio Takeuchi, Hideaki Komatsu, Toshio Nakatani	A new speculation technique to optimize floating-point performance while preserving bit-by-bit reproducibility.	ICS	2003	DBLP DOI BibTeX RDF	bit-by-bit reproducibility, floating-point speculation, fused multiply-add, reassociation, striding, Java, prefetching, accuracy, instruction-level parallelism, software pipelining, just-in-time compiler, loop unrolling, privatization, IA-64, IEEE 754
1	Roni Rosner, Micha Moffie, Yiannakis Sazeides, Ronny Ronen	Selecting long atomic traces for high coverage.	ICS	2003	DBLP DOI BibTeX RDF	trace atomicity, trace processors, trace selection, trace cache
1	Min Zhao, Bruce R. Childers, Mary Lou Soffa	Predicting the impact of optimizations for embedded systems.	LCTES	2003	DBLP DOI BibTeX RDF	code models, embedded systems, prediction, optimizing compilers, loop optimizations, resource models, optimization models
1	John S. Seng, Dean M. Tullsen	The Effect of Compiler Optimizations on Pentium 4 Power Consumption.	Interaction between Compilers and Computer Architectures	2003	DBLP DOI BibTeX RDF
1	Gregorio Bernabé, José M. García, José González	Reducing 3D Wavelet Transform Execution Time through the Streaming SIMD Extensions.	PDP	2003	DBLP DOI BibTeX RDF
1	Jirong Liao, Weng-Fai Wong, Tulika Mitra	A Model for Hardware Realization of Kernel Loops.	FPL	2003	DBLP DOI BibTeX RDF
1	Takahiro Katagiri, Kenji Kise, Hiroaki Honda, Toshitsugu Yuba	FIBER: A Generalized Framework for Auto-tuning Software.	ISHPC	2003	DBLP DOI BibTeX RDF	Numerical library Eigensolver, Eigensolver, Performance modeling, Parameter optimization, Auto-Tuning