Search results for "low power"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Ajith Amerasekera	Ultra low power electronics in the next decade.	ISLPED	2010	DBLP DOI BibTeX RDF	low-power electronics, power management
4	Dimin Niu, Yiran Chen, Yuan Xie	Low-power dual-element memristor based memory design.	ISLPED	2010	DBLP DOI BibTeX RDF	memristor, low power, nonvolatile memory
4	Himanshu Markandeya, Georgios Karakonstantis, Shriram Raghunathan, Pedro Irazoqui, Kaushik Roy	Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection.	ISLPED	2010	DBLP DOI BibTeX RDF	low power, epilepsy, biomedical, seizure detection
4	Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy	Analysis and design of ultra low power thermoelectric energy harvesting systems.	ISLPED	2010	DBLP DOI BibTeX RDF	thermoelectric energy harvesting, ultra low power
4	Sudhanshu Khanna, Benton H. Calhoun	Serial sub-threshold circuits for ultra-low-power systems.	ISLPED	2009	DBLP DOI BibTeX RDF	bit width, serial systems, leakage, ultra low power, sub-threshold
4	Shu-Yi Wong, Chunhong Chen, Q. M. Jonathan Wu	Power-management-based Chien search for low power BCH decoder.	ISLPED	2009	DBLP DOI BibTeX RDF	BCH decoder, Chien search, low power, power management
4	Hussain Alzaher, Noman Tasadduq	A CMOS low power current-mode polyphase filter.	ISLPED	2009	DBLP DOI BibTeX RDF	CMOS analog integrated circuits, low power current mode circuit, polyphase filter
4	Flavio Carbognani, Luca Henzen	Cross-over current suppressing latch compared to state-of-the-art for low-power low-frequency applications with resonant clocking.	ISLPED	2009	DBLP DOI BibTeX RDF	flipflops, low power design, clock, digital circuits, adiabatic
4	Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, Dennis Sylvester, David Blaauw	Low power circuit design based on heterojunction tunneling transistors (HETTs).	ISLPED	2009	DBLP DOI BibTeX RDF	SRAM design, low power applications, tunneling transistor
4	Chenjie Yu, Xiangrong Zhou, Peter Petrov	Low-power inter-core communication through cache partitioning in embedded multiprocessors.	SBCCI	2009	DBLP DOI BibTeX RDF	low-power cache architectures, low-power cache coherence, MPSoC, on-chip communication
4	Soheil Modirzadeh, Brian Fuller, Sandeep Mirchandani, Jon McDonald, Ran Avinun, Camille Kokozaki	It is all about power analysis, exploration and trade-offs.	ISLPED	2009	DBLP DOI BibTeX RDF	IDT, NXP, broadcom, cadence, system design and verification, technical panel, low power, low power design
4	Ke Xu, Chiu-sing Choy	Low-power H.264/AVC baseline decoder for portable applications.	ISLPED	2007	DBLP DOI BibTeX RDF	low-power, decoder, H.264/AVC
4	Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, Jongcheol Jeong, Euljoo Jeong, Suk Joong Lee, Hoi-Jun Yoo	A low power multimedia SoC with fully programmable 3D graphics and MPEG4/H.264/JPEG for mobile devices.	ISLPED	2007	DBLP DOI BibTeX RDF	mobile multimedia SoC, programmable 3D graphics, low power design
4	Nilanjan Banerjee, Jung Hwan Choi, Kaushik Roy	A process variation aware low power synthesis methodology for fixed-point FIR filters.	ISLPED	2007	DBLP DOI BibTeX RDF	fixed-point FIR filters, variation aware, low-power, synthesis
4	Keejong Kim, Hamid Mahmoodi, Kaushik Roy	A low-power SRAM using bit-line charge-recycling technique.	ISLPED	2007	DBLP DOI BibTeX RDF	write margin, write power, low power, process variation, SRAM, charge-recycling
4	Ja Chun Ku, Yehea I. Ismail	Thermal-aware methodology for repeater insertion in low-power VLSI circuits.	ISLPED	2007	DBLP DOI BibTeX RDF	low-power design, repeater insertion, temperature-aware design
4	Zhenhua Wang	Adaptive analog biasing: a robustness-enhanced low-power technique for analog baseband design.	ISLPED	2007	DBLP DOI BibTeX RDF	robustness enhancement, sensitivity reduction, low-power, low-energy, analog integrated circuits, biasing
4	Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy	Low-power process-variation tolerant arithmetic units using input-based elastic clocking.	ISLPED	2007	DBLP DOI BibTeX RDF	elastic clocking, process tolerant, low power
4	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A Gated Clock Scheme for Low Power Testing of Logic Cores.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	test-per-scan, test-per-clock, low power design, low power test
4	Amin Shameli, Payam Heydari	A novel power optimization technique for ultra-low power RFICs.	ISLPED	2006	DBLP DOI BibTeX RDF	radio-frequency integrated circuit, CMOS, ultra-low power, low-noise amplifier
4	Stephan Henzler, Siegmar Koeppe	High-speed low-power frequency divider with intrinsic phase rotator.	ISLPED	2006	DBLP DOI BibTeX RDF	phase-rotator, pre-scaler, low-power, divider
4	Mohammad Sharifkhani, Manoj Sachdev	A low power SRAM architecture based on segmented virtual grounding.	ISLPED	2006	DBLP DOI BibTeX RDF	static-random access memory, write power reduction, low-power, SRAM, leakage reduction
4	Jie Jin, Chi-Ying Tsui	A low power Viterbi decoder implementation using scarce state transition and path pruning scheme for high throughput wireless applications.	ISLPED	2006	DBLP DOI BibTeX RDF	low power, convolutional code, Viterbi algorithm
4	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Low-power fanout optimization using MTCMOS and multi-Vt techniques.	ISLPED	2006	DBLP DOI BibTeX RDF	buffer chain, fanout tree, low-power design, fanout optimization
4	Jianwei Zhang, Yizheng Ye, Bin-Da Liu	A new mismatch-dependent low power technique with shadow match-line voltage-detecting scheme for CAMs.	ISLPED	2006	DBLP DOI BibTeX RDF	mismatch-dependent, voltage detecting, low power, high speed, CAM
4	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Low-power fanout optimization using multiple threshold voltage inverters.	ISLPED	2005	DBLP DOI BibTeX RDF	buffer chain, fanout tree, low-power design, fanout optimization
4	Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh	Cascaded carry-select adder (C2SA): a new structure for low-power CSA design.	ISLPED	2005	DBLP DOI BibTeX RDF	low-power, carry-select adder
4	Srinivasa R. Sridhara, Naresh R. Shanbhag	A low-power bus design using joint repeater insertion and coding.	ISLPED	2005	DBLP DOI BibTeX RDF	low-power, coding, crosstalk, repeaters
4	Jinn-Shyan Wang, Chien-Nan Kuo, Tsung-Han Yang	Low-power fixed-width array multipliers.	ISLPED	2004	DBLP DOI BibTeX RDF	fixed-width multiplier, left-to-right multiplier, reduced-width multiplier, low power
4	Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy	Low-power carry-select adder using adaptive supply voltage based on input vector patterns.	ISLPED	2004	DBLP DOI BibTeX RDF	adaptive supply voltage, low power adder, carry-select adder
4	Maged Ghoneima, Yehea I. Ismail	Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses.	ISLPED	2004	DBLP DOI BibTeX RDF	low power, interconnects, buses, coupling capacitance
4	Yijun Liu, Stephen B. Furber	The design of a low power asynchronous multiplier.	ISLPED	2004	DBLP DOI BibTeX RDF	Booth's algorithm, low power, benchmark, multiplier, asynchronous logic
4	Stefano Gregori, Yunlei Li, Huijuan Li, Jin Liu, Franco Maloberti	2.45 GHz power and data transmission for a low-power autonomous sensors platform.	ISLPED	2004	DBLP DOI BibTeX RDF	RF to DC power conversion, low power clock and data recovery, microwave power transmission, wireless sensor
4	Bipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy	Device optimization for ultra-low power digital sub-threshold operation.	ISLPED	2004	DBLP DOI BibTeX RDF	device optimization, sub-threshold operation, ultra-low power applications
4	Ming-Feng Huang, Shuenn-Yuh Lee, Chung J. Kuo	A CMOS even harmonic mixer with current reuse for low power applications.	ISLPED	2004	DBLP DOI BibTeX RDF	current reuse, low power, mixer
4	Deming Chen, Jason Cong	Delay optimal low-power circuit clustering for FPGAs with dual supply voltages.	ISLPED	2004	DBLP DOI BibTeX RDF	circuit clustering, low-power FPGA, dual supply voltage
4	Tsugio Makimoto, Yoshio Sakai	Evolution of low power electronics and its future applications.	ISLPED	2003	DBLP DOI BibTeX RDF	Nomadic Age, low power technologies, robotics, applications
4	Azadeh Davoodi, Ankur Srivastava	Effective graph theoretic techniques for the generalized low power binding problem.	ISLPED	2003	DBLP DOI BibTeX RDF	low-power binding, graph theory, high level synthesis
4	Kyu-won Choi, Abhijit Chatterjee	UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI.	ISLPED	2003	DBLP DOI BibTeX RDF	device and interconnect co-optimization, nanometer design, time slack distribution, low-power design
4	Qadeer Ahmad Khan, Sanjay Kumar Wadhwa, Kulbhushan Misri	Low power startup circuits for voltage and current reference with zero steady state current.	ISLPED	2003	DBLP DOI BibTeX RDF	low power integrated circuits, startup circuit, voltage reference, current reference
4	Hesam Amir Aslanzadeh, Saeid Mehrmanesh, Mohammad B. Vahidfar, Amin Quasem Safarian, Reza Lotfi	A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using "Slew Boost" technique.	ISLPED	2003	DBLP DOI BibTeX RDF	CMOS analog circuit, Slew Boost technique, class AB, low power, high speed, operational amplifier, pipelined analog to digital converter, ultra low voltage
4	Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer	A low-power VLSI architecture for turbo decoding.	ISLPED	2003	DBLP DOI BibTeX RDF	MAP decoder, low power architecture, turbo decoding
4	Sung-Mo Kang	Elements of low power design for integrated systems.	ISLPED	2003	DBLP DOI BibTeX RDF	low power integrated circuits, VLSI, CMOS
4	Woo Young Choi, Jong Duk Lee, Byung-Gook Park	Reverse-order source/drain formation with double offset spacer (RODOS) for CMOS low-power, high-speed and low-noise amplifiers.	ISLPED	2003	DBLP DOI BibTeX RDF	RODOS, offset spacer, reverse-order, low-power, high-speed, low-noise, amplifier
4	Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy	High performance and low power FIR filter design based on sharing multiplication.	ISLPED	2002	DBLP DOI BibTeX RDF	FIR filter design, computation sharing, conditional capture flip-flop, high performance and low power carry select adder
4	Victor V. Zyuban, Stephen V. Kosonocky	Low power integrated scan-retention mechanism.	ISLPED	2002	DBLP DOI BibTeX RDF	balloon latch, data retention, low power, scan, leakage, latch, MTCMOS, subthreshold
4	Aristides Efthymiou, Jim D. Garside	An adaptive serial-parallel CAM architecture for low-power cache blocks.	ISLPED	2002	DBLP DOI BibTeX RDF	VLSI, low power, asynchronous circuits, low energy, CAM, cache design
4	Kyu-won Choi, Abhijit Chatterjee	HA2TSD: hierarchical time slack distribution for ultra-low power CMOS VLSI.	ISLPED	2002	DBLP DOI BibTeX RDF	gate-level power optimization, time slack distribution, low-power design
4	Carl De Ranter, Michiel Steyaert	Design techniques for low power high bandwidth upconversion in CMOS.	ISLPED	2002	DBLP DOI BibTeX RDF	upconversion, low power, CMOS, analog, oscillators, RF design
4	Magnus Ekman, Per Stenström, Fredrik Dahlgren	TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors.	ISLPED	2002	DBLP DOI BibTeX RDF	virtual caches, low-power, CMP, snoop
4	Chunhong Chen, Changjun Kang, Majid Sarrafzadeh	Activity-sensitive clock tree construction for low power.	ISLPED	2002	DBLP DOI BibTeX RDF	low power, clock gating, clock tree, activity pattern
4	Yu-Lung Hsu, Sying-Jyan Wang	Retiming-based logic synthesis for low-power.	ISLPED	2002	DBLP DOI BibTeX RDF	switching actvity, low-power, logic design, retiming
4	David Garrett, Chris Nicol, Andrew J. Blanksby, Chris Howland	A low power normalized-LMS decision feedback equalizer for a wireless packet modem.	ISLPED	2002	DBLP DOI BibTeX RDF	NLMS, low power, equalization, early termination
4	Gurhan Kucuk, Kanad Ghose, Dmitry Ponomarev, Peter M. Kogge	Energy: efficient instruction dispatch buffer design for superscalar processors.	ISLPED	2001	DBLP DOI BibTeX RDF	bitline segmentation, low power comparator, low power instruction scheduling, low-power superscalar datapath
4	Alain-Serge Porret, Thierry Melly, Eric A. Vittoz, Christian C. Enz	Tradeoffs and design of an ultra low power UHF transceiver integrated in a standard digital CMOS process.	ISLPED	2000	DBLP DOI BibTeX RDF	low-power, CMOS, low-voltage, RF, transceiver
4	Antonio G. M. Strollo, Ettore Napoli, Davide De Caro	New clock-gating techniques for low-power flip-flops.	ISLPED	2000	DBLP DOI BibTeX RDF	flip-fops, CMOS digital integrated circuits, transition probability, low-power circuits
4	Khalil Najafi	Low-power micromachined microsystems (invited talk).	ISLPED	2000	DBLP DOI BibTeX RDF	micromachining, power sources, low-power, MEMS, energy harvesting, microsystems
4	Jae-Hee Won, Kiyoung Choi	Low power self-timed Radix-2 division (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF	RSD, radix-2 division, low power, self-timed
4	Andrea Pallotta, Francesco Centurelli, Alessandro Trifiletti	A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers.	ISLPED	2000	DBLP DOI BibTeX RDF	SDH, clock recovery, low power, optical communications
4	Vamsi K. Srikantam, N. Ranganathan, Srikanth Srinivasan	CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis.	VLSI Design	2000	DBLP DOI BibTeX RDF	Register and Module Assignment Design for low power, High level synthesis, Low power design, Floorplanning
4	Xiaodong Zhang, Kaushik Roy	Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction. (PDF / PS)	DFT	1999	DBLP DOI BibTeX RDF	BIST Synthesis, Weighted Random Pattern Generator, Low Power BIST, Testing, Low Power, Cellular Automata, Peak Power
4	Christian Piguet, T. Schneider, Jean-Marc Masgonty, Claude Arm, Serge Durand, M. Stegers	Low-Power Embedded Microprocessor Design.	EUROMICRO	1996	DBLP DOI BibTeX RDF	low-power embedded microprocessor design, low-power RISC-like architectures, gated clock techniques, power savings, microprocessor chips, CMOS technology, hierarchical memories, clock cycles
4	Joep L. W. Kessels	VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player.	ASYNC	1995	DBLP DOI BibTeX RDF	digital audio tape, VLSI programming, low-power asynchronous Reed-Solomon decoder, DCC player, Tangram, minimal power dissipation, low-power cost-effective design, VLSI, logic programming, power consumption, power consumption, asynchronous circuits, asynchronous circuit, decoding, Reed-Solomon codes
4	Enric Musoll, Jordi Cortadella	Scheduling and resource binding for low power.	ISSS	1995	DBLP DOI BibTeX RDF	data-path power budget, low-power data-paths, scheduling, low power, high level synthesis, high-level synthesis, power consumption, adders, multipliers, logic circuits, data flow graphs, trading off, network synthesis, functional units, resource binding, resource-binding
4	Chuan-Yu Wang, Kaushik Roy	Control unit synthesis targeting low-power processors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	control unit synthesis, low-power processors, low-power decoding scheme, microprogrammed architecture, nanoprogrammed architecture, 8086 instruction set, instruction opcodes, computer architecture, logic design, encoding, decoding, microprocessor chips, graph embedding, instruction sets, microprogramming, CMOS circuits, logic minimization, system reliability, switching activity, minimisation of switching nets, pseudo-Boolean programming
4	Andrew Wolfe	A case study in low-power system-level design. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	low-power system-level design, touchscreen interface device, RS232 communication lines, design automation community, real-time systems, logic design, systems analysis, personal computer, low-power embedded system
3	Leila Koushaeian, Stan Skafidas	A 65nm CMOS low-power, low-voltage bandgapreference with using self-biased composite cascode opamp.	ISLPED	2010	DBLP DOI BibTeX RDF	bandgap voltage reference, self-biased, self-cascode, temperature coefficient, voltage reference
3	Martin Saint-Laurent, Animesh Datta	A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology.	ISLPED	2010	DBLP DOI BibTeX RDF	clock gater, clock gating cell, local clock buffer, set-reset latch
3	Lang Lin, Daniel E. Holcomb, Dilip Kumar Krishnappa, Prasad Shabadi, Wayne Burleson	Low-power sub-threshold design of secure physical unclonable functions.	ISLPED	2010	DBLP DOI BibTeX RDF	embedded system security, sub-threshold circuits, RFID, physical unclonable function
3	Saurabh Sinha, Jounghyuk Suh, Bertan Bakkaloglu, Yu Cao	Workload-aware neuromorphic design of low-power supply voltage controller.	ISLPED	2010	DBLP DOI BibTeX RDF	neuromorphic engineering, DVS, spiking neurons
3	Mingoo Seok, David Blaauw, Dennis Sylvester	Clock network design for ultra-low power applications.	ISLPED	2010	DBLP DOI BibTeX RDF	ultra-low power, robust design, clock network
3	Xuebei Yang, Jyotsna Chauhan, Jing Guo, Kartik Mohanram	Graphene tunneling FET and its applications in low-power circuit design.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	graphene nanoribbons, tunneling fets, low-power
3	Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas	A low power, variable resolution two-step flash ADC.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	two-step flash ADC, variable resolution, low power
3	Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys	A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking.	DAC	2010	DBLP DOI BibTeX RDF	WSN node, hardware specialization, microcoded architecture, low-power design
3	Shinobu Fujita, Shinichi Yasuda, Dae Sung Lee, Xiangyu Chen, Deji Akinwande, H.-S. Philip Wong	Detachable nano-carbon chip with ultra low power.	DAC	2010	DBLP DOI BibTeX RDF	NEMS, ultra-low power, 3D-IC
3	Nagaraj Ns, John Byler, Koorosh Nazifi, Venugopal Puvvada, Toshiyuki Saito, Alan Gibbons, S. Balajee	What's cool for the future of ultra low power designs?	DAC	2010	DBLP DOI BibTeX RDF	system level power, low power, system design
3	Nicolas Tsiftes, Joakim Eriksson, Niclas Finne, Fredrik Österlind, Joel Höglund, Adam Dunkels	A framework for low-power IPv6 routing simulation, experimentation, and evaluation.	SIGCOMM	2010	DBLP DOI BibTeX RDF	RPL, routing, low-power, wireless, IPv6
3	Ashutosh Chakraborty, David Z. Pan	PASAP: power aware structured ASIC placement.	ISLPED	2010	DBLP DOI BibTeX RDF	structured ASICS, low power, placement, regular fabrics
3	Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini	Automatic synthesis of near-threshold circuits with fine-grained performance tunability.	ISLPED	2010	DBLP DOI BibTeX RDF	near threshold, sub-threshold performance, variability compensation, low power, ultra low power, dual VDD, sub-threshold
3	Prateek Mishra, Anish Muttreja, Niraj K. Jha	Low-power FinFET circuit synthesis using multiple supply and threshold voltages.	JETC	2009	DBLP DOI BibTeX RDF	Low-power, linear programming, synthesis, TCMS
3	Chua-Chin Wang, Gang-Neng Sung	Low-Power Multiplier Design Using a Bypassing Technique.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Low power multiplier, Timing control, Partial product, Bypassing
3	Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi	Sign Bit Reduction Encoding For Low Power Applications.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Low power multiplier, Signed multiplier, Sign extension, FIR filter, Power reduction, Energy reduction, Bus encoding
3	Choong Jin Hyun, Myung Hoon Sunwoo	Low Power Complexity-Reduced ME and Interpolation Algorithms for H.264/AVC.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Motion estimation, Low power design, H.264/AVC, Motion compensation, Data reuse
3	Veera Papirla, Aarul Jain, Chaitali Chakrabarti	Low power robust signal processing.	ISLPED	2009	DBLP DOI BibTeX RDF	algorithmic noise tolerance, redundant binary arithmetic, soft DSP
3	Noriko Takagi, Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura	Cooperative shared resource access control for low-power chip multiprocessors.	ISLPED	2009	DBLP DOI BibTeX RDF	low power, chip multiprocessors, cache partitioning, dvfs, resource conflict
3	Zheng Li, Jie Wu, Li Shang, Alan Rolf Mickelson, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, Yihe Sun	A high-performance low-power nanophotonic on-chip network.	ISLPED	2009	DBLP DOI BibTeX RDF	networks-on-chip, optical communication, silicon photonics
3	Matthew M. Ziegler, Victor V. Zyuban, George Gristede, Milena Vratonjic, Joshua Friedrich	The opportunity cost of low power design: a case study in circuit tuning.	ISLPED	2009	DBLP DOI BibTeX RDF	low power design, productivity, circuit tuning
3	Jason Cong, Bin Liu 0006, Zhiru Zhang	Behavior-level observability don't-cares and application to low-power behavioral synthesis.	ISLPED	2009	DBLP DOI BibTeX RDF	low power, observability, behavioral synthesis
3	Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi	Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories.	ISLPED	2009	DBLP DOI BibTeX RDF	boost converter, inductor design, SSD, charge pump
3	Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Gilles Sicard	A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications.	ISLPED	2009	DBLP DOI BibTeX RDF	bose choudhury hocquenghem, design, low power, methodology, logic, energy, cmos, library, circuit, subthreshold, ultra low voltage
3	Mojy Chian	Challenges and opportunities in low-power design enablement.	ISLPED	2009	DBLP DOI BibTeX RDF	keynote
3	M. A. Ochoa-Montiel, Bashir M. Al-Hashimi, Peter Kollig	Design of a low power MPEG-1 motion vector reconstructor.	SBCCI	2009	DBLP DOI BibTeX RDF	behavioural synthesis, low power
3	Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas	Design of novel CAM core cell structures for an efficient implementation of low power BCAM system.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	binary content addressable memory (bcam), core cell, match line scheme, low power
3	Colin J. Ihrig, Gerold Joseph Dhanabalan, Alex K. Jones	A low-power CMOS thyristor based delay element with programmability extensions.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	delay element, thyristor, low power
3	Maria Gorlatova, Peter R. Kinget, Ioannis Kymissis, Dan Rubenstein, Xiaodong Wang, Gil Zussman	Challenge: ultra-low-power energy-harvesting active networked tags (EnHANTs).	MOBICOM	2009	DBLP DOI BibTeX RDF	energy efficient networking, energy scavenging, ultra-low power communications, UWB, ultra-wideband, energy harvesting
3	Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, David Z. Pan	O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration.	DAC	2009	DBLP DOI BibTeX RDF	low power nanophotonic integration, optical routing, integer linear programming
3	Han-Jong Ryu, Seung-Min Lee, Jun-Soo Jeon, Sang-Chul Shin	Implementation of the low power performance analysis system for WSN.	SenSys	2009	DBLP DOI BibTeX RDF	low power performance, power analysis
3	Barbara Staehle	Optimizing the Association Procedure for Low-Power 802.15.4 Nonbeacon Sensor Networks.	Networking	2009	DBLP DOI BibTeX RDF	Nonbeacon 802.15.4, Wireless Sensor Networks, Low-Power
3	Xin He, Jorgen Peddersen, Sri Parameswaran	LOP: a novel SRAM-based architecture for low power and high throughput packet classification.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	low-power, packet classification, hardware design
3	Se Hun Kim, Saibal Mukhopadhyay, Wayne Wolf	Experimental analysis of sequence dependence on energy saving for error tolerant image processing.	ISLPED	2009	DBLP DOI BibTeX RDF	voltage over-scaling, low power, DCT