Search results for "low power SRAM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Keejong Kim, Hamid Mahmoodi, Kaushik Roy	A low-power SRAM using bit-line charge-recycling technique.	ISLPED	2007	DBLP DOI BibTeX RDF	write margin, write power, low power, process variation, SRAM, charge-recycling
2	Ramy E. Aly, Mohamed A. Elgamel, Magdy A. Bayoumi	Dual sense amplified bit lines (DSABL) architecture for low-power SRAM design.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Koji Nii, Hiroshi Makino, Yoshiki Tujihashi, Chikayoshi Morishima, Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori Hamano	A low power SRAM using auto-backgate-controlled MT-CMOS.	ISLPED	1998	DBLP DOI BibTeX RDF
1	Balwinder Raj, Jatin Mitra, Deepak Kumar Bihani, V. Rangharajan, A. K. Saxena, S. Dasgupta	Process Variation Tolerant FinFET Based Robust Low Power SRAM Cell Design at 32 nm Technology.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo, Jeremy Yung Shern Low	Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Luca Sterpone, Luigi Carro, Debora Matos, Stephan Wong, F. Fakhar	A new reconfigurable clock-gating technique for low power SRAM-based FPGAs.	DATE	2011	DBLP DOI BibTeX RDF
1	Byung-Do Yang	A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations.	J. Solid-State Circuits	2010	DBLP DOI BibTeX RDF
1	Minki Cho, Jason Schlessman, Hamid Mahmoodi, Marilyn Wolf, Saibal Mukhopadhyay	Postsilicon Adaptation for Low-Power SRAM under Process Variation.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF
1	José G. Delgado-Frias, Zhe Zhang, Michael A. Turi	Low power SRAM cell design for FinFET and CNTFET technologies.	Green Computing Conference	2010	DBLP DOI BibTeX RDF
1	Sheng Wu, Xiang Zheng, Zhiqiang Gao, Xiangqing He	A 65nm embedded low power SRAM compiler.	DDECS	2010	DBLP DOI BibTeX RDF
1	G. Razavipour, Ali Afzali-Kusha, Massoud Pedram	Design and Analysis of Two Low-Power SRAM Cell Structures.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Shigenobu Komatsu, Masanao Yamaoka, Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada	A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation.	CICC	2009	DBLP DOI BibTeX RDF
1	Minki Cho, Jason Schlessman, Wayne Wolf, Saibal Mukhopadhyay	Accuracy-aware SRAM: a reconfigurable low power SRAM architecture for mobile multimedia applications.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy	A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors.	DAC	2009	DBLP DOI BibTeX RDF	low power SRAM, supply voltage over-scaling, graceful degradation
1	Deblina Sarkar, Deepanjan Datta, Sudeb Dasgupta	Modeling of Leakage Current Mechanisms in Nanoscale DG MOSFET and its Application to Low Power SRAM Design.	JCP	2008	DBLP DOI BibTeX RDF
1	Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, Takashi Ipposhi	Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation.	JCP	2008	DBLP DOI BibTeX RDF
1	Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim	Circuit techniques for ultra-low power subthreshold SRAMs.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Farshad Moradi, Dag T. Wisland, Snorre Aunet, Hamid Mahmoodi, Tuan Vu Cao	65NM sub-threshold 11T-SRAM for ultra low voltage applications.	SoCC	2008	DBLP DOI BibTeX RDF
1	Hao-I Yang, Ssu-Yun Lai, Wei Hwang	Low-power floating bitline 8-T SRAM design with write assistant circuits.	SoCC	2008	DBLP DOI BibTeX RDF
1	Helmut Puchner	NBTI product level reliability for a low-power SRAM technology.	Microelectronics Reliability	2007	DBLP DOI BibTeX RDF
1	Deblina Sarkar, Samiran Ganguly, Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta	Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy	A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM.	ISLPED	2007	DBLP DOI BibTeX RDF	low power SRAM, low voltage SRAM, schmitt trigger, subthreshold SRAM, process variations
1	Tamer Cakici, Keejong Kim, Kaushik Roy	FinFET Based SRAM Design for Low Standby Power Applications.	ISQED	2007	DBLP DOI BibTeX RDF
1	Mohammad Sharifkhani, Manoj Sachdev	A low power SRAM architecture based on segmented virtual grounding.	ISLPED	2006	DBLP DOI BibTeX RDF	static-random access memory, write power reduction, low-power, SRAM, leakage reduction
1	Qikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy	Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design.	DATE	2006	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, Kaushik Roy	Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM.	DAC	2006	DBLP DOI BibTeX RDF	adaptive source biasing, hold failures, low power SRAM
1	Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto	A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering.	ISLPED	2006	DBLP DOI BibTeX RDF	data-bit reordering, low power SRAM, two-port SRAM, real-time image processing, majority logic
1	Thomas Janik, Eric Liau, H. Lorenz, Manfred Menke, E. Plaettner, J. Schweden, H. Seitz, E. Vega-Ordonez	A 1.8V p(seudo)SRAM using standard 140nm DRAM technology with self adapting clocked standby operation.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Keejong Kim, Chris H. Kim, Kaushik Roy	TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique.	ISQED	2005	DBLP DOI BibTeX RDF
1	Rabiul Islam, Adam Brand, Dave Lippincott	Low power SRAM techniques for handheld products.	ISLPED	2005	DBLP DOI BibTeX RDF	back-bias, bitcell, memory, leakage
1	Ashis Maity, R. G. Raghavendra, Pradip Mandal	On-Chip Voltage Regulator with Improved Transient Response.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Stefan Cserveny, Jean-Marc Masgonty, Christian Piguet	Noise Margin in Low Power SRAM Cells.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Hwang-Cherng Chow, Shu-Hsien Chang	High performance sense amplifier circuit for low power SRAM applications.	ISCAS	2004	DBLP BibTeX RDF
1	Mario R. Casu, Philippe Flatresse	Converting an Embedded Low-Power SRAM from Bulk to PD-SOI.	MTDT	2002	DBLP DOI BibTeX RDF
1	M. Jagasivamani, Dong Sam Ha	Development of a low-power SRAM compiler.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Jeyran Hezavei, Narayanan Vijaykrishnan, Mary Jane Irwin	A comparative study of power efficient SRAM designs.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF	low power, decoder, SRAM
1	Martin Margala	Low-Power SRAM Circuit Design.	MTDT	1999	DBLP DOI BibTeX RDF	design, VLSI, low-power, SRAM, low-voltage