Search results for "low power applications"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Lu Chao, Chi-Ying Tsui, Wing-Hung Ki	Vibration energy scavenging and management for ultra low power applications.	ISLPED	2007	DBLP DOI BibTeX RDF	batteryless, energy scavenging and management, MPPT
2	Karim Abdelhalim, Leonard MacEachern, Samy A. Mahmoud	A nanowatt ADC for ultra low power applications.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Didier Van Reeth, Georges G. E. Gielen	A CAD Platform for Sensor Interfaces in Low-Power Applications.	PATMOS	2005	DBLP DOI BibTeX RDF
2	Jung Hyun Choi	Minimization of parasitic effects on the design of an accurate 2-MHz RC oscillator for low voltage and low power applications.	SBCCI	2005	DBLP DOI BibTeX RDF	2MHz RC circuit, parasitic effects, design, minimization, oscillator
2	Alexander Fish, Shy Hamami, Orly Yadid-Pecht	Self-powered active pixel sensors for ultra low-power applications.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Ad M. G. Peeters, Kees van Berkel	Single-rail handshake circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	single-rail handshake circuits, four-phase handshake protocol, standard-cell library, technology migration, low-power applications, VLSI, protocols, energy-efficient, asynchronous circuits, asynchronous circuits, integrated logic circuits, cellular arrays
1	Rohit Dhiman, Rajeevan Chandel	Sub-Threshold Delay and Power Analysis of Complementary Metal-Oxide Semiconductor Buffer Driven Interconnect Load for Ultra Low Power Applications.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Qing Dong, Bo Yang, Gong Chen, Jing Li, Shigetoshi Nakatake	Transistor channel decomposition for structured analog layout, manufacturability and low-power applications.	ISQED	2012	DBLP DOI BibTeX RDF
1	Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly	Vertical Slit Field Effect Transistor in ultra-low power applications.	ISQED	2012	DBLP DOI BibTeX RDF
1	Oliver Stecklina, Dieter Genschow, Christian Goltz	TandemStack - A Flexible and Customizable Sensor Node Platform for Low Power Applications.	SENSORNETS	2012	DBLP BibTeX RDF
1	Subhra Dhar, Manisha Pattanaik, Poolla Rajaram	Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Tiempo Sas, Gilles Sicard	40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
1	Soo Youn Kim, Selin Baytok, Kaushik Roy	Scaled LTPS TFTs for low-cost low-power applications.	ISQED	2011	DBLP DOI BibTeX RDF
1	Khawla Alzoubi, Daniel G. Saab, Sijing Han, Massood Tabib-Azar	Complementary Nano-Electro-Mechanical Switch for ultra-low-power applications: Design and modeling.	ISQED	2011	DBLP DOI BibTeX RDF
1	Josef Bajer, Jiri Vavra, Dalibor Biolek, Karel Hajek	Low-distortion current-mode quadrature oscillator for low-voltage low-power applications with non-linear non-inertial automatic gain control.	ECCTD	2011	DBLP DOI BibTeX RDF
1	S. D. Pable, Mohd. Hasan	Performance analysis of FPGA interconnect fabric for ultra-low power applications.	ICCCS	2011	DBLP DOI BibTeX RDF
1	Pramod Kumar Meher, Yu Pan	MCM-based implementation of block FIR filters for high-speed and low-power applications.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
1	Davide Carli, Davide Brunelli, Luca Benini, Massimiliano Ruggeri	An effective multi-source energy harvester for low power applications.	DATE	2011	DBLP BibTeX RDF
1	Mohamed O. Shaker, Magdy A. Bayoumi	A clock gated flip-flop for low power applications in 90 nm CMOS.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija	Multiplier structures for low power applications in deep-CMOS.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Louis P. Alarcón, Tsung-Te Liu, Jan M. Rabaey	A low-leakage parallel CRC generator for ultra-low power applications.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Louis H. Jung, Torsten Lehmann, Gregg J. Suaning, Nigel H. Lovell	A semi-static threshold-triggered delay element for low power applications.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Ashutosh Nandi, Rajeevan Chandel	Design and Analysis of Sub-DT Sub-Domino Logic Circuits for Ultra Low Power Applications.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Katsumi Dosaka, Daisuke Ogawa, Takahito Kusumoto, Masayuki Miyama, Yoshio Matsuda	A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Manoj Kumar, Sandeep K. Arya, Sujata Pandey	Level Shifter Design for Low Power Applications	CoRR	2010	DBLP BibTeX RDF
1	Shiann-Rong Kuang, Jiun-Ping Wang, Hong-Yi Huang	Variable-Latency Floating-Point Multipliers for Low-Power Applications.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Yngvar Berg, Tuan Vu Cao	New SRAM design using body bias technique for ultra low power applications.	ISQED	2010	DBLP DOI BibTeX RDF
1	Khodor Ahmad Fawaz, Tughrul Arslan, Sami Khawam, Mark Muir, Ioannis Nousias, Iain Lindsay, Ahmet T. Erdogan	A dynamically reconfigurable asynchronous processor for low power applications.	DASIP	2010	DBLP DOI BibTeX RDF
1	Mingoo Seok, David Blaauw, Dennis Sylvester	Clock network design for ultra-low power applications.	ISLPED	2010	DBLP DOI BibTeX RDF	ultra-low power, robust design, clock network
1	Farshad Moradi, Charles Augustine, Ashish Goel, Georgios Karakonstantis, Tuan Vu Cao, Dag T. Wisland, Hamid Mahmoodi, Kaushik Roy	Data-dependant sense-amplifier flip-flop for low power applications.	CICC	2010	DBLP DOI BibTeX RDF
1	Ahmed H. M. Abolila, Hesham F. A. Hamed, El-Sayed A. M. Hasaneen	High performance wideband CMOS current conveyor for low voltage low power applications.	ISSPIT	2010	DBLP DOI BibTeX RDF
1	Sumanth Amarchinta, Dhireesha Kudithipudi	Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffers.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	charge-boosters, subthreshold design, biasing
1	Xuebei Yang, Jyotsna Chauhan, Jing Guo, Kartik Mohanram	Graphene tunneling FET and its applications in low-power circuit design.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	graphene nanoribbons, tunneling fets, low-power
1	J. Gubelmann, P. A. Dal Fabbro, Marc Pastre, Maher Kayal	High-efficiency dynamic supply CMOS audio power amplifier for low-power applications.	Microelectronics Journal	2009	DBLP DOI BibTeX RDF
1	Yingbo Hu, Runde Zhou	Low Clock-Swing TSPC Flip-Flops for Low-Power Applications.	Journal of Circuits, Systems, and Computers	2009	DBLP DOI BibTeX RDF
1	Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi	Sign Bit Reduction Encoding For Low Power Applications.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Low power multiplier, Signed multiplier, Sign extension, FIR filter, Power reduction, Energy reduction, Bus encoding
1	Maurice Keller, Andrew Byrne, William P. Marnane	Elliptic Curve Cryptography on FPGA for Low-Power Applications.	TRETS	2009	DBLP DOI BibTeX RDF	FPGA, low-power, Cryptography, elliptic curves
1	Maruthi Chandrasekhar Bh, Sudeb Dasgupta	A 1.2 volt, 90nm, 16-bit three way segmented digital to analog converter (DAC) for low power applications.	ISQED	2009	DBLP DOI BibTeX RDF
1	Sungmin Bae, Krishnan Ramakrishnan, Narayanan Vijaykrishnan	A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications.	ISVLSI	2009	DBLP DOI BibTeX RDF
1	Yusuf Leblebici	Subthreshold Circuit Design for Ultra-Low-Power Applications.	PATMOS	2009	DBLP DOI BibTeX RDF
1	Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Gilles Sicard	A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications.	ISLPED	2009	DBLP DOI BibTeX RDF	bose choudhury hocquenghem, design, low power, methodology, logic, energy, cmos, library, circuit, subthreshold, ultra low voltage
1	Jeffrey Boyd, Hari Sundaram	A framework to detect and classify activity transitions in low-power applications.	ICME	2009	DBLP DOI BibTeX RDF
1	Le Zheng, Hsin-Cheng Yao, Fred Tzeng, Payam Heydari	Design and Analysis of a Current-reuse Transmitter for Ultra-low Power Applications.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, Dennis Sylvester, David Blaauw	Low power circuit design based on heterojunction tunneling transistors (HETTs).	ISLPED	2009	DBLP DOI BibTeX RDF	SRAM design, low power applications, tunneling transistor
1	Flavio Carbognani, Luca Henzen	Cross-over current suppressing latch compared to state-of-the-art for low-power low-frequency applications with resonant clocking.	ISLPED	2009	DBLP DOI BibTeX RDF	flipflops, low power design, clock, digital circuits, adiabatic
1	Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada	All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance.	DDECS	2009	DBLP DOI BibTeX RDF
1	Peter Malík, Michal Ufnal, Arkadiusz W. Luczyk, Marcel Baláz, Witold A. Pleskacz	MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio.	DDECS	2009	DBLP DOI BibTeX RDF
1	Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Ali Peiravi, Snorre Aunet, Tuan Vu Cao	New subthreshold concepts in 65nm CMOS technology.	ISQED	2009	DBLP DOI BibTeX RDF
1	J. Brad Boos, Brian R. Bennett, Nicolas A. Papanicolaou, Mario G. Ancona, James G. Champlain, Yeong-Chang Chou, Michael D. Lange, Jeffrey M. Yang, Robert Bass, Doewon Park, Ben V. Shanabrook	Sb-Based n- and p-Channel Heterostructure FETs for High-Speed, Low-Power Applications.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	S. Ramakrishnan, K. T. Lau	Improved Dynamic Current Mode Logic for Low Power Applications.	Journal of Circuits, Systems, and Computers	2008	DBLP DOI BibTeX RDF
1	Billy Tomatsopoulos, Andreas Demosthenous	A CMOS Hard-Decision Analog Convolutional Decoder Employing the MFDA for Low-Power Applications.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Biswajit Mishra, Bashir M. Al-Hashimi	Subthreshold FIR Filter Architecture for Ultra Low Power Applications.	PATMOS	2008	DBLP DOI BibTeX RDF	Subthreshold design, Minimum Energy Point, Ultra Low Power Design, Leakage, FIR
1	Michael E. Imhof, Hans-Joachim Wunderlich, Christian G. Zoellin	Integrating Scan Design and Soft Error Correction in Low-Power Applications.	IOLTS	2008	DBLP DOI BibTeX RDF
1	Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer	Improving the power-delay product in SCL circuits using source follower output stage.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Hai Bing Yin, Xi Zhong Lou, Zhe Lei Xia, Wen Gao	An efficient VLSI architecture for rate disdortion optimization in AVS video encoder.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Charbel J. Akl, Magdy A. Bayoumi	Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family.	ISQED	2008	DBLP DOI BibTeX RDF	circuit family, low-power, high-speed
1	Sami Khawam, Ioannis Nousias, Mark Milward, Ying Yi, Mark Muir, Tughrul Arslan	The Reconfigurable Instruction Cell Array.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Jens-Peter Kaps	Chai-Tea, Cryptographic Hardware Implementations of xTEA.	INDOCRYPT	2008	DBLP DOI BibTeX RDF	symmetric key algorithms, TEA, XTEA, FPGA, ASIC, Efficient implementation
1	Juanjo Noguera, Robert Esser, Katarina Paulsson, Michael Hübner, Jürgen Becker	Towards Novel Approaches in Design Automation for FPGA Power Optimization.	PATMOS	2008	DBLP DOI BibTeX RDF
1	Cheng-Yi Xiong, Jin-Wen Tian, Jian Liu	High performance word level sequential and parallel coding methods and architectures for bit plane coding.	Science in China Series F: Information Sciences	2008	DBLP DOI BibTeX RDF	bit plane coding, word-level sequential, multi-word parallel, high performance
1	Dimitri Kagaris, Themistoklis Haniotakis	Transistor-Level Synthesis for Low-Power Applications.	ISQED	2007	DBLP DOI BibTeX RDF
1	Hamed F. Dadgour, Kaustav Banerjee	Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications.	DAC	2007	DBLP DOI BibTeX RDF
1	Grzegorz Mrugalski, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer	New Test Data Decompressor for Low Power Applications.	DAC	2007	DBLP DOI BibTeX RDF
1	Martin Simlastík, Viera Stopjaková, Libor Majer, Peter Malík	Clockless Implementation of LEON2 for Low-Power Applications.	DDECS	2007	DBLP BibTeX RDF
1	Kiyoo Itoh, Masanao Yamaoka, Takayuki Kawahara	Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	FD-SOI, VT variation, bulk, deep-sub-100-nm CMOS LSIs, minimum VDD, speed variation, leakage, SRAM, DRAM, logic gate
1	Asha Balijepalli, Saurabh Sinha, Yu Cao	Compact modeling of carbon nanotube transistor for early stage process-design exploration.	ISLPED	2007	DBLP DOI BibTeX RDF	optimum delay, schottky-barrier, surface potential, modeling, process variability, CNT
1	Yu Pu, Jose de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha	Vt balancing and device sizing towards high yield of sub-threshold static logic gates.	ISLPED	2007	DBLP DOI BibTeX RDF	variability, sub-threshold
1	Wing On Fung, Tughrul Arslan	A multi-objective algorithm for the design of high performance reconfigurable architectures with embedded decoding.	IEEE Congress on Evolutionary Computation	2007	DBLP DOI BibTeX RDF
1	Scott Hanson, Mingoo Seok, Dennis Sylvester, David Blaauw	Nanometer Device Scaling in Subthreshold Circuits.	DAC	2007	DBLP DOI BibTeX RDF
1	Mingoo Seok, Scott Hanson, Dennis Sylvester, David Blaauw	Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design.	DAC	2007	DBLP DOI BibTeX RDF
1	Anna Arbat, Ángel Dieguez, Josep Samitier	An Improved Temperature Compensation Technique for Current Biasing.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Shilpa Bhoj, Dinesh Bhatia	Thermal Modeling and Temperature Driven Placement for FPGAs.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Tsung-Chu Huang, Gau-Bin Chang, Ling Li	Congruence Synchronous Mirror Delay.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Savvas Koudounas, Julius Georgiou	A Reduced-Area, Low-Power CMOS Bandgap Reference Circuit.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Afshin Nourivand, Chunyan Wang, M. Omair Ahmad	An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM.	ISCAS	2007	DBLP DOI BibTeX RDF
1	S. Alireza Zabihian, Reza Lotfi	Ultra-Low-Voltage, Low-Power, High-Speed Operational Amplifiers Using Body-Driven Gain-Boosting Technique.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Vahid Moalemi, Ali Afzali-Kusha	Subthreshold Pass Transistor Logic for Ultra-Low Power Operation.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Tse-Yu Yeh	Low-Power, High-Performance Architecture of the PWRficient Processor Family.	IEEE Micro	2007	DBLP DOI BibTeX RDF	coherent memory system, low power, computer architecture, chip multiprocessor, high-performance, processor
1	Tung-Chien Chen, Yu-Han Chen, Sung-Fang Tsai, Shao-Yi Chien, Liang-Gee Chen	Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC.	IEEE Trans. Circuits Syst. Video Techn.	2007	DBLP DOI BibTeX RDF
1	Doru-Florin Chiper, M. N. S. Swamy, M. Omair Ahmad	An Efficient Unified Framework for Implementation of a Prime-Length DCT/IDCT With High Throughput.	IEEE Transactions on Signal Processing	2007	DBLP DOI BibTeX RDF
1	Harmander Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka	Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Victor Navarro-Botello, Juan A. Montiel-Nelson, Saeid Nooshabadi	Low Power and High Performance Arithmetic Circuits in Feedthrough CMOS Logic Family for Low Power Applications.	J. Low Power Electronics	2006	DBLP DOI BibTeX RDF
1	Hyoun Soo Park, Bong Hyun Lee, Young Hwan Kim	Level Converting Flip-Flops for High-Speed and Low-Power Applications.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Amara Amara, Frederic Amiel, Thomas Ea	FPGA vs. ASIC for low power applications.	Microelectronics Journal	2006	DBLP DOI BibTeX RDF
1	Yang Song, Takeshi Ikenaga, Satoshi Goto, Zhenyu Liu	Enhanced Partial Distortion Sorting Fast Motion Estimation Algorithm for Low-Power Applications.	APCCAS	2006	DBLP DOI BibTeX RDF
1	S. Miller, Leonard MacEachern	A nanowatt bandgap voltage reference for ultra-low power applications.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Eric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri	CMOS Comparators for High-Speed and Low-Power Applications.	ICCD	2006	DBLP BibTeX RDF
1	Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan	Robust analytical gate delay modeling for low voltage circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	A. Yang, R. Chandra, S. Burke, J. A. DeLaCruz, S. Santhanam, U. Ko	Entering the hot zone: can you handle the heat and be cool?	DAC	2006	DBLP DOI BibTeX RDF	IC packaging, thermal effects, low power
1	Ranjith Kumar, Volkan Kursun	A design methodology for temperature variation insensitive low power circuits.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF
1	Ad M. G. Peeters	Clockless IC design using handshake technology.	ISPD	2006	DBLP DOI BibTeX RDF
1	Luis H. C. Ferreira, Tales Cleber Pimenta, Robson L. Moreno, Wilhelmus A. M. Van Noije	Ultra low-voltage ultra low-power CMOS threshold voltage reference.	SBCCI	2006	DBLP DOI BibTeX RDF	low power, CMOS, low voltage, threshold voltage, voltage reference
1	D. Majumdar, W. Li, H. Leung, B. J. Maundy	A Low Cost/Low Power Chaos-based Transceiver Exploiting Ergodicity.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez	Testing and Diagnosis of Power Switches in SOCs.	European Test Symposium	2006	DBLP DOI BibTeX RDF
1	Wing On Fung, Tughrul Arslan	A stochastic multi-objective algorithm for the design of high performance reconfigurable architectures.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Harmander Deogun, Dennis Sylvester, Kevin J. Nowka	Fine grained multi-threshold CMOS for enhanced leakage reduction.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Alessandro Girardi, Fernando da Rocha Paixão Cortes, Sergio Bampi	A tool for automatic design of analog circuits based on gm/ID methodology.	ISCAS	2006	DBLP DOI BibTeX RDF
1	J. A. P. Reyes, Louis P. Alarcón, L. Alarilla Jr.	A study of floating-point architectures for pipelined RISC processors.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Hui Shao, Chi-Ying Tsui, Wing-Hung Ki	A charge based computation system and control strategy for energy harvesting applications.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Sanjay Kumar Wadhwa, G. K. Siddhartha, Anand Gaurav	Zero Steady State Current Power on Reset Circuit with Brown-Out Detector.	VLSI Design	2006	DBLP DOI BibTeX RDF