Search results for "low power architecture"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Hangu Yeo, Yu Hen Hu	A Novel Matching Criterion And Low Power Architecture For Real-Time Block Based Motion Estimation.	ASAP	1996	DBLP DOI BibTeX RDF	matching criterion, real-time block based motion estimation, video signals, binary level matching criterion, bit-wise comparison, processor level design, total power consumption, motion estimation, power consumption, power consumption, video signal processing, combinational logic, low power architecture
2	Ramen Dutta, T. K. Bhattacharyya	A Low Power Architecture to Extend the Tuning Range of a Quadrature Clock.	VLSI Design	2009	DBLP DOI BibTeX RDF
2	Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu 0001	Low power architecture for high speed packet classification.	ANCS	2008	DBLP DOI BibTeX RDF	energy efficient, hardware accelerator, packet classification, frequency scaling
2	Shuichi Kunie, Takefumi Hiraga, Tatsuya Tokue, Sunao Torii, Taku Ohsawa	Low power architecture and design techniques for mobile handset LSI MedityTM M2.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Chien-Chung Kuo, Sheau-Fang Lei	Design of a Low Power Architecture for CABAC Encoder in H.264.	APCCAS	2006	DBLP DOI BibTeX RDF
2	Wael M. Badawy, Magdy Bayoumi	A Low Power Architecture for HASM Motion Tracking.	VLSI Signal Processing	2004	DBLP DOI BibTeX RDF	video, mesh, affine transformation, motion tracking, low power architecture
2	Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer	A low-power VLSI architecture for turbo decoding.	ISLPED	2003	DBLP DOI BibTeX RDF	MAP decoder, low power architecture, turbo decoding
1	Randy Wayne Morris Jr., Avinash Karanth Kodi	Power-Efficient and High-Performance Multi-level Hybrid Nanophotonic Interconnect for Multicores.	NOCS	2010	DBLP DOI BibTeX RDF	Network-on-Chip, Interconnects, Low-Power architecture, Optoelectronic
1	Athanasios Milidonis, Vasileios Porpodas, Nikolaos Alachiotis, Athanasios P. Kakarountas, Harris E. Michail, George A. Panagiotakopoulos, Costas E. Goutis	Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse.	IET Computers & Digital Techniques	2009	DBLP DOI BibTeX RDF
1	Ehsan Rahiminejad, Reza Lotfi	A low-power architecture for integrating analog-to-digital converters.	ICECS	2009	DBLP DOI BibTeX RDF
1	Mark Woh, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner	AnySP: anytime anywhere anyway signal processing.	ISCA	2009	DBLP DOI BibTeX RDF	fully programmable architecture, high-end signal processing, single-instruction multiple-data parallelism, software defined radio, low-power architecture, simd
1	Sami Khawam, Ioannis Nousias, Mark Milward, Ying Yi, Mark Muir, Tughrul Arslan	The Reconfigurable Instruction Cell Array.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sung-Fang Tsai, Liang-Gee Chen	Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	parallel processing, motion estimation, H.264, data reuse
1	Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick, Robert G. Knobel	Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors.	DAC	2007	DBLP DOI BibTeX RDF
1	Yijun Li, Magdy A. Bayoumi	A Three-Level Parallel High-Speed Low-Power Architecture for EBCOT of JPEG 2000.	IEEE Trans. Circuits Syst. Video Techn.	2006	DBLP DOI BibTeX RDF
1	Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner	SODA: A Low-power Architecture For Software Radio.	ISCA	2006	DBLP DOI BibTeX RDF
1	Felix Bürgin, Flavio Carbognani, Martin Hediger, Hektor Meier, Robert Meyer-Piening, Rafael Santschi, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner	Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm.	DAC	2006	DBLP DOI BibTeX RDF	speech enhancement, low-power architecture, hearing aids
1	Rajesh Vivekanandham, Bharadwaj S. Amrutur, R. Govindarajan	A scalable low power issue queue for large instruction window processors.	ICS	2006	DBLP DOI BibTeX RDF	complexity-effective architecture, wakeup logic, low-power architecture, issue logic
1	Mohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi	ByZFAD: a low switching activity architecture for shift-and-add multipliers.	SBCCI	2006	DBLP DOI BibTeX RDF	adder bypass, byZFAD, hot-block ring counter, shiftand-add multiplier, low-power, switching activity
1	Heng-Yao Lin, Ying-Hong Lu, Bin-Da Liu, Jar-Ferr Yang	Low power design of H.264 CAVLC decoder.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Shingo Yoshizawa, Yoshikazu Miyanaga	Tunable word length architecture for low power wireless OFDM demodulator.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Martin Feldhofer, Christian Rechberger	A Case Against Currently Used Hash Functions in RFID Protocols.	OTM Workshops	2006	DBLP DOI BibTeX RDF
1	Ramy E. Aly, Magdy A. Bayoumi	High-Speed and Low-Power IP for Embedded Block Coding with Optimized Truncation (EBCOT) Sub-Block in JPEG2000 System Implementation.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF
1	Binu K. Mathew, Al Davis, Michael Parker	A low power architecture for embedded perception.	CASES	2004	DBLP DOI BibTeX RDF	computer vision, embedded systems, speech recognition, perception, low power design, VLIW, stream processor
1	Nicolas Darbel, Yves Rasse, Benoît Jubelin, Martial Carrié	A UMTS-FDD Cell Search Engine.	VLSI Signal Processing	2004	DBLP DOI BibTeX RDF	UMTS-WCDMA, initial acquisition, digital matched filter, fast hadamard transform, low power architecture
1	Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen	Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures.	Computer Architecture Letters	2003	DBLP DOI BibTeX RDF	chip multiprocessor, low-power architecture
1	Dan Ernst, Todd M. Austin	Efficient Dynamic Scheduling Through Tag Elimination. (PDF / PS)	ISCA	2002	DBLP DOI BibTeX RDF	complexity-effective architecture, last-tag prediction, dynamic scheduling, low-power architecture
1	Júlio C. B. de Mattos, Luigi Carro	Efficient architecture for FPGA-based microcontrollers.	ISCAS	2002	DBLP DOI BibTeX RDF
1	David Garrett, Mircea R. Stan	A 2.5 Mb/s, 23 mW SOVA traceback chip for turbo decoding applications.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Amr N. Hafez, Mohamed I. Elmasry	A Novel Low Power Low Phase-Noise PLL Architecture for Wireless Transceivers. (PDF / PS)	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
1	Kyoung-Mook Lim, Seh-Woong Jeong, Yong-Chun Kim, Seung-Jae Jeong, Hong-Kyu Kim, Yang-Ho Kim, Bong-Young Chung, Hyung-Lae Roh, H. S. Yang	CalmRISCTM: A Low Power Microcontroller with Efficient Coprocessor Interface.	ICCD	1999	DBLP DOI BibTeX RDF	low-power, microcontroller, coprocessor
1	Imed Ben Dhaou, Hannu Tenhunen	Combinatorial architectural level power optimization for a class of orthogonal transforms.	ISCAS	1999	DBLP DOI BibTeX RDF
1	S. Ramanathan, V. Visvanathan, S. K. Nandy	Architectural Synthesis of Computational Engines for Subband Adaptive Filtering.	VLSI Signal Processing	1999	DBLP DOI BibTeX RDF
1	David Garrett, Mircea R. Stan	Low power architecture of the soft-output Viterbi algorithm.	ISLPED	1998	DBLP DOI BibTeX RDF	SOVA, VA, low power, turbo codes
1	Hiroshi Uno, Keiji Kumatani, Hiroyuki Okuhata, Isao Shirakawa, Toru Chiba	Low power architecture for high speed infrared wireless communication system.	ISLPED	1997	DBLP DOI BibTeX RDF
1	S. Ramanathan, V. Visvanathan	Low-Power Configurable Processor Array for DLMS Adaptive Filtering.	VLSI Design	1997	DBLP DOI BibTeX RDF
1	William H. Mangione-Smith, Phil Seong Ghang, Sean Nazareth, Paul Lettieri, Walt Boring, Rajeev Jain	A low power architecture for wireless multimedia systems: lessons learned from building a power hog.	ISLPED	1996	DBLP DOI BibTeX RDF