Search results for "low power design"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Kevin Skadron, Pradip Bose, Kanad Ghose, Resit Sendag, Joshua J. Yi, Derek Chiou	Low-Power Design and Temperature Management.	IEEE Micro	2007	DBLP DOI BibTeX RDF	low-power design, power management, hardware, energy-aware systems, temperature-aware design
3	Manfred Koegst, Günter Franke, Steffen Rülke, Klaus Feske	Low Power Design of FSMs by State Assignment and Disabling Self-Loops.	EUROMICRO	1997	DBLP DOI BibTeX RDF	FSM synthesis, encoding constraints, low power design, clock gating, state assignment
2	Matthew M. Ziegler, Victor V. Zyuban, George Gristede, Milena Vratonjic, Joshua Friedrich	The opportunity cost of low power design: a case study in circuit tuning.	ISLPED	2009	DBLP DOI BibTeX RDF	low power design, productivity, circuit tuning
2	Soheil Modirzadeh, Brian Fuller, Sandeep Mirchandani, Jon McDonald, Ran Avinun, Camille Kokozaki	It is all about power analysis, exploration and trade-offs.	ISLPED	2009	DBLP DOI BibTeX RDF	IDT, NXP, broadcom, cadence, system design and verification, technical panel, low power, low power design
2	Shengqi Yang, Wenping Wang, Tiehan Lv, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie	Case Study of Reliability-Aware and Low-Power Design.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Shi-Hao Chen, Jiing-Yuan Lin	Experiences of low power design implementation and verification.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Swarup Bhunia, Kaushik Roy	Low power design under parameter variations.	SoCC	2008	DBLP DOI BibTeX RDF
2	Kaushal R. Gandhi, Nihar R. Mahapatra	Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation Bypass.	VLSI Design	2008	DBLP DOI BibTeX RDF	operand encoding, opera- tion bypass, low-power design, soft error
2	James Tschanz	SUB 45nm Low Power Design Challenges.	ISQED	2007	DBLP DOI BibTeX RDF
2	Subhomoy Chattopadhyay	Low power design techniques for nanometer design processes: 65 nm and smaller.	SBCCI	2007	DBLP DOI BibTeX RDF	65 nm, low power, embedded design
2	Tarun Sairam, Wei Zhao, Yu Cao	Optimizing finfet technology for high-speed and low-power design.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	power, energy, variations, speed, threshold voltage, FinFET, noise margin
2	Enrico Macii, Massoud Pedram, Dirk Friebel, Robert C. Aitken, Antun Domic, Roberto Zafalon	Low-power design tools: are EDA vendors taking this matter seriously?	DATE	2006	DBLP DOI BibTeX RDF
2	Heng-Yao Lin, Ying-Hong Lu, Bin-Da Liu, Jar-Ferr Yang	Low power design of H.264 CAVLC decoder.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram	Charge recycling in MTCMOS circuits: concept and analysis.	DAC	2006	DBLP DOI BibTeX RDF	low power design, MTCMOS, charge recycling
2	Kaijian Shi, David Howard	Challenges in sleep transistor design and implementation in low-power designs.	DAC	2006	DBLP DOI BibTeX RDF	methodology, low-power design, power gating, sleep transistor
2	Sangwoon Yang, Jinsub Park, Younggap You	The Smallest ARIA Module with 16-Bit Architecture.	ICISC	2006	DBLP DOI BibTeX RDF	Cryptography, Low Power Design, ARIA
2	Naehyuck Chang, Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Hyung Gyu Lee, Hojun Shim	Graduate Class for System-Level Low-Power Design.	MSE	2005	DBLP DOI BibTeX RDF
2	Jan M. Rabaey	Traveling the Wild Frontier of Ultra Low-Power Design.	PATMOS	2005	DBLP DOI BibTeX RDF
2	Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell	Variable Input Delay CMOS Logic for Low Power Design.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	Zhiyong He, Sébastien Roy 0002, Paul Fortier	High-speed and low-power design of parallel turbo decoder.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Zhijun Huang, Milos D. Ercegovac	High-Performance Low-Power Left-to-Right Array Multiplier Design.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Left-to-right array multiplier, tree multiplier, layout regularity, low-power design, high-performance design
2	N. J. August, Dong Sam Ha	Low power design of DCT and IDCT for low bit rate video codecs.	IEEE Transactions on Multimedia	2004	DBLP DOI BibTeX RDF
2	Mohamed Abbas, Makoto Ikeda, Kunihiro Asada	Noise Effects on Performance of Low Power Design Schemes in Deep Submicron Regime.	DFT	2004	DBLP DOI BibTeX RDF
2	Kanishka Lahiri, Anand Raghunathan	Power analysis of system-level on-chip communication architectures.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	system-on-chip, network-on-chip, low-power design, power analysis, communication architectures
2	Martin Feldhofer, Sandra Dominikus, Johannes Wolkerstorfer	Strong Authentication for RFID Systems Using the AES Algorithm.	CHES	2004	DBLP DOI BibTeX RDF	symmetric challenge-response, Radio frequency identification (RFID), low-power design, Advanced Encryption Standard (AES)
2	Andrea Bona, Vittorio Zaccaria, Roberto Zafalon	Low Effort, High Accuracy Network-on-Chip Power Macro Modeling.	PATMOS	2004	DBLP DOI BibTeX RDF	Network-on-Chip power analysis, communication based low power design, system-level energy optimization
2	E. Seebacher, Gerhard Rappitsch, H. Höller	Process Characterization for Low VTH and Low Power Design.	PATMOS	2003	DBLP DOI BibTeX RDF
2	Paul Flugger	RTL-Based Signal Statistics Calculation Facilitates Low Power Design Approaches.	PATMOS	2003	DBLP DOI BibTeX RDF
2	Reza Lotfi, Mohammad Taherzadeh-Sani, M. Yaser Azizi, Omid Shoaei	A low-power design methodology for high-resolution pipelined analog-to-digital converters.	ISLPED	2003	DBLP DOI BibTeX RDF	low-power design, operational amplifiers, pipelined analog-to-digital converters
2	Sung-Mo Kang	Elements of low power design for integrated systems.	ISLPED	2003	DBLP DOI BibTeX RDF	low power integrated circuits, VLSI, CMOS
2	Jiun-In Guo, Chih-Da Chien, Chien-Chang Lin	A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Sung I. Park, Vijay Raghunathan, Mani B. Srivastava	Energy efficiency and fairness tradeoffs in multi-resource, multi-tasking embedded systems.	ISLPED	2003	DBLP DOI BibTeX RDF	low power design, dynamic power management, embedded system design, energy efficient design
2	Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen	Design theory and implementation for low-power segmented bus systems.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	OLA tree, bus graph model, bus segmentation, bus segmentation cell, low-power design flow, low-power design, ASIC design
2	Kanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi	Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design.	VLSI Design	2002	DBLP DOI BibTeX RDF
2	Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi	Discrete-time battery models for system-level low-power design.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
2	Shih-Hsu Huang	An effective low power design methodology based on interconnect prediction.	SLIP	2001	DBLP DOI BibTeX RDF
2	Abdoul Rjoub, M. Alrousan, O. Jarrah, Odysseas G. Koufopavlou	Multi-level low swing voltage values for low power design applications.	ISCAS	2001	DBLP DOI BibTeX RDF
2	B. A. White, Mohamed I. Elmasry	Low-power design of decimation filters for a digital IF receiver.	IEEE Trans. VLSI Syst.	2000	DBLP DOI BibTeX RDF
2	Ki-Seok Chung, Taewhan Kim, Chien-Liang Liu	Behavioral-level partitioning for low power design in control-dominated application.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
2	Mark S. Bright, Tughrul Arslan	Multi-objective design strategy for high-level low power design of DSP systems.	ISCAS	1999	DBLP DOI BibTeX RDF
2	Michael Eisenring, Jürgen Teich	Interfacing Hardware and Software.	FPL	1998	DBLP DOI BibTeX RDF	automatic interface synthesis, low power design, rapid prototyping, hardware/software codesign
2	Jerry Frenkil	Tools and Methodologies for Low Power Design.	DAC	1997	DBLP DOI BibTeX RDF
2	Vishwani D. Agrawal	Low-Power Design by Hazard Filtering.	VLSI Design	1997	DBLP DOI BibTeX RDF	hazard filtering, multiple transitions, hazard pulses, differential delay, low-power design, power consumption, CMOS logic circuits, CMOS circuit, logic gate, gate delays
2	Uming Ko, T. Balsara, Wai Lee	Low-power design techniques for high-performance CMOS adders.	IEEE Trans. VLSI Syst.	1995	DBLP DOI BibTeX RDF
2	Kimiyoshi Usami, Mark Horowitz	Clustered voltage scaling technique for low-power design.	ISLPD	1995	DBLP DOI BibTeX RDF
2	Hiroaki Ueda, Kozo Kinoshita	Low power design and its testability.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	power reduction tool, power dissipation factor, testability parameters, fault diagnosis, logic testing, delays, probability, design for testability, low power design, logic CAD, testability, fault location, stuck-at faults, CMOS logic circuits, delay faults, CMOS circuit, PORT, automatic test software, redundant faults, transition probability
1	Shireesh Verma	A Special Issue on Low Power Design and Verification Techniques.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Jiongyao Ye, Yu Wan, Takahiro Watanabe	An Adaptive Various-Width Data Cache for Low Power Design.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Hongxia Liu, Bo Yuan	Low-power design and application based on CSD optimization for a fixed coefficient multiplier.	SCIENCE CHINA Information Sciences	2011	DBLP DOI BibTeX RDF
1	David Meisner, Thomas F. Wenisch	Does low-power design imply energy efficiency for data centers?	ISLPED	2011	DBLP BibTeX RDF
1	Sudarshan Srinivasan, Bharath Phanibhushana, Arunkumar Vijayakumar, Sandip Kundu	Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto	Network flow-based simultaneous retiming and slack budgeting for low power design.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Yisheng Miao, Huarui Wu, Huaji Zhu, Feng Li, Feifei Li 0002	Low power design based on seed circulation Supervisory Hand-held device.	EMEIT	2011	DBLP DOI BibTeX RDF
1	Barry M. Pangrle, John Biggs, C. Clavel, Olivier Domerego, Knut M. Just	Beyond UPF & CPF: Low-power design and verification.	DATE	2011	DBLP BibTeX RDF
1	Naehyuck Chang, Jörg Henkel	Guest Editorial: Current Trends in Low-Power Design.	ACM Trans. Design Autom. Electr. Syst.	2010	DBLP DOI BibTeX RDF
1	Bo Lei, Harry Hofmann	Energy consumption and low power design of optical equipment.	Bell Labs Technical Journal	2010	DBLP DOI BibTeX RDF
1	Meng-Hsueh Chiang, Yi-Bo Liao, Jun-Tin Lin, Wei-Chou Hsu, Chu Yu, Pei-Chia Chiang, Y.-Y. Hsu, W.-H. Liu, Shyh-Shyuan Sheu, Keng-Li Su, Ming-Jer Kao, Ming-Jinn Tsai	Low power design of phase-change memory based on a comprehensive model.	IET Computers & Digital Techniques	2010	DBLP DOI BibTeX RDF
1	Ghizlane Lhairech-Lebreton, Philippe Coussy, Eric Martin	Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA.	FPL	2010	DBLP DOI BibTeX RDF
1	Muhammad Nadeem, Stephan Wong, Georgi Kuzmanov	Configurable, low-power design for inverse integer transform in H.264/AVC.	FIT	2010	DBLP DOI BibTeX RDF
1	Mohammad Arjomand, Hamid Sarbazi-Azad	Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Wolfgang Raab, Jörg Berthold, J. A. Ulrich Hachmann, Dominik Langen, Michael Schreiner, Holger Eisenreich, Jens-Uwe Schluessler, Georg Ellguth	Low power design of the X-GOLD® SDR 20 baseband processor.	DATE	2010	DBLP BibTeX RDF
1	Qiang Liu, Tim Todman, Wayne Luk	Combining optimizations in automated low power design.	DATE	2010	DBLP BibTeX RDF
1	Maryam Zaare', Reza Lotfi, Mohammad Maymandi-Nejad	Capacitor scaling for low-power design of cyclic analog-to-digital converters.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Touqeer Azam, David R. S. Dimming	Robust low power design in nano-CMOS technologies.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Chih-Hung Lin, Alex Chien-Lin Huang, Robert Chen-Hao Chang, Kuang-Hao Lin	Low-power design of variable block-size LDPC decoder using nanometer technology.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Thomas Büchner	A holistic view on low power design.	SoCC	2010	DBLP DOI BibTeX RDF
1	Sylvian Kaiser, Ilija Materic, Rabih Saade	ESL solutions for low power design.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar	Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency.	DAC	2010	DBLP DOI BibTeX RDF	scalable effort, support vector machines, low power design, recognition, mining, approximate computing
1	John Goodenough, Rob Aitken	Post-silicon is too late avoiding the $50 million paperweight starts with validated designs.	DAC	2010	DBLP DOI BibTeX RDF	low power design, emulation, post-silicon validation
1	Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys	A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking.	DAC	2010	DBLP DOI BibTeX RDF	WSN node, hardware specialization, microcoded architecture, low-power design
1	Jason Helge Anderson, Chirag Ravishankar	FPGA power reduction by guarded evaluation.	FPGA	2010	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, logic synthesis, technology mapping
1	Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija	Energy efficient implementation of parallel CMOS multipliers with improved compressors.	ISLPED	2010	DBLP DOI BibTeX RDF	arithmetic and logic structures, VLSI, low-power design, high- speed arithmetic, booth encoding
1	Felipe Klein, Alexandro Baldassin, João Moreira, Paulo Centoducatte, Sandro Rigo, Rodolfo Azevedo	STM versus lock-based systems: an energy consumption perspective.	ISLPED	2010	DBLP DOI BibTeX RDF	lock-based systems, parallel programming, low power design, transactional memory, multi-core
1	Weixun Wang, Xiaoke Qin, Prabhat Mishra	Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach.	ISLPED	2010	DBLP DOI BibTeX RDF	dvs, temperature-aware, model checking, low power design
1	Chacko John Deepu, Xiaoyuan Xu, Xiaodan Zou, Libin Yao, Yong Lian	An ECG-on-Chip for Wearable Cardiac Monitoring Devices.	DELTA	2010	DBLP DOI BibTeX RDF	QRS detection, ECG-on-Chip, Low Power design, Wearable devices, Electrocardiography
1	Vincent C. Gaudet, Warren J. Gross	Switching Activity in Stochastic Decoders.	ISMVL	2010	DBLP DOI BibTeX RDF	stochastic decoding, low-power design, iterative decoding, LDPC
1	Zichu Qi, Qi Guo, Ge Zhang, Xiangku Li, Weiwu Hu	Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power.	VLSI Design	2010	DBLP DOI BibTeX RDF	FMA, dual-path FMA, low-power design
1	Suman Kalyan Mandal, Rabi N. Mahapatra, Praveen Bhojwani, Saraju P. Mohanty	IntellBatt: Toward a Smarter Battery.	IEEE Computer	2010	DBLP DOI BibTeX RDF	IntellBatt, Battery management, Smart battery, Low-power design, Hardware
1	Robert Wille, Mathias Soeken, Rolf Drechsler	Reducing the number of lines in reversible circuits.	DAC	2010	DBLP DOI BibTeX RDF	optimization, quantum computation, reversible logic
1	Krishna Kant Chintalapudi	i-MAC - a MAC that learns.	IPSN	2010	DBLP DOI BibTeX RDF
1	Claudio Cicconetti, Luciano Lenzini, Daniele Migliorini, Enzo Mingozzi, Carlo Vallati	Design and performance evaluation of an energy-aware scheduling framework for mobile WiMAX.	MSWiM	2010	DBLP DOI BibTeX RDF
1	Jalel Ktari, Mohamed Abid	A Low Power Design Space Exploration Methodology Based on High Level Models and Confidence Intervals.	J. Low Power Electronics	2009	DBLP DOI BibTeX RDF
1	Xiao Xin Xia, Teng Tiow Tay	Intra-Application Energy Reduction for Microprocessor Low-Power Design.	Journal of Circuits, Systems, and Computers	2009	DBLP DOI BibTeX RDF
1	Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell	Variable Input Delay CMOS Logic for Low Power Design.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Shih-Lun Chen, Ho-Yin Lee, Chiung-An Chen, Hong-Yi Huang, Ching-Hsing Luo	Wireless Body Sensor Network With Adaptive Low-Power Design for Biometrics and Healthcare Applications.	IEEE Systems Journal	2009	DBLP DOI BibTeX RDF
1	Jean-Pierre Schoellkopf, Philippe Magarshack	Low-Power Design Solutions forWireless Multimedia SoCs.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Mojy Chian	Challenges and opportunities in low-power design enablement.	ISLPED	2009	DBLP DOI BibTeX RDF	keynote
1	Khaled Alghathbar	Low power design for silent pass authentication system.	ICITST	2009	DBLP BibTeX RDF
1	Li-gang Hou, Xiao-hong Peng, Wu-chen Wu	Low Power Design of a Grating Detection System Chip.	CSIE	2009	DBLP DOI BibTeX RDF
1	Sumit DasGupta	Common Power Format: A User-driven Ecosystem For Proven Low Power Design Flows.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Stephen Bailey	The Future of Low Power Design is Here: IEEE P1801, aka, UPF 2.0.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Abhijit Chatterjee, Jacob A. Abraham, Adit D. Singh, Elie Maricau, Rakesh Kumar, Chris Papachristou	Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?.	IOLTS	2009	DBLP DOI BibTeX RDF
1	Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi	A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache).	CASES	2009	DBLP DOI BibTeX RDF	low power memory organization, memory organization., remapping cache, variation aware cache, fault tolerance, low power design, low power cache, vfs
1	Veera Papirla, Chaitali Chakrabarti	Energy-aware error control coding for Flash memories.	DAC	2009	DBLP DOI BibTeX RDF	low-power design, Flash memories, error control coding, endurance
1	Emre Tuncer, Jordi Cortadella, Luciano Lavagno	Enabling adaptability through elastic clocks.	DAC	2009	DBLP DOI BibTeX RDF	low power design, GALS, desynchronization, adaptive voltage scaling
1	Qiang Wang, Subodh Gupta, Jason Helge Anderson	Clock power reduction for virtex-5 FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
1	Flavio Carbognani, Luca Henzen	Cross-over current suppressing latch compared to state-of-the-art for low-power low-frequency applications with resonant clocking.	ISLPED	2009	DBLP DOI BibTeX RDF	flipflops, low power design, clock, digital circuits, adiabatic
1	Sushu Zhang, Karam S. Chatha, Goran Konjevod	Near optimal battery-aware energy management.	ISLPED	2009	DBLP DOI BibTeX RDF	low power design, dynamic power management, dynamic voltage/frequency scaling
1	Felipe Klein, Alexandro Baldassin, Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo	On the energy-efficiency of software transactional memory.	SBCCI	2009	DBLP DOI BibTeX RDF	low power design, transactional memory, multi-core, MPSoC
1	Abel G. Silva-Filho, Cristiano C. de Araujo	A methodology for tuning two-level cache hierarchy considering energy and performance.	SBCCI	2009	DBLP DOI BibTeX RDF	exploration mechanism, two-level caches, embedded systems, system-on-chip, low power design, memory hierarchy