Search results for "low power realization"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Low power realization of FIR filters using multirate architectures.	VLSI Design	1996	DBLP DOI BibTeX RDF	low power realization, multirate architectures, computationally efficient implementations, power dissipation reduction, dedicated ASIC implementation, TMS320C2x/C5x programmable DSP, computational complexity, computational complexity, application specific integrated circuits, power analysis, digital filters, FIR filters, FIR filters, digital signal processing chips
2	M. N. Mahesh, Mahesh Mehendale	Low Power Realization of Residue Number System Based FIR Filters.	VLSI Design	2000	DBLP DOI BibTeX RDF	Low power implementation, DSP, Residue Number System(RNS), FIR filters
2	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Low-power realization of FIR filters on programmable DSPs.	IEEE Trans. VLSI Syst.	1998	DBLP DOI BibTeX RDF
2	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters.	VLSI Design	1998	DBLP DOI BibTeX RDF	Hardware/Software High Level Synthesis, Low Power Design, FIR Filters
1	Kavallur Gopi Smitha, A. Prasad Vinod	Low Power Realization and Synthesis of Higher-Order FIR Filters Using an Improved Common Subexpression Elimination Method.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Oscar Gustafsson, Saeeid Tahmasbi Oskuii, Kenny Johansson, Per Gunnar Kjeldsberg	Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data.	PATMOS	2007	DBLP DOI BibTeX RDF	dual bit type, coefficient reordering, MAC, FIR filter, switching activity
1	A. Prasad Vinod, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla	Low Power FIR Filter Realization Using Minimal Difference Coefficients: Part II - Algorithm.	APCCAS	2006	DBLP DOI BibTeX RDF
1	A. Prasad Vinod, Chip-Hong Chang, Pramod Kumar Meher, Ankita Singla	Low Power FIR Filter Realization using Minimal Difference Coefficients: Part I - Complexity Analysis.	APCCAS	2006	DBLP DOI BibTeX RDF
1	A. Prasad Vinod, Ankita Singla, Chip-Hong Chang	Improved differential coefficients-based low power FIR filters. Part I. Fundamentals.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Sergio Saponara, Michele Cassiano, Stefano Marsi, Riccardo Coen, Luca Fanucci	Cost-effective VLSI Design of Non Linear Image Processing Filters.	DSD	2005	DBLP DOI BibTeX RDF
1	Mathias Stäger, Paul Lukowicz, Gerhard Tröster	Implementation and Evaluation of a Low-Power Sound-Based User Activity Recognition System.	ISWC	2004	DBLP DOI BibTeX RDF
1	Mathias Stäger, Paul Lukowicz, Niroshan Perera, T. von Büren, Gerhard Tröster, Thad Starner	SoundButton: Design of a Low Power Wearable Audio Classification System.	ISWC	2003	DBLP DOI BibTeX RDF
1	Nikolaos D. Zervas, Kostas Masselos, Odysseas G. Koufopavlou, Constantinos E. Goutis	Power exploration of multimedia applications realized on embedded cores.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Mahesh Mehendale, Amit Sinha, Sunil D. Sherlekar	Low Power Realization of FIR Filters Implemented using Distributed Arithmetic.	ASP-DAC	1998	DBLP BibTeX RDF
1	Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya	Algorithms for Low Power FIR Filter Realization Using Differential Coefficients.	VLSI Design	1997	DBLP DOI BibTeX RDF	low power FIR filter realization, differential coefficients, computational reduction, convolution, FIR filters
1	Sue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, C. L. Liu	Low power realization of finite state machines - a decomposition approach.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	decomposition of finite state machines, lower power design, state assignment
1	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Techniques for low power realization for FIR filters.	ASP-DAC	1995	DBLP DOI BibTeX RDF