Search results for "low power test"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer	Low-Power Test Data Application in EDT Environment Through Decompressor Freeze.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Nicola Nicolici, Xiaoqing Wen	Embedded Tutorial on Low Power Test.	European Test Symposium	2007	DBLP DOI BibTeX RDF
2	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich	High Defect Coverage with Low-Power Test Sequences in a BIST Environment.	IEEE Design & Test of Computers	2002	DBLP DOI BibTeX RDF
1	Vasileios Tenentes, Xrysovalantis Kavousianos	Low Power Test-Compression for High Test-Quality and Low Test-Data Volume.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Dongsoo Lee, Kaushik Roy	Viterbi-Based Efficient Test Data Compression.	European Test Symposium	2011	DBLP DOI BibTeX RDF	On-Chip Decompressor, Scalability, Logic Test, Test Data Compression, Low-Power Test
1	Shaochong Lei, Feng Liang, Zeye Liu, Xiaoying Wang, Zhen Wang	A Low Power Test Pattern Generator for BIST.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Sobeeh Almukhaizim, Mohammad Gh. Mohammad, Mohammad Khajah	Low-power test in compression-based reconfigurable scan architectures.	SBCCI	2010	DBLP DOI BibTeX RDF
1	Ilia Polian	Special session 4B: Panel low-power test and noise-aware test: Foes or friends?	VTS	2010	DBLP DOI BibTeX RDF
1	Szu-Pang Mu, Mango Chia-Tso Chao	Theoretical analysis for low-power test decompression using test-slice duplication.	VTS	2010	DBLP DOI BibTeX RDF
1	Christian G. Zoellin, Hans-Joachim Wunderlich	Low-power test planning for arbitrary at-speed delay-test clock schemes.	VTS	2010	DBLP DOI BibTeX RDF
1	Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas	Gating internal nodes to reduce power during scan shift.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	gating internal nodes, scan shift power reduction, low power test
1	Meng-Fan Wu, Kai-Shun Hu, Jiun-Lang Huang	LPTest: a Flexible Low-Power Test Pattern Generator.	J. Electronic Testing	2009	DBLP BibTeX RDF
1	Bin Zhou, Yizheng Ye, Zhao-lin Li, Xin-chun Wu, Rui Ke	A new low power test pattern generator using a variable-length ring counter.	ISQED	2009	DBLP DOI BibTeX RDF
1	Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal	On Minimization of Peak Power for Scan Circuit during Test.	European Test Symposium	2009	DBLP DOI BibTeX RDF	Power droop, Test vector re-ordering, Low power test, Peak Power
1	Srivaths Ravi, Rubin A. Parekhji, Jayashree Saxena	Low Power Test for Nanometer System-on-Chips (SoCs).	J. Low Power Electronics	2008	DBLP DOI BibTeX RDF
1	Swapnil Bahl, Rajiv Sarkar, Akhil Garg	Low Power Test.	ITC	2008	DBLP DOI BibTeX RDF
1	Ho Fai Ko, Nicola Nicolici	Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Skewed-load, Scan division, At-speed test, Low-power test
1	Xijiang Lin, Yu Huang 0005	Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Scan shift, Low power test, Scan test, Signal probability
1	Bei Cao, Liyi Xiao, Yongsheng Wang	A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata.	DELTA	2008	DBLP DOI BibTeX RDF
1	Stelios Neophytou, Maria K. Michael	On the Relaxation of n-detect Test Sets.	VTS	2008	DBLP DOI BibTeX RDF	N-detect, test set relaxation
1	Hong-Sik Kim, Sungho Kang, Michael S. Hsiao	A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Keyword System on a chip, Test compression, Low power testing, Scan testing
1	Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji	Methodology for low power test pattern generation using activity threshold control logic.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Grzegorz Mrugalski, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer	New Test Data Decompressor for Low Power Applications.	DAC	2007	DBLP DOI BibTeX RDF
1	Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Riccardo Mariani	A Functional Verification Based Fault Injection Environment.	DFT	2007	DBLP DOI BibTeX RDF
1	Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer	Low Power Embedded Deterministic Test.	VTS	2007	DBLP DOI BibTeX RDF
1	Jinkyu Lee, Nur A. Touba	LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Jun Zhou, Hans-Joachim Wunderlich	Software-based self-test of processors under power constraints.	DATE	2006	DBLP DOI BibTeX RDF	test program generation, low power test, processor test
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A Gated Clock Scheme for Low Power Testing of Logic Cores.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	test-per-scan, test-per-clock, low power design, low power test
1	N.-C. Lai, S.-J. Wang, Y.-H. Fu	Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas	Low Power Test Generation for Path Delay Faults.	J. Low Power Electronics	2005	DBLP DOI BibTeX RDF
1	Kicheol Kim, DongSub Song, Incheol Kim, Sungho Kang	A New Low Power Test Pattern Generator for BIST Architecture.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Youbean Kim, Myung-Hoon Yang, Yong Lee 0002, Sungho Kang	A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura	Low Power Test Compression Technique for Designs with Multiple Scan Chain.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas	Low power test generation for path delay faults using stability functions.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	low power, ATPG, path delay faults
1	Libor Rufer, Salvador Mir, Emmanuel Simeu, C. Domingues	On-Chip Pseudorandom MEMS Testing.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	BIST, pseudorandom sequences, impulse response, MEMS testing
1	Jinkyu Lee, Nur A. Touba	Low Power Test Data Compression Based on LFSR Reseeding.	ICCD	2004	DBLP DOI BibTeX RDF
1	Maciej Bellos, Dimitri Kagaris, Dimitris Nikolos	Low Power Test Set Embedding Based on Phase Shifters.	ISVLSI	2003	DBLP DOI BibTeX RDF
1	Krishna Sekar, Sujit Dey	LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	LI-BIST, crosstalk test, BIST, SoC test, low-power test
1	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich	A Modified Clock Scheme for a Low Power BIST Test Pattern Generator.	VTS	2001	DBLP DOI BibTeX RDF
1	Tsung-Chu Huang, Kuen-Jong Lee	An Input Control Technique for Power Reduction in Scan Circuits During Test Application.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	ATPG, VLSI testing, Power Minimization, Low-power Test, Full-scan