Search results for "low-power FPGA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Tim Tuan, A. Rahman, Satyaki Das, Steven Trimberger, Sean Kao	A 90-nm Low-Power FPGA for Battery-Powered Applications.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Tim Tuan, Sean Kao, Ahmad Arif Rahman, Satyaki Das, Steven Trimberger	A 90nm low-power FPGA for battery-powered applications.	FPGA	2006	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, low-power design, programmable logic
2	Chao You, Jong-Ru Guo, Russell P. Kraft, Kuan Zhou, Michael Chu, John F. McDonald	A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	BC, BCII, FPGA, dynamic routing, CML
1	Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama	Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Shota Ishihara, Masanori Hariyama, Michitaka Kameyama	A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Sergi Consul-Pacareu, Jordi Albo-Canals, Xavier Vilasís-Cardona, Jordi Riera-Babures	High performance DT-CNN camera device design on ACTEL IGLOO low power FPGA.	ECCTD	2011	DBLP DOI BibTeX RDF
1	George Provelengios, Nikolaos S. Voros, Paris Kitsos	Low Power FPGA Implementations of JH and Fugue Hash Functions.	DSD	2011	DBLP DOI BibTeX RDF
1	Jianfeng Zhu, Dong Wu, Yaru Yan, Xiao Yu, Hu He, Liyang Pan	A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
1	Paris Kitsos, Nicolas Sklavos, Athanassios N. Skodras	Low Power FPGA Implementations of 256-bit Luffa Hash Function.	DSD	2010	DBLP DOI BibTeX RDF
1	Felix Eberli	Automotive embedded driver assistance: A real-time low-power FPGA stereo engine using semi-global matching.	ICCD	2010	DBLP DOI BibTeX RDF
1	Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung	Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems.	IET Computers & Digital Techniques	2009	DBLP DOI BibTeX RDF
1	Roberto Gutierrez, Javier Valls	Low-Power FPGA-Implementation of atan(Y/X) Using Look-Up Table Methods for Communication Applications.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	atan(Y/X), FPGA, Wireless communication, CORDIC
1	Shota Ishihara, Masanori Hariyama, Michitaka Kameyama	A low-power FPGA based on autonomous fine-grain power-gating.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Thomas Schmid, Dustin Torres, Mani B. Srivastava	Low-power high-precision timing hardware for sensor networks.	SenSys	2009	DBLP DOI BibTeX RDF	HLTimer, clocks, time synchronization
1	Yu Zhou, Shijo Thekkel, Swarup Bhunia	Low power FPGA design using hybrid CMOS-NEMS approach.	ISLPED	2007	DBLP DOI BibTeX RDF	hybrid CMOS-NEMS, low power, FPGA design
1	Spencer G. Fowers, Dah-Jye Lee, Beau J. Tippetts, Kirt D. Lillywhite, Aaron W. Dennis, James K. Archibald	Vision Aided Stabilization and the Development of a Quad-Rotor Micro UAV.	CIRA	2007	DBLP DOI BibTeX RDF
1	Chao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Bryan S. Goda, John F. McDonald	A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis	A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Yan Zhang, Jussi Roivainen, Aarne Mämmelä	Clock-Gating in FPGAs: A Novel and Comparative Evaluation.	DSD	2006	DBLP DOI BibTeX RDF
1	Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle	A Field Programmable RFID Tag and Associated Design Flow.	FCCM	2006	DBLP DOI BibTeX RDF
1	Somsubhra Mondal, Seda Ogrenci Memik	A low power FPGA routing architecture.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Aman Gayasen, K. Lee, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan	A Dual-VDD Low Power FPGA Architecture.	FPL	2004	DBLP DOI BibTeX RDF
1	Fei Li, Yan Lin, Lei He, Jason Cong	Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, low power, power efficient, dual-Vdd, dual-Vt
1	Deming Chen, Jason Cong, Fei Li, Lei He	Low-power technology mapping for FPGA architectures with dual supply voltages.	FPGA	2004	DBLP DOI BibTeX RDF	low-power FPGA, technology mapping, dual supply voltage
1	Deming Chen, Jason Cong	Delay optimal low-power circuit clustering for FPGAs with dual supply voltages.	ISLPED	2004	DBLP DOI BibTeX RDF	circuit clustering, low-power FPGA, dual supply voltage
1	Vasilios Kalenteridis, Haroula Pournara, K. Siozios, Konstantinos Tatas, George Koutroumpezis, Ilias Pappas, Spiridon Nikolaidis, Stilianos Siskos, D. J. Soudris, Adonios Thanailakis	An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development.	IPDPS	2004	DBLP DOI BibTeX RDF	Low Power FPGA interconnect architecture, CLB Architecture, Graphical User Interface
1	Benton H. Calhoun, Frank Honoré, Anantha Chandrakasan	Design methodology for fine-grained leakage control in MTCMOS.	ISLPED	2003	DBLP DOI BibTeX RDF	fine-grain sleep regions, sneak leakage, low power, design methodology, leakage, circuit design, sleep mode, MTCMOS
1	Jan-Min Hwang, Feng-Yi Chiang, TingTing Hwang	A Re-engineering Approach to Low Power FPGA Design Using SPFD.	DAC	1998	DBLP DOI BibTeX RDF
1	Chau-Shen Chen, TingTing Hwang, C. L. Liu	Low Power FPGA Design - A Re-engineering Approach.	DAC	1997	DBLP DOI BibTeX RDF