Search results for "low-power circuits"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk	High-Quality Circuit Synthesis for Modern Technologies.	ISQED	2008	DBLP DOI BibTeX RDF	nano CMOS technologies, high-speed and low-power circuits, information-driven synthesis, multi-objective optimization, circuit synthesis
2	Rahul Sarpeshkar, Woradorn Wattanapanitch, Benjamin I. Rapoport, Scott K. Arfin, Michael W. Baker, Soumyajit Mandal, Michale S. Fee, Sam Musallam, Richard A. Andersen	Low-Power Circuits for Brain-Machine Interfaces.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Michael Phan, Masaya Sumita	Session 28 overview: Adaptive and low-power circuits: Energy-efficient digital subcommittee.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Manoj K. Garg, Duk-Jin Kim, Deepak S. Turaga, Balakrishnan Prabhakaran	Multimodal analysis of body sensor network data streams for real-time healthcare.	Multimedia Information Retrieval	2010	DBLP DOI BibTeX RDF	multi-modal analysis, systems and communications, sensor networks, body sensor networks
1	Hong Chen, Ming Liu, Wenhan Hao, Yi Chen, Chen Jia, Chun Zhang, Zhihua Wang	Low-Power Circuits for the Bidirectional Wireless Monitoring System of the Orthopedic Implants.	IEEE Trans. Biomed. Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, Kun-Cheng Wu	Fault modeling and testing of retention flip-flops in low power designs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, Dennis Sylvester, David Blaauw	Low power circuit design based on heterojunction tunneling transistors (HETTs).	ISLPED	2009	DBLP DOI BibTeX RDF	SRAM design, low power applications, tunneling transistor
1	Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li	MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency.	ISLPED	2009	DBLP DOI BibTeX RDF	efficiency, DVFS, timing adaptability
1	Maria Gorlatova, Peter R. Kinget, Ioannis Kymissis, Dan Rubenstein, Xiaodong Wang, Gil Zussman	Challenge: ultra-low-power energy-harvesting active networked tags (EnHANTs).	MOBICOM	2009	DBLP DOI BibTeX RDF	energy efficient networking, energy scavenging, ultra-low power communications, UWB, ultra-wideband, energy harvesting
1	Rahul Sarpeshkar, Woradorn Wattanapanitch, Scott K. Arfin, Benjamin I. Rapoport, Soumyajit Mandal, Michael W. Baker, Michale S. Fee, Sam Musallam, Richard A. Andersen	Low-Power Circuits for Brain-Machine Interfaces.	IEEE Trans. Biomed. Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Lech Józwiak, Szymon Bieganski	Technology Library Modelling for Information-driven Circuit Synthesis.	DSD	2008	DBLP DOI BibTeX RDF
1	Lelia Festila, Lorant Andras Szolga, Mihaela Cirlugea, Robert Groza	Analog Multiplying/Weighting VLSI Cells for SVM Classifiers.	KES	2008	DBLP DOI BibTeX RDF	weighting circuits, th domain, square-root domain, current controlled amplifiers, analog multipliers
1	Robert G. Lupu, Andrei Stan, Florina Ungureanu	Patient Monitoring: Wearable Device for Patient Monitoring.	World Congress on Engineering (Selected Papers)	2008	DBLP DOI BibTeX RDF	wearable medical Device, monitoring device, Wearable Device, Patient Monitoring
1	Nikos Dimokas, Dimitrios Katsaros, Yannis Manolopoulos	Cooperative Caching in Wireless Multimedia Sensor Networks.	MONET	2008	DBLP DOI BibTeX RDF	wireless sensor networks, multimedia, cooperative caching, replacement policy
1	Hamidreza Hashempour, Fabrizio Lombardi	Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs.	DATE	2007	DBLP DOI BibTeX RDF	CNTFET, fault detection, nanotechnology, carbon nanotube, defect modeling, CNT
1	Nikos Dimokas, Dimitrios Katsaros, Yannis Manolopoulos	Cooperative caching in wireless multimedia sensor networks.	MobiMedia	2007	DBLP DOI BibTeX RDF
1	Mandeep Singh, Christophe Giacomotto, Bart R. Zeydel, Vojin G. Oklobdzija	Logic Style Comparison for Ultra Low Power Operation in 65nm Technology.	PATMOS	2007	DBLP DOI BibTeX RDF
1	David Rios-Arambula, Aurélien Buhrig, Gilles Sicard, Marc Renaudin	On the Use of Feedback Systems to Dynamically Control the Supply Voltage of Low-Power Circuits.	J. Low Power Electronics	2006	DBLP DOI BibTeX RDF
1	Peter A. Beerel	Asynchronous Design for High-Speed and Low-Power Circuits.	PATMOS	2006	DBLP DOI BibTeX RDF
1	Ranjith Kumar, Volkan Kursun	A design methodology for temperature variation insensitive low power circuits.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF
1	Aleksandar Tasic	Adaptive Multifunctional Circuits and Systems for Future Generations of Wireless Communications.	AHS	2006	DBLP DOI BibTeX RDF	adaptive and low-power circuits and systems, multifunctional circuits and systems, receiver circuits, RF front-end circuits, analog circuits
1	Marco Ottavi, Luca Schiano, Fabrizio Lombardi, Douglas Tougaw	HDLQ: A HDL environment for QCA design.	JETC	2006	DBLP DOI BibTeX RDF	CAD, fault injection, QCA, HDL
1	Gopal Paul, S. N. Pradhan, Ajit Pal, Bhargab B. Bhattacharya	Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Filipp Akopyan, Rajit Manohar, Alyssa B. Apsel	A Level-Crossing Flash Asynchronous Analog-to-Digital Converter.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Aswath Oruganti, Nagarajan Ranganathan	Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Paul Beckett	Low-power circuits using dynamic threshold devices.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	silicide, thin-body, CMOS, nanotechnology, SOI, subthreshold leakage, double-gate
1	Jürgen Fischer, Philip Teichmann, Doris Schmitt-Landsiedel	Scaling trends in adiabatic logic.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	low power, energy recovery, adiabatic computing
1	Hadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi	ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Avik Chakraborty	Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays.	VLSI Design	2005	DBLP DOI BibTeX RDF	Fault models, Testability, Design for test, Iterative logic arrays, Universal test sets, Reversible circuits
1	Didier Van Reeth, Georges G. E. Gielen	A CAD Platform for Sensor Interfaces in Low-Power Applications.	PATMOS	2005	DBLP DOI BibTeX RDF
1	Woopyo Jeong, Bipul Chandra Paul, Kaushik Roy	Adaptive supply voltage technique for low swing interconnects.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Michael Liu, Wei-Shen Wang, Michael Orshansky	Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation.	ISLPED	2004	DBLP DOI BibTeX RDF	variability, yield, power minimization
1	Mohamed Abbas, Makoto Ikeda, Kunihiro Asada	Noise Effects on Performance of Low Power Design Schemes in Deep Submicron Regime.	DFT	2004	DBLP DOI BibTeX RDF
1	Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell	CMOS Circuit Design for Minimum Dynamic Power and Highest Speed.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	D. Satyanarayana, Santanu Chattopadhyay, Jakki Sasidhar	Low Power Combinational Circuit Synthesis targeting Multiplexer based FPGAs.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban	Low-power circuits and technology for wireless digital systems.	IBM Journal of Research and Development	2003	DBLP DOI BibTeX RDF
1	Khalid H. Abed, Raymond E. Siferd	CMOS VLSI Implementation of a Low-Power Logarithmic Converter.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Anti-logarithm, binary logarithms, floating-point normalization, leading-one detector, elementary functions, logarithmic number system, low-power circuits
1	Khalid H. Abed, Raymond E. Siferd	VLSI Implementation of a Low-Power Antilogarithmic Converter.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Antilogarithm, binary logarithm, leading-one detector, logarithmic shifter, logarithmic number system (LNS), low-power circuits
1	Nicola Nicolici, Bashir M. Al-Hashimi	Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Digital systems testing, design for test, low power circuits
1	Debasis Samanta, Nishant Sinha, Ajit Pal	Synthesis of High Performance Low Power Dynamic CMOS Circuits.	VLSI Design	2002	DBLP DOI BibTeX RDF
1	Seongmoon Wang, Sandeep K. Gupta	An automatic test pattern generator for minimizing switching activity during scan testing activity.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Eric Keller	Building Asynchronous Circuits with JBits.	FPL	2001	DBLP DOI BibTeX RDF
1	Antonio G. M. Strollo, Ettore Napoli, Davide De Caro	New clock-gating techniques for low-power flip-flops.	ISLPED	2000	DBLP DOI BibTeX RDF	flip-fops, CMOS digital integrated circuits, transition probability, low-power circuits
1	Junhyung Um, Taewhan Kim, C. L. Liu	A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis.	DAC	2000	DBLP DOI BibTeX RDF
1	Andrea Gerosa, Arianna Novo, Andrea Neviani	Low-power sensing and digitization of cardiac signals based on sigma-delta conversion (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF
1	Khalil Najafi	Low-power micromachined microsystems (invited talk).	ISLPED	2000	DBLP DOI BibTeX RDF	micromachining, power sources, low-power, MEMS, energy harvesting, microsystems
1	Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	ALPS: A Peak Power Estimation Tool for Sequential Circuits.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
1	Unni Narayanan, Peichen Pan, C. L. Liu	Low power logic synthesis under a general delay model.	ISLPED	1998	DBLP DOI BibTeX RDF
1	Gustavo E. Téllez, Amir H. Farrahi, Majid Sarrafzadeh	Activity-driven clock design for low power circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	Gated Clock Tree, Sleep Mode, Power minimization, Clock Tree
1	Mircea R. Stan, Wayne P. Burleson	Bus-invert coding for low-power I/O.	IEEE Trans. VLSI Syst.	1995	DBLP DOI BibTeX RDF