Search results for "low-power electronics"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Ajith Amerasekera	Ultra low power electronics in the next decade.	ISLPED	2010	DBLP DOI BibTeX RDF	low-power electronics, power management
3	Tsugio Makimoto, Yoshio Sakai	Evolution of low power electronics and its future applications.	ISLPED	2003	DBLP DOI BibTeX RDF	Nomadic Age, low power technologies, robotics, applications
2	Ajit Gupte, Bharadwaj Amrutur	Adaptive Global Elimination Algorithm for Low Power Motion Estimation (J. Low Power Electronics 5: 1-16 (2009)).	J. Low Power Electronics	2009	DBLP DOI BibTeX RDF
2	Diana Marculescu, Jörg Henkel	Guest Editorial Special Section on Low-Power Electronics and Design.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Rahul Sarpeshkar	Invited Talk: Ultra Low Power Electronics for Medicine.	BSN	2006	DBLP DOI BibTeX RDF
2	Patrick Girard	Welcome to the Journal of Low Power Electronics.	J. Low Power Electronics	2005	DBLP DOI BibTeX RDF
2	James D. Meindl	A history of low power electronics: how it began and where it's headed.	ISLPED	1997	DBLP DOI BibTeX RDF
2	Kai Chen 0002, Yuhua Cheng, Chenming Hu	Device design for low power electronics with accurate deep submicrometer LDD-MOSFET models.	ISLPED	1996	DBLP DOI BibTeX RDF
1	J. Mazurier, O. Weber, François Andrieu, Alain Toffoli, Olivier Thomas, Fabienne Allain, J.-P. Noel, Marc Belleville, Olivier Faynot, T. Poiroux	Ultra-Thin Body and Buried Oxide (UTBB) FDSOI Technology with Low Variability and Power Management Capability for 22 nm Node and Below.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Smriti Joshi, Anne Lombardot, Philippe Flatresse, Carmelo D'agostino, Andre Juge, Edith Beigné, Stéphane Girard	Statistical Estimation of Dominant Physical Parameters for Leakage Variability in 32 Nanometer CMOS, Under Supply Voltage Variations.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Julien De Vos, Denis Flandre, David Bol	Pushing Adaptive Voltage Scaling Fully on Chip.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Subhash Chander, Pramod Agarwal, Indra Gupta	Design and Implementation of Field Programmable Gate Array based Digital Pulse Width Modulator for Synchronous Buck Converter.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Ge Chen, Saeid Nooshabadi	Optimization of On-Chip Interconnect Signaling for Low Energy and High Performance.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Rohit Dhiman, Rajeevan Chandel	Sub-Threshold Delay and Power Analysis of Complementary Metal-Oxide Semiconductor Buffer Driven Interconnect Load for Ultra Low Power Applications.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Nadine Azémard, Marc Belleville	Selected Articles from the VARI 2011 Workshop.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Ming-Hung Chang, Shang-Yuan Lin, Wei Hwang	A 0.4 V 520 nW 990 μm2 Fully Integrated Frequency-Domain Smart Temperature Sensor in 65 nm CMOS.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Masoud Daneshtalab, Masoumeh Kamali, Masoumeh Ebrahimi, S. Mohammadi, Ali Afzali-Kusha, Juha Plosila	Adaptive Input-Output Selection Based On-Chip Router Architecture.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Vyasa Sai, Ajay Ogirala, Marlin H. Mickle	Low-Power Data Driven Symbol Decoder for a UHF Passive RFID Tag.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Yang Xu, Hu He, Zhizhong Tang	Energy Consumption Optimized Scheduling Algorithm for Clustered VLIW Architectures.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Kaushik Bhattacharyya, Pradip Mandal	Improvement of Performance of Dynamically Reconfigurable Switched Capacitor Based Non-Overlap Rotational Time Interleaved Embedded DC-DC Converter.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Muhammad Tariqus Salam, Fayçal Mounaïm, Dang Khoa Nguyen, Mohamad Sawan	Low-Power Circuit Techniques for Epileptic Seizures Detection and Subsequent Neurostimulation.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Tushar Gupta, Clement Bertolini, Olivier Héron, Nicolas Ventroux, Thomas Zimmer, François Marc	Impact of Power Consumption and Temperature on Processor Lifetime Reliability.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Hassan Salmani, Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty, Patrick Girard, Xiaoqing Wen	Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Gabriel A. Rincón-Mora, Andres A. Blanco, Justin P. Vogt	A 1.3-μW, 0.6-μm CMOS Current-Frequency Analog-Digital Converter for Implantable Blood-Glucose Monitors.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Biswajit Maity, Soumya Gangula, Pradip Mandal	Design and Implementation of an Area and Power Efficient Switched-Capacitor Based Embedded DC-DC Converter.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty	Ensuring Power-Safe Application of Test Patterns Using an Effective Gating Approach Considering Current Limits.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Somayyeh Rahimian, Vasilis F. Pavlidis, Giovanni De Micheli	Inter-Plane Communication Methods for 3-D ICs.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez	Digital Adaptive Calibration of Multi-Step Analog to Digital Converters.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Pierre-Antoine Haddad, Geoffroy Gosset, Denis Flandre	Design of an Ultra-Low-Power Multi-Stage AC/DC Voltage Rectifier and Multiplier Using a Fully-Automated and Portable Design Methodology.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Jean Michel Portal, Marc Bocquet, Damien Deleruyelle, Christophe Muller	Non-Volatile Flip-Flop Based on Unipolar ReRAM for Power-Down Applications.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Bin Zhou, Liyi Xiao, Yizheng Ye, Xin-chun Wu, Bei Cao	Test Pattern Generation Based on Multi-TRC Scan Architecture for Reducing Test Cost.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Naehyuck Chang, Hiroshi Nakamura, Koji Inoue, Kenichi Osada, Massimo Poncino (eds.)	Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011, Fukuoka, Japan, August 1-3, 2011	ISLPED	2011	DBLP BibTeX RDF
1	Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada	Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA.	ISLPED	2011	DBLP BibTeX RDF
1	Jong-Kwan Woo, Tae-Hoon Kim, Hyongmin Lee, Sunkwon Kim, Hyunjoong Lee, Suhwan Kim	A comparator-based cyclic analog-to-digital converter with boosted preset voltage.	ISLPED	2011	DBLP BibTeX RDF
1	Bushra Ahsan, Lorena Ndreu, Isidoros Sideris, Yiannakis Sazeides, Sachin Idgunji, Emre Özer	Eliminating energy of same-content-cell-columns of on-chip SRAM arrays.	ISLPED	2011	DBLP BibTeX RDF
1	Pingqiang Zhou, Jieming Yin, Antonia Zhai, Sachin S. Sapatnekar	NoC frequency scaling with flexible-pipeline routers.	ISLPED	2011	DBLP BibTeX RDF
1	Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang	Analysis of power-performance for ultra-thin-body GeOI logic circuits.	ISLPED	2011	DBLP BibTeX RDF
1	Ken Takeuchi	Green high performance storage class memory & NAND flash memory hybrid SSD system.	ISLPED	2011	DBLP BibTeX RDF
1	Phillip Stanley-Marbell, Victoria Caparrós Cabezas, Ronald P. Luijten	Pinned to the walls: impact of packaging and application properties on the memory and power walls.	ISLPED	2011	DBLP BibTeX RDF
1	Saro Meguerdichian, Miodrag Potkonjak	Matched public PUF: ultra low energy security platform.	ISLPED	2011	DBLP BibTeX RDF
1	Hyunjoong Lee, Hyongmin Lee, Jong-Kwan Woo, Sunkwon Kim, Young June Park, Suhwan Kim	A CMOs readout integrated circuit with wide dynamic range for a CNT bio-sensor array system.	ISLPED	2011	DBLP BibTeX RDF
1	Hong-Ting Lin, Yi-Lin Chuang, Tsung-Yi Ho	Pulsed-latch-based clock tree migration for dynamic power reduction.	ISLPED	2011	DBLP BibTeX RDF
1	Takayasu Sakurai	Designing ultra-low voltage logic.	ISLPED	2011	DBLP BibTeX RDF
1	Sang Phill Park, Soo Youn Kim, Dongsoo Lee, Jae-Joon Kim, W. Paul Griffin, Kaushik Roy	Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors.	ISLPED	2011	DBLP BibTeX RDF
1	Xin Zhao, Jeremy R. Tolbert, Chang Liu, Saibal Mukhopadhyay, Sung Kyu Lim	Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits.	ISLPED	2011	DBLP BibTeX RDF
1	Tadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai	Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS.	ISLPED	2011	DBLP BibTeX RDF
1	Jongmin Lee 0002, Seokin Hong, Soontae Kim	TLB index-based tagging for cache energy reduction.	ISLPED	2011	DBLP BibTeX RDF
1	Pi-Cheng Hsiu, Chun-Han Lin, Cheng-Kang Hsieh	Dynamic backlight scaling optimization for mobile streaming applications.	ISLPED	2011	DBLP BibTeX RDF
1	Denis Dondi, Piero Zappi, Tajana Simunic Rosing	A scheduling algorithm for consistent monitoring results with solar powered high-performance wireless embedded systems.	ISLPED	2011	DBLP BibTeX RDF
1	Aldhino Anggorosesar, Young-Jin Kim	Object-based local dimming for LCD systems with LED BLUs.	ISLPED	2011	DBLP BibTeX RDF
1	Kentaro Honda, Katsuyuki Ikeuchi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai	Reduction of minimum operating voltage (VDDmin) of CMOS logic circuits with post-fabrication automatically selective charge injection.	ISLPED	2011	DBLP BibTeX RDF
1	David Li, Pierce Chuang, David Nairn, Manoj Sachdev	Design and analysis of metastable-hardened flip-flops in sub-threshold region.	ISLPED	2011	DBLP BibTeX RDF
1	Karthik Kumar, Kshitij A. Doshi, Martin Dimitrov, Yung-Hsiang Lu	Memory energy management for an enterprise decision support system.	ISLPED	2011	DBLP BibTeX RDF
1	Daeyeon Kim, Vikas Chandra, Robert C. Aitken, David Blaauw, Dennis Sylvester	Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs.	ISLPED	2011	DBLP BibTeX RDF
1	Raid Zuhair Ayoub, Ümit Y. Ogras, Eugene Gorbatov, Yanqin Jin, Timothy Kam, Paul Diefenbaugh, Tajana Rosing	OS-level power minimization under tight performance constraints in general purpose systems.	ISLPED	2011	DBLP BibTeX RDF
1	Yasunori Miyahara	Next-generation wireless technologies trends for ultra low energy.	ISLPED	2011	DBLP BibTeX RDF
1	Chin-Hung Lin, Ing-Chao Lin, Kuan-Hui Li	TG-based technique for NBTI degradation and leakage optimization.	ISLPED	2011	DBLP BibTeX RDF
1	Yanzhi Wang, Younghyun Kim, Qing Xie, Naehyuck Chang, Massoud Pedram	Charge migration efficiency optimization in hybrid electrical energy storage (HEES) systems.	ISLPED	2011	DBLP BibTeX RDF
1	Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich	SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures.	ISLPED	2011	DBLP BibTeX RDF
1	Mitsumasa Koyanagi	3D super chip technology to achieve low-power and high-performance system-on-a chip.	ISLPED	2011	DBLP BibTeX RDF
1	Amin Jadidi, Mohammad Arjomand, Hamid Sarbazi-Azad	High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement.	ISLPED	2011	DBLP BibTeX RDF
1	Manuj R. Sabharwal	Software power optimization: analysis and optimization for energy-efficient software.	ISLPED	2011	DBLP BibTeX RDF
1	Kai-Chiang Wu, Diana Marculescu, Ming-Chao Lee, Shih-Chieh Chang	Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits.	ISLPED	2011	DBLP BibTeX RDF
1	Youngtaek Kim, Lizy Kurian John	Automated di/dt stressmark generation for microprocessor power delivery networks.	ISLPED	2011	DBLP BibTeX RDF
1	Po-Hsun Wu, Tsung-Yi Ho	Thermal-aware bus-driven floorplanning.	ISLPED	2011	DBLP BibTeX RDF
1	Liyuan Liu, Dongmei Li, Yafei Ye, Zhihua Wang	A 92.4dB SNDR 24kHz ΔΕ modulator consuming 352μW.	ISLPED	2011	DBLP BibTeX RDF
1	Azalia Mirhoseini, Farinaz Koushanfar	Learning to manage combined energy supply systems.	ISLPED	2011	DBLP BibTeX RDF
1	Mahsan Rofouei, Miodrag Potkonjak, Majid Sarrafzadeh	Energy efficient E-textile based portable keyboard.	ISLPED	2011	DBLP BibTeX RDF
1	Mitsuo Yokokawa, Fumiyoshi Shoji, Atsuya Uno, Motoyoshi Kurokawa, Tadashi Watanabe	The K computer: Japanese next-generation supercomputer development project.	ISLPED	2011	DBLP BibTeX RDF
1	Anurag Nigam, Clinton Wills Smullen IV, Vidyabhushan Mohan, Eugene Chen, Sudhanva Gurumurthi, Mircea R. Stan	Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM).	ISLPED	2011	DBLP BibTeX RDF
1	Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai	12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics.	ISLPED	2011	DBLP BibTeX RDF
1	Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta	Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores.	ISLPED	2011	DBLP BibTeX RDF
1	Piotr Patronik, Krzysztof S. Berezowski, Stanislaw J. Piestrak, Janusz Biernat, Aviral Shrivastava	Fast and energy-efficient constant-coefficient FIR filters using residue number system.	ISLPED	2011	DBLP BibTeX RDF
1	Warren Wai-Kit Shum, Jason Helge Anderson	FPGA glitch power analysis and reduction.	ISLPED	2011	DBLP BibTeX RDF
1	Woojoo Lee, Younghyun Kim, Yanzhi Wang, Naehyuck Chang, Massoud Pedram, Soohee Han	Versatile high-fidelity photovoltaic module emulation system.	ISLPED	2011	DBLP BibTeX RDF
1	Sachin S. Sapatnekar	The whys and hows of thermal management.	ISLPED	2011	DBLP BibTeX RDF
1	Junyoung Park, Jacob A. Abraham	A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems.	ISLPED	2011	DBLP BibTeX RDF
1	Lei Jiang, Youtao Zhang, Jun Yang 0002	Enhancing phase change memory lifetime through fine-grained current regulation and voltage upscaling.	ISLPED	2011	DBLP BibTeX RDF
1	Xun He, Dajiang Zhou, Xin Jin, Satoshi Goto	A 98 GMACs/W 32-core vector processor in 65nm CMOS.	ISLPED	2011	DBLP BibTeX RDF
1	Qiong Cai, José González, Grigorios Magklis, Pedro Chaparro, Antonio González	Thread shuffling: combining DVFS and thread migration toreduce energy consumptions for multi-core systems.	ISLPED	2011	DBLP BibTeX RDF
1	Xin Fan, Shigeru Kusakabe	Energy efficient scheduling for multithreaded programs on general-purpose processors.	ISLPED	2011	DBLP BibTeX RDF
1	Vaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, Kaushik Roy	IMPACT: imprecise adders for low-power approximate computing.	ISLPED	2011	DBLP BibTeX RDF
1	Toshiro Hiramoto	Ultra-low-voltage operation: device perspective.	ISLPED	2011	DBLP BibTeX RDF
1	Ming-Hung Chang, Yi-Te Chiu, Shu-Lin Lai, Wei Hwang	A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS.	ISLPED	2011	DBLP BibTeX RDF
1	Joseph F. Ryan, Sudhanshu Khanna, Benton H. Calhoun	An analytical model for performance yield of nanoscale SRAM accounting for the sense amplifier strobe signal.	ISLPED	2011	DBLP BibTeX RDF
1	Amir Zjajo, José Pineda de Gyvez	A 1.2v 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOs.	ISLPED	2011	DBLP BibTeX RDF
1	Rami A. Abdallah, Pradeep S. Shenoy, Naresh R. Shanbhag, Philip T. Krein	System energy minimization via joint optimization of the DC-DC converter and the core.	ISLPED	2011	DBLP BibTeX RDF
1	Aaron Carpenter, Jianyun Hu, Michael C. Huang, Hui Wu, Peng Liu	A design space exploration of transmission-line links for on-chip interconnect.	ISLPED	2011	DBLP BibTeX RDF
1	David Meisner, Thomas F. Wenisch	Does low-power design imply energy efficiency for data centers?	ISLPED	2011	DBLP BibTeX RDF
1	Kee Sup Kim	Holistic low power solutions for the new world.	ISLPED	2011	DBLP BibTeX RDF
1	Zvi M. Kedem, Vincent John Mooney, Kirthi Krishna Muntimadugu, Krishna V. Palem	An approach to energy-error tradeoffs in approximate ripple carry adders.	ISLPED	2011	DBLP BibTeX RDF
1	Jun-Hong Weng, Ching-Yuan Yang, Yi-Lin Jhu	A low-power direct digital frequency synthesizer using an analogue-sine-conversion technique.	ISLPED	2011	DBLP BibTeX RDF
1	Yi-Wei Chiu, Jihi-Yu Lin, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang	8T single-ended sub-threshold SRAM with cross-point data-aware write operation.	ISLPED	2011	DBLP BibTeX RDF
1	Alessandro Vincenzi, Arvind Sridhar, Martino Ruggiero, David Atienza	Fast thermal simulation of 2D/3D integrated circuits exploiting neural networks and GPUs.	ISLPED	2011	DBLP BibTeX RDF
1	Sehwan Kim, Pai H. Chou	Energy harvesting by sweeping voltage-escalated charging of a reconfigurable supercapacitor array.	ISLPED	2011	DBLP BibTeX RDF
1	Jason Cong, Karthik Gururaj, Hui Huang 0001, Chunyue Liu, Glenn Reinman, Yi Zou	An energy-efficient adaptive hybrid cache.	ISLPED	2011	DBLP BibTeX RDF
1	Carlo Brandolese, Simone Corbetta, William Fornaciari	Software energy estimation based on statistical characterization of intermediate compilation code.	ISLPED	2011	DBLP BibTeX RDF
1	Yiran Chen, Weng-Fai Wong, Hai Li, Cheng-Kok Koh	Processor caches with multi-level spin-transfer torque ram cells.	ISLPED	2011	DBLP BibTeX RDF
1	Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Shigeki Tawa, Koji Maekawa, Motoshige Igarashi, Koji Nii	A dynamic body-biased SRAM with asymmetric halo implant MOSFETs.	ISLPED	2011	DBLP BibTeX RDF
1	Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga	Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs.	ISLPED	2011	DBLP BibTeX RDF