Search results for "low-power processors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Chuan-Yu Wang, Kaushik Roy	Control unit synthesis targeting low-power processors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	control unit synthesis, low-power processors, low-power decoding scheme, microprogrammed architecture, nanoprogrammed architecture, 8086 instruction set, instruction opcodes, computer architecture, logic design, encoding, decoding, microprocessor chips, graph embedding, instruction sets, microprogramming, CMOS circuits, logic minimization, system reliability, switching activity, minimisation of switching nets, pseudo-Boolean programming
1	Felix Xiaozhu Lin, Zhen Wang, Robert LiKamWa, Lin Zhong	Reflex: using low-power processors in smartphones without knowing them.	ASPLOS	2012	DBLP DOI BibTeX RDF
1	Phillip Stanley-Marbell, Victoria Caparrós Cabezas	Performance, Power, and Thermal Analysis of Low-Power Processors for Scale-Out Systems.	IPDPS Workshops	2011	DBLP DOI BibTeX RDF
1	Jungseob Lee, Chi-Chao Wang, Hamid Reza Ghasemi, Lloyd Bircher, Yu Cao, Nam Sung Kim	Workload-adaptive process tuning strategy for power-efficient multi-core processors.	ISLPED	2010	DBLP DOI BibTeX RDF	process parameter tuning, DVFS, multi-core processor
1	Adrian M. Caulfield, Laura M. Grupp, Steven Swanson	Gordon: using flash memory to build fast, power-efficient clusters for data-intensive applications.	ASPLOS	2009	DBLP DOI BibTeX RDF	data centric, solid-state storage, flash memory, cluster architecture
1	Vimal Mehta, Weihua Sheng, Tianzhou Chen, Quan Shi	Development and calibration of a low cost wireless camera sensor network.	IROS	2009	DBLP DOI BibTeX RDF
1	Renée St. Amant, Daniel A. Jiménez, Doug Burger	Low-power, high-performance analog neural branch prediction.	MICRO	2008	DBLP DOI BibTeX RDF
1	Stefano Tennina, Marco Di Renzo, Fortunato Santucci, Fabio Graziosi	On the Distribution of Positioning Errors in Wireless Sensor Networks: A Simulative Comparison of Optimization Algorithms.	WCNC	2008	DBLP DOI BibTeX RDF
1	Amit Pabalkar, Aviral Shrivastava, Arun Kannan, Jongeun Lee	SDRM: Simultaneous Determination of Regions and Function-to-Region Mapping for Scratchpad Memories.	HiPC	2008	DBLP DOI BibTeX RDF	Code overlay, Compilers, Scratchpad memory, Static code analysis
1	Kiyoshi Hayakawa	SCMD-CLUSTER: Design, Implementation, and Primary Evaluation.	PDCAT	2007	DBLP DOI BibTeX RDF
1	Taisuke Boku, Mitsuhisa Sato, Daisuke Takahashi, Hiroshi Nakashima, Hiroshi Nakamura, Satoshi Matsuoka, Yoshihiko Hotta	MegaProto/E: power-aware high-performance cluster with commodity technology.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Manish Verma, Peter Marwedel	Overlay techniques for scratchpad memories in low power embedded processors.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	George Almási, Gyan Bhanot, Alan Gara, Manish Gupta, James C. Sexton, Robert Walkup, Vasily Bulatov, Andrew W. Cook, Bronis R. de Supinski, James N. Glosli, Jeffrey A. Greenough, François Gygi, Alison Kubota, Steve Louis, Thomas E. Spelce, Frederick H. Streitz, Peter L. Williams, Robert K. Yates, Charles Archer, José E. Moreira, Charles A. Rendleman	Scaling physics and material science applications on a massively parallel Blue Gene/L system.	ICS	2005	DBLP DOI BibTeX RDF	scalability, MPI, applications, supercomputers, Blue Gene/L
1	Jacob Sorber, Nilanjan Banerjee, Mark D. Corner, Sami Rollins	Turducken: hierarchical power management for mobile devices.	MobiSys	2005	DBLP DOI BibTeX RDF	mobile computing, pervasive computing, power management, energy management, embedded devices, low-power computing
1	Paolo D'Alberto, Alexandru Nicolau, Alexander V. Veidenbaum, Rajesh K. Gupta	Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Cache-line size adaptivity, parameterized loop nests, interference, spatial locality
1	George S. Almasi, Gyan Bhanot, Dong Chen, Maria Eleftheriou, Blake G. Fitch, Alan Gara, Robert S. Germain, John A. Gunnels, Manish Gupta, Philip Heidelberger, Michael Pitman, Aleksandr Rayshubskiy, James C. Sexton, Frank Suits, Pavlos Vranas, Robert Walkup, T. J. Christopher Ward, Yuriy Zhestkov, Alessandro Curioni, Wanda Andreoni, Charles Archer, José E. Moreira, Richard Loft, Henry M. Tufo, Theron Voran, Katherine Riley	Early Experience with Scientific Applications on the Blue Gene/L Supercomputer.	Euro-Par	2005	DBLP DOI BibTeX RDF
1	Akihiro Chiyonobu, Toshinori Sato	Investigating heterogeneous combination of functional units for a criticality-based low-power processor architecture.	ISICT	2004	DBLP DOI BibTeX RDF
1	Vasily G. Moshnyaga	Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	bit-truncation, low-power design, video processing, switching activity
1	Guilherme Ottoni, Sandro Rigo, Guido Araujo, Subramanian Rajagopalan, Sharad Malik	Optimal Live Range Merge for Address Register Allocation in Embedded Programs.	CC	2001	DBLP DOI BibTeX RDF
1	Tim Anderson, Sanjive Agarwala	Effective Hardware-Based Two-Way Loop Cache for High Performance Low Power Processors. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
1	Enric Musoll	Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power Processors. (PDF / PS)	MICRO	1999	DBLP DOI BibTeX RDF