Search results for "manufacturing yield"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Jianfeng Luo, Subarna Sinha, Qing Su, Jamil Kawa, Charles Chiang	An IC manufacturing yield model considering intra-die variations.	DAC	2006	DBLP DOI BibTeX RDF	random variation, systematic variation, CMP, spatial correlation, manufacturing yield
2	Xiaojun Ma, Masoud Hashempour, Lei Wang 0003, Fabrizio Lombardi	Manufacturing yield of QCA circuits by synthesized DNA self-assembled templates.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	design, manufacturing, nanotechnology, defect tolerance
2	Arthur Nieuwoudt, Tamer Ragheb, Hamid Nejati, Yehia Massoud	Increasing Manufacturing Yield for Wideband RF CMOS LNAs in the Presence of Process Variations.	ISQED	2007	DBLP DOI BibTeX RDF
2	M. A. Karim, Saman K. Halgamuge, A. J. R. Smith, Arthur L. Hsu	Manufacturing Yield Improvement by Clustering.	ICONIP	2006	DBLP DOI BibTeX RDF	Clustering quality, Filtration of noisy data, Data mining, Self-organising map, Yield improvement
2	T. Ritthidetch, R. Masuchun, A. Chaikla, P. Julsereewong, K. Tirasesth	Improving suspension manufacturing yield using polynomial regression.	ICARCV	2004	DBLP DOI BibTeX RDF
2	Witold A. Pleskacz	Yield Estimation of VLSI Circuits with Downscaled Layouts. (PDF / PS)	DFT	1999	DBLP DOI BibTeX RDF	IC layout scaling, VLSI circuits, critical area, spot defects, manufacturing yield
1	Nishant Dhumane, Sandip Kundu	Critical area driven dummy fill insertion to improve manufacturing yield.	ISQED	2012	DBLP DOI BibTeX RDF
1	Ding-Ming Kwai, Chang-Tzu Lin	3D Stacked IC layout considering bond pad density and doubling for manufacturing yield improvement.	ISQED	2011	DBLP DOI BibTeX RDF
1	Hui Zhu, Sébastien Le Beux, Nataliya Yakymets, Ian O'Connor	Using Self-Reconfiguration to Increase Manufacturing Yield of CNTFET-based Architectures.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita R. Das, Jian Li	Cost-driven 3D integration with interconnect layers.	DAC	2010	DBLP DOI BibTeX RDF	interconnect service layer, three-dimensional integrated circuit, network-on-chip
1	Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke	Necromancer: enhancing system throughput by animating dead cores.	ISCA	2010	DBLP DOI BibTeX RDF	execution abstraction, heterogeneous core coupling, manufacturing defects
1	Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke	ZerehCache: armoring cache architectures in high defect density technologies.	MICRO	2009	DBLP DOI BibTeX RDF	fault-tolerant cache, process variation, manufacturing yield
1	Anmol Mathur, Qi Wang	Power Reduction Techniques and Flows at RTL and System Level.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Lun-Chun Wei, Hung-Ming Chen, Li-Da Huang, Sarah Songjie Xu	Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flow.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	redundant via insertion, network flow, relaxation
1	Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud	Robust reconfigurable filter design using analytic variability quantification techniques.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Antun Domic	Design or manufacturing: which will be best for the future of the semiconductor roadmap?	ISPD	2008	DBLP DOI BibTeX RDF
1	David Atienza, Giovanni De Micheli, Luca Benini, José L. Ayala, Pablo Garcia Del Valle, Michael DeBole, Vijaykrishnan Narayanan	Reliability-aware design for nanometer-scale devices.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Anil Deshpande	Verification of IP-Core Based SoC's.	ISQED	2008	DBLP DOI BibTeX RDF	Verification, SoC, Moore's Law
1	Srikanth Venkataraman, Nagesh Tamarapalli	DFM / DFT / SiliconDebug / Diagnosis.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Sachin S. Sapatnekar	Building your yield of dreams.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF	nanoscale, modeling variations, CMOS, yield, design for manufacturability, DFM
1	Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka	Performance-Optimized Design for Parametric Reliability.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Adaptive design, Process variation compensation, Parametric reliability, Noise tolerance
1	Chiung-Fen Huang, Ruey-Shun Chen	Application of new Apriori algorithm MDNC to TFT-LCD array manufacturing yield improvement.	IJCAT	2007	DBLP DOI BibTeX RDF
1	Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Rung-Bin Lin	Double-via-driven standard cell library design.	DATE	2007	DBLP DOI BibTeX RDF
1	Jung Hwan Choi, Jayathi Murthy, Kaushik Roy	The effect of process variation on device temperature in FinFET circuits.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Payman Zarkesh-Ha, Ken Doniger	Stochastic interconnect layout sensitivity model.	SLIP	2007	DBLP DOI BibTeX RDF	critical area analysis, layout sensitivity, reliability, stochastic model, yield, design for manufacturability, defect density
1	H. J. Kadim	Predictive Analysis for Robust Operation with Applications to Autonomous Biosensors.	AHS	2007	DBLP DOI BibTeX RDF
1	Nicola Nicolici, Xiaoqing Wen	Embedded Tutorial on Low Power Test.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia	Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield.	IOLTS	2007	DBLP DOI BibTeX RDF
1	Ali Shahabi, Nima Honarmand, Zainalabedin Navabi	Programmable Routing Tables for Degradable Torus-Based Networks on Chips.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Chun-Lin Yang, Yuang-Cheng Hsiao, Shyue-Kung Lu	Efficient BISR Techniques for Embedded Memories Considering Cluster Faults.	PRDC	2007	DBLP DOI BibTeX RDF
1	Hendrik F. Hamann, Alan J. Weger, James A. Lacey, Zhigang Hu, Pradip Bose, Erwin Cohen, Jamil A. Wakil	Temperature-limited microprocessors: Measurements and design implications.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Zhaoliang Pan, Melvin A. Breuer	Estimating Error Rate in Defective Logic Using Signature Analysis.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Binning integrated circuits, effective yield, signature testing, error rate, error tolerance, yield loss
1	Dirk Müller	Optimizing yield in global routing.	ICCAD	2006	DBLP DOI BibTeX RDF	Steiner tree packing, multi-commodity flows, yield optimization, VLSI routing
1	Fei Su, Krishnendu Chakrabarty	Yield enhancement of reconfigurable microfluidics-based biochips using interstitial redundancy.	JETC	2006	DBLP DOI BibTeX RDF	space redundancy, reconfiguration, Microfluidics, yield enhancement
1	Mehdi Baradaran Tahoori	Application-independent defect tolerance of reconfigurable nanoarchitectures.	JETC	2006	DBLP DOI BibTeX RDF	reconfigurable architectures, nanotechnology, Defect tolerance
1	Jason A. Cheatham, John M. Emmert, Stanley Baumgart	A survey of fault tolerant methodologies for FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	fault tolerance, FPGA, self test
1	Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka	Adaptive Design for Performance-Optimized Robustness.	DFT	2006	DBLP DOI BibTeX RDF
1	Akhil Garg, Prashant Dubey	Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost.	DFT	2006	DBLP DOI BibTeX RDF	Compression and Yield, Memory, Repair, Fuse
1	Cristian Grecu, André Ivanov, Res Saleh, Partha Pratim Pande	NoC Interconnect Yield Improvement Using Crosspoint Redundancy.	DFT	2006	DBLP DOI BibTeX RDF
1	Pongstorn Maidee, Kia Bazargan	Defect-Tolerant FPGA Architecture Exploration.	FPL	2006	DBLP DOI BibTeX RDF
1	Puneet Gupta, Andrew B. Kahng, Chul-Hong Park, Kambiz Samadi, Xu Xu	Wafer Topography-Aware Optical Proximity Correction.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Shyue-Kung Lu, Yu-Chen Tsai, Chih-Hsien Hsu, Kuo-Hua Wang, Cheng-Wen Wu	Efficient built-in redundancy analysis for embedded memories with 2-D redundancy.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko	Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA redundancy, interconnect faults, fault tolerance, yield enhancement, interconnect model, yield prediction, catastrophic faults, FPGA interconnect
1	Thomas W. Williams	Design for Testability: The Path to Deep Submicron.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Fei Su, Krishnendu Chakrabarty, Vamsee K. Pamula	Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration.	DATE	2005	DBLP DOI BibTeX RDF
1	Jiang Brandon Liu, Andreas G. Veneris	Incremental fault diagnosis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Youngshin Han, Junghee Kim, Chilgee Lee	Automatic Detection of Failure Patterns Using Data Mining.	KES	2005	DBLP DOI BibTeX RDF
1	Donghoon Han, Abhijit Chatterjee	Device Resizing Based Optimization of Analog Circuits for Reduced Test Cost: Cost Metric and Case Study.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
1	Jing Huang, Mehdi Baradaran Tahoori, Fabrizio Lombardi	On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars.	DFT	2004	DBLP DOI BibTeX RDF
1	Xiaopeng Wang, Marco Ottavi, Fred J. Meyer, Fabrizio Lombardi	On The Yield of Compiler-Based eSRAMs.	DFT	2004	DBLP DOI BibTeX RDF
1	Kiyong Choi, David J. Allstot	Post-optimization design centering for RF integrated circuits.	ISCAS	2004	DBLP DOI BibTeX RDF
1	Shyue-Kung Lu, Shih-Chang Huang	Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs.	MTDT	2004	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Bao Liu, Ion I. Mandoiu	Nontree routing for reliability and yield improvement [IC layout].	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger	Exploiting Microarchitectural Redundancy For Defect Tolerance.	ICCD	2003	DBLP DOI BibTeX RDF
1	Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow	A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy.	ITC	2003	DBLP DOI BibTeX RDF	built-in redundancy-analysis, built-in self-test, memory testing, semiconductor memory, built-in self-repair
1	Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri	Optimal Spare Utilization in Repairable and Reliable Memory Cores.	MTDT	2003	DBLP DOI BibTeX RDF	Embedded Memory Repair and Reliability, Fault-Tolerant Memory Core, System-on-chip, Yield, Built-In-Self-Repair
1	Minsu Choi, Noh-Jin Park, K. M. George, Byoungjae Jin, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi	Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems. (PDF / PS)	NCA	2003	DBLP DOI BibTeX RDF	Built-in-self-repair (BISR), Field Reconfiguration, HW/SW Co-reliability, Reliability Assurance, Reliability, High performance computing, Yield, Massively parallel computing, Fault-tolerant memory, Modular Redundancy
1	Nicola Nicolici, Bashir M. Al-Hashimi	Power-Conscious Test Synthesis and Scheduling.	IEEE Design & Test of Computers	2003	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Bao Liu, Ion I. Mandoiu	Non-tree routing for reliability and yield improvement.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri	Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems. (PDF / PS)	DFT	2002	DBLP DOI BibTeX RDF
1	Nitin Agrarwal	Applications of generalized support vector machines to predictive modeling.	KDD	2001	DBLP DOI BibTeX RDF
1	Shi-Yu Huang	On Improving the Accuracy Of Multiple Defect Diagnosis.	VTS	2001	DBLP DOI BibTeX RDF
1	Jennifer Dworak, Jason D. Wicker, Sooryong Lee, Michael R. Grimaila, M. Ray Mercer, Kenneth M. Butler, Bret Stewart, Li-C. Wang	Defect-Oriented Testing and Defective-Part-Level Prediction.	IEEE Design & Test of Computers	2001	DBLP DOI BibTeX RDF
1	Masaru Sanada	Defect Detection from Visual Abnormalities in Manufacturing Process Using IDDQ.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	various current, visual abnormalities, fault diagnosis, manufacturing, I DDQ
1	N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang	When bad things happen to good chips (panel session).	DAC	2000	DBLP DOI BibTeX RDF
1	Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai	An Even Wiring Approach to the Ball Grid Array Package Routing.	ICCD	1999	DBLP DOI BibTeX RDF
1	Witold A. Pleskacz, Wojciech Maly	Improved Yield Model for Submicron Domain. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF
1	Donald Staab, Eugene R. Hnatek	Diagnosing IC Failures in a Fast Environment.	IEEE Design & Test of Computers	1997	DBLP DOI BibTeX RDF
1	Sy-Yen Kuo	YOR: a yield-optimizing routing algorithm by minimizing critical areas and vias.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
1	Sy-Yen Kuo, W. Kent Fuchs	Fault Diagnosis and Spare Allocation for Yield Enhancement in Large Reconfigurable PLA's.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	reconfigurable PLAs, spare allocation, circuit density, chip size, fault diagnosis algorithm, computational complexity, fault tolerant computing, fault location, programmable logic arrays, multiple faults, logic arrays, yield enhancement, reconfigurable logic, memory structures, circuit reliability, manufacturing yield
1	Kuochen Wang, Sy-Yen Kuo	Computer-aided modeling and evaluation of reconfigurable VLSI processor arrays with VHDL.	IEEE Trans. on CAD of Integrated Circuits and Systems	1992	DBLP DOI BibTeX RDF
1	Mingshien Wang, Michal Cutler, Stephen Y. H. Su	Reconfiguration of VLSI/WSI Mesh Array Processors with Two-Level Redundancy.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	distributed defects, VLSI/WSI mesh array processors, two-level redundancy, parallel rectangular, operation reliability, clustered defects, complexity, parallel processing, VLSI, fault tolerant computing, reconfiguration, processing elements, optimization technique, combinatorial analysis, manufacturing yield