Search results for "memory access"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Jungeun Kim, Taewhan Kim	Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design.	DAC	2005	DBLP DOI BibTeX RDF	scheduling, binding, memory access
3	Yichen Xie, Andy Chou, Dawson R. Engler	ARCHER: using symbolic, path-sensitive analysis to detect memory access errors.	ESEC / SIGSOFT FSE	2003	DBLP DOI BibTeX RDF	memory access errors, security, static analysis, error detection, buffer overflow, buffer overrun
3	Yingtao Jiang, Ting Zhou, Yiyan Tang, Yuke Wang	Twiddle-Factor-Based FFT Algorithm with Reduced Memory Access. (PDF / PS)	IPDPS	2002	DBLP DOI BibTeX RDF	Hoffman coding, twiddle factor, indexing, FFT, DSP, DFT, memory access
3	Stefan Manegold, Peter A. Boncz, Martin L. Kersten	Optimizing database architecture for the new bottleneck: memory access.	VLDB J.	2000	DBLP DOI BibTeX RDF	Memory access optimization, Decomposed storage model, Query processing, Main-memory databases, Join algorithms, Implementation techniques
3	Tai-Yi Huang, Jane W.-S. Liu, Jen-Yao Chung	Allowing cycle-stealing direct memory access I/O concurrent with hard-real-time programs. (PDF / PS)	ICPADS	1996	DBLP DOI BibTeX RDF	cycle-stealing direct memory access, I/O concurrent, hard-real-time programs, bus cycles, straight-line sequence, cycle-stealing operations, real-time systems, fault tolerant computing, worst-case execution time, schedulability analysis, file organisation
3	Mayez A. Al-Mouhamed	Analysis of Macro-Dataflow Dynamic Scheduling on Nonuniform Memory Access Architectures.	IEEE Trans. Parallel Distrib. Syst.	1993	DBLP DOI BibTeX RDF	macro-dataflow dynamic scheduling, nonuniform memory access architectures, computational tasks, least-communication, finish time, first-come first-served scheduling, scheduling, computational complexity, parallel programming, parallel architectures, time complexity, granularity, communication costs, data transfer, multiprocessing programs, scheduling heuristic
3	Narain H. Gehani	Capsules: A Shared Memory Access Mechanism for Concurrent C/C++.	IEEE Trans. Parallel Distrib. Syst.	1993	DBLP DOI BibTeX RDF	shared memory access mechanism, Concurrent C/C++, messagepassing, dataabstraction, Concurrent C compiler, parallel programming, parallel programming, message passing, inheritance, inheritance, synchronisation, shared memory multiprocessor, shared memory systems, parallel languages, class, shared data structures, capsule
3	Xiaodong Zhang, Xiaohan Qin	Performance Prediction and Evaluation of Parallel Processing on a NUMA Multiprocessor.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	nonuniform memory access, parallel processing performance, BBN GP1000, NUMA shared-memory multiprocessor, scheduling, performance evaluation, parallel processing, programming environment, multiprocessing systems, analytical models, interprocessor communication, process scheduling, network contention, process synchronization, memory contention, optimal strategies, remote memory access
3	Michel Dubois, Christoph Scheurich	Memory Access Dependencies in Shared-Memory Multiprocessors.	IEEE Trans. Software Eng.	1990	DBLP DOI BibTeX RDF	memory access dependencies, logical concurrency model, pipelining, multiprocessing systems, rules, shared-memory multiprocessors, multiprogramming, storage allocation, multiprocessor architectures, private caches
2	Byunghyun Jang, Dana Schaa, Perhaad Mistry, David R. Kaeli	Exploiting Memory Access Patterns to Improve Memory Performance in Data-Parallel Architectures.	IEEE Trans. Parallel Distrib. Syst.	2011	DBLP DOI BibTeX RDF	General-purpose computation on GPUs (GPGPUs), memory access pattern, memory selection, memory coalescing, data-parallel architectures, vectorization, data parallelism, memory optimization, GPU computing
2	Jan Staschulat, Marco Bekooij	Dataflow models for shared memory access latency analysis.	EMSOFT	2009	DBLP DOI BibTeX RDF	multiprocessor performance analysis, real-time, memory accesses, dataflow model
2	Zhibin Fang, Xian-He Sun, Yong Chen, Surendra Byna	Core-aware memory access scheduling schemes.	IPDPS	2009	DBLP DOI BibTeX RDF
2	Marc-André Hermanns, Markus Geimer, Bernd Mohr, Felix Wolf	Scalable Detection of MPI-2 Remote Memory Access Inefficiency Patterns.	PVM/MPI	2009	DBLP DOI BibTeX RDF	mpi-2, scalability, performance analysis, pattern search, remote memory access
2	Harmen L. A. van der Spek, Erwin M. Bakker, Harry A. G. Wijshoff	Characterizing the performance penalties induced by irregular code using pointer structures and indirection arrays on the intel core 2 architecture.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	spark00, benchmarking, memory access, irregularity
2	Guru Venkataramani, Ioannis Doudalis, Yan Solihin, Milos Prvulovic	MemTracker: An accelerator for memory debugging and monitoring.	TACO	2009	DBLP DOI BibTeX RDF	memory access monitoring, debugging, Accelerator
2	Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet	Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto	HyMacs: hybrid memory access optimization based on custom-instruction scheduling.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	asip, cad algorithm, hardware/software co-design
2	Woo-Cheol Kwon, Sungjoo Yoo, Sung-Min Hong, Byeong Min, Kyu-Myung Choi, Soo-Kwan Eo	A practical approach of memory access parallelization to exploit multiple off-chip DDR memories.	DAC	2008	DBLP DOI BibTeX RDF	parallelization, memory, arbitration
2	Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu	Memory Access Scheduling Schemes for Systems with Multi-Core Processors.	ICPP	2008	DBLP DOI BibTeX RDF
2	Guofu Feng, Xiaoshe Dong, Siyuan Ma, Jinghua Feng, Xuhao Wang	A Profile-based Memory Access Optimizing Technology on CBE Architecture.	HPCC	2008	DBLP DOI BibTeX RDF
2	E. Yuan, Yunquan Zhang, Xiangzheng Sun	Memory Access Complexity Analysis of SpMV in RAM (h) Model.	HPCC	2008	DBLP DOI BibTeX RDF
2	Liesbeth Steffens, Manvi Agarwal, Pieter van der Wolf	Real-Time Analysis for Memory Access in Media Processing SoCs: A Practical Approach.	ECRTS	2008	DBLP DOI BibTeX RDF
2	Lixia Liu, Zhiyuan Li, Ahmed H. Sameh	Analyzing memory access intensity in parallel programs on multicore.	ICS	2008	DBLP DOI BibTeX RDF	parallel, multicore, linear system, memory bandwidth, intensity
2	Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon	Speculative DMA for architecturally visible storage in instruction set extensions.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	architecturally visible storage, speculative direct memory access, instruction set extensions, application-specific processors
2	Chunhui Zhang, Fadi J. Kurdahi	Reducing Off-Chip Memory Access via Stream-Conscious Tiling on Multimedia Applications.	International Journal of Parallel Programming	2007	DBLP DOI BibTeX RDF	low power, DSP, memory hierarchy, tiling, data locality, iteration space
2	Taewhan Kim, Jungeun Kim	Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory-Access Optimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Sze-Wei Lee, Soon-Chieh Lim	An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	2-D DWT processing systems, memory mapping scheme, memeory access, memory bandwidth
2	Yong Ho Moon	A New Coeff-Token Decoding Method With Efficient Memory Access in H.264/AVC Video Coding Standard.	IEEE Trans. Circuits Syst. Video Techn.	2007	DBLP DOI BibTeX RDF
2	Christof Pitter, Martin Schoeberl	Time Predictable CPU and DMA Shared Memory Access.	FPL	2007	DBLP DOI BibTeX RDF
2	Miguel Peón Quirós, Alexandros Bartzas, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris	Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption.	PATMOS	2007	DBLP DOI BibTeX RDF
2	Jung-Yang Kao	Method for Decreasing Computation Load and Memory Access Frequency during Interpolation for Video Coding.	SiPS	2007	DBLP DOI BibTeX RDF
2	Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan	Low Computation and Memory Access for Variable Block Size Motion Estimation Using Pixel Truncation.	SiPS	2007	DBLP DOI BibTeX RDF
2	Michael Gerndt, Edmond Kereku	Automatic Memory Access Analysis with Periscope.	International Conference on Computational Science	2007	DBLP DOI BibTeX RDF	program tuning, memory accesses analysis, Performance analysis, supercomputers
2	Vinod Tipparaju, Andriy Kot, Jarek Nieplocha, Monika ten Bruggencate, Nikos Chrisochoides	Evaluation of Remote Memory Access Communication on the Cray XT3.	IPDPS	2007	DBLP DOI BibTeX RDF
2	Onur Mutlu, Thomas Moscibroda	Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors.	MICRO	2007	DBLP DOI BibTeX RDF
2	Hakduran Koc, Mahmut T. Kandemir, Ehat Ercanli, Ozcan Ozturk	Reducing Off-Chip Memory Access Costs Using Data Recomputation in Embedded Chip Multi-processors.	DAC	2007	DBLP DOI BibTeX RDF
2	Tsun-Hsien Wang, Ching-Te Chiu	Low Power Design of High Performance Memory Access Architecture for HDTV Decoder.	ICME	2007	DBLP DOI BibTeX RDF
2	Hyojin Choi, Wonchul Lee, Wonyong Sung	Memory Access Reduced Software Implementation of H.264/AVC Sub-pixel Motion Estimation Using Differential Data Encoding.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Tomas Henriksson, Pieter van der Wolf, Axel Jantsch, Alistair C. Bruce	Network Calculus Applied to Verification of Memory Access Performance in SoCs.	ESTImedia	2007	DBLP DOI BibTeX RDF
2	Guru Venkataramani, Brandyn Roemer, Yan Solihin, Milos Prvulovic	MemTracker: Efficient and Programmable Support for Memory Access Monitoring and Debugging.	HPCA	2007	DBLP DOI BibTeX RDF
2	Dae Wan Cho, Hyeon Soo Kim, Seunguk Oh	A new approach to detecting memory access errors in C programs.	ACIS-ICIS	2007	DBLP DOI BibTeX RDF	bitmap coloring, software testing, code instrumentation, memory error
2	Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad H. Hammoud, Rami G. Melhem	CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	high-performance search accelerator, high-performance memory substrate, search-intensive application, content addressable random access memory, search operation, memory hierarchy concept, direct hardware implementation, parallel key matching operation, hash function, memory access, application-specific processor, memory structure, hashing technique
2	Xudong Shi, Feiqi Su, Jih-Kwon Peir, Ye Xia 0001, Zhen Yang	Modeling and Single-Pass Simulation of CMP Cache Capacity and Accessibility.	ISPASS	2007	DBLP DOI BibTeX RDF	multiple cache organization, single-pass simulation, on-chip storage space, on-chip cache capacity, single-pass stack simulation, global stack, shared stack, per-core private stack, single simulation pass, average memory access time, chip-multiprocessor, data replication, data accessibility, abstract model, reuse distances
2	Girish Venkataramani, Tobias Bjerregaard, Tiberiu Chelcea, Seth Copen Goldstein	Hardware compilation of application-specific memory-access interconnect.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Philippe Clauss, Bénédicte Kenmei	Polyhedral Modeling and Analysis of Memory Access Profiles.	ASAP	2006	DBLP DOI BibTeX RDF
2	Guang-Huei Lin, Sao-Jie Chen, R. B. Lee, Yu Hen Hu	Memory Access Optimization of Motion Estimation Algorithms on a Native SIMD PLX Processor.	APCCAS	2006	DBLP DOI BibTeX RDF
2	Sofien Chtourou, Mohamed Chtourou, Omar Hammami	Neural Network Based Memory Access Prediction Support for SoC Dynamic Reconfiguration.	IJCNN	2006	DBLP DOI BibTeX RDF
2	Dag Arne Osvik, Adi Shamir, Eran Tromer	Cache Attacks and Countermeasures: The Case of AES.	CT-RSA	2006	DBLP DOI BibTeX RDF	cache, cryptanalysis, AES, side-channel attack, memory access
2	Jarno K. Tanskanen, Reiner Creutzburg, Jarkko Niittylahti	On Design of Parallel Memory Access Schemes for Video Coding.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	parallel memory access, SIMD memory architecture, video coding, MPEG-4, H.263, subword parallelism, conflict-free access, storage scheme, skewing scheme, data alignment
2	Yanwei Niu, Ziang Hu, Kenneth E. Barner, Guang R. Gao	Performance Modelling and Optimization of Memory Access on Cellular Computer Architecture Cyclops64.	NPC	2005	DBLP DOI BibTeX RDF
2	Jarek Nieplocha, Doug Baxter, Vinod Tipparaju, Craig Edward Rasmussen, Robert W. Numrich	Symmetric Data Objects and Remote Memory Access Communication for Fortran-95 Applications.	Euro-Par	2005	DBLP DOI BibTeX RDF
2	Jonathan Weinberg, Michael O. McCracken, Erich Strohmaier, Allan Snavely	Quantifying Locality In The Memory Access Patterns of HPC Applications.	SC	2005	DBLP DOI BibTeX RDF
2	Michael Gerndt, Tianchao Li	Automated Analysis of Memory Access Behavior.	IPDPS	2005	DBLP DOI BibTeX RDF
2	Kostas Magoutis	Memory Management Support for Multi-Programmed Remote Direct Memory Access (RDMA) Systems.	CLUSTER	2005	DBLP DOI BibTeX RDF
2	Yimin Xia, Jun Luo, Minxuan Zhang	Detecting Memory Access Errors with Flow-Sensitive Conditional Range Analysis.	ICESS	2005	DBLP DOI BibTeX RDF
2	Mehrdad Reshadi, Prabhat Mishra	Memory access optimizations in instruction-set simulators.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	memory address-space mapping, instruction-set simulator
2	Cheong-Ghil Kim, Dae-Young Jeong, Byung-Gil Kim, Shin-Dug Kim	Reconfigurable Microarchitecture Based System-Level Dynamic Power Management SoC Platform.	ICESS	2005	DBLP DOI BibTeX RDF	quarter-pel interpolation, multimedia SoC, low-power, system architecture, H.264/AVC, motion compensation, memory access
2	Christopher C. Aycock	MPI Ruby with Remote Memory Access.	HPDC	2004	DBLP DOI BibTeX RDF
2	Qiang Wu, Artem Pyatakov, Alexey Spiridonov, Easwaran Raman, Douglas W. Clark, David I. August	Exposing Memory Access Regularities Using Object-Relative Memory Profiling.	CGO	2004	DBLP DOI BibTeX RDF
2	Vinod Tipparaju, Gopalakrishnan Santhanaraman, Jarek Nieplocha, Dhabaleswar K. Panda	Host-Assisted Zero-Copy Remote Memory Access Communication on InfiniBand.	IPDPS	2004	DBLP DOI BibTeX RDF
2	Chun-Gi Lyuh, Taewhan Kim	Memory access scheduling and binding considering energy minimization in multi-bank memory systems.	DAC	2004	DBLP DOI BibTeX RDF	scheduling, binding, low energy design
2	Surendra Byna, Xian-He Sun, William Gropp, Rajeev Thakur	Predicting memory-access cost based on data-access patterns.	CLUSTER	2004	DBLP DOI BibTeX RDF
2	Gang Shi, Mingchang Hu, Hongda Yin, Weiwu Hu, Zhimin Tang	A shared virtual memory network with fast remote direct memory access and message passing.	CLUSTER	2004	DBLP DOI BibTeX RDF
2	Motohiro Kawahito, Hideaki Komatsu, Toshio Nakatani	Instruction combining for coalescing memory accesses using global code motion.	Memory System Performance	2004	DBLP DOI BibTeX RDF	instruction combining, memory access coalescing, Java, JIT compilers, IA-64, 64-bit architectures
2	Laxmi N. Bhuyan, Hu-Jun Wang	Switch MSHR: A Technique to Reduce Remote Read Memory Access Time in CC-NUMA Multiprocessors.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	CC-NUMA multiprocessor, memory latency problem, miss status holding register, interconnection network, execution-driven simulation
2	Vinod Tipparaju, Manojkumar Krishnan, Jarek Nieplocha, Gopalakrishnan Santhanaraman, Dhabaleswar K. Panda	Exploiting Non-blocking Remote Memory Access Communication in Scientific Benchmarks.	HiPC	2003	DBLP DOI BibTeX RDF
2	Pramod Ramarao, Akhilesh Tyagi, Gyungho Lee	Run-Time Support for Detection of Memory Access Violations to Prevent Buffer Overflow Exploits.	ISC	2003	DBLP DOI BibTeX RDF
2	Shinji Sumimoto, Kouichi Kumon	PM/Ehernet-kRMA: A High Performance Remote Memory Access Facility Using Multiple Gigabit Ethernet Cards.	CCGRID	2003	DBLP DOI BibTeX RDF
2	Vinod Tipparaju, Jarek Nieplocha, Dhabaleswar K. Panda	Fast Collective Operations Using Shared and Remote Memory Access Protocols on Clusters.	IPDPS	2003	DBLP DOI BibTeX RDF
2	Jarek Nieplocha, Vinod Tipparaju, Manojkumar Krishnan, Gopalakrishnan Santhanaraman, Dhabaleswar K. Panda	Optimizing Mechanisms for Latency Tolerance in Remote Memory Access Communication on Clusters.	CLUSTER	2003	DBLP DOI BibTeX RDF
2	Surendra Byna, William D. Gropp, Xian-He Sun, Rajeev Thakur	Improving the Performance of MPI Derived Datatypes by Optimizing Memory-Access Cost.	CLUSTER	2003	DBLP DOI BibTeX RDF
2	Keqiang Wu, Resit Sendag, David J. Lilja	Exploring Memory Access Regularity in Pointer-Intensive Application Programs.	IDEAL	2003	DBLP DOI BibTeX RDF
2	Alberto Macii, Enrico Macii, Massimo Poncino	Increasing the locality of memory access patterns by low-overhead hardware address relocation.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Youhui Zhang, Weimin Zheng	User-level communication based cooperative caching.	Operating Systems Review	2003	DBLP DOI BibTeX RDF	Remote Direct Memory Access, cooperative caching, user-level communication
2	Won Woo Ro, Jean-Luc Gaudiot, Stephen P. Crago, Alvin M. Despain	HiDISC: A Decoupled Architecture for Data-Intensive Application.	IPDPS	2003	DBLP DOI BibTeX RDF	Memory access latency and Speculative pre-execution, Data prefetching, Data-intensive applications, Decoupled architecture
2	Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Minimizing memory access energy in embedded systems by selective instruction compression.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
2	Chi-Hung Chi, Jun-Li Yuan	Runtime Association of Software Prefetch Control to Memory Access Instructions (Research Note).	Euro-Par	2002	DBLP DOI BibTeX RDF
2	Jie Tao, Martin Schulz, Wolfgang Karl	Improving Data Locality Using Dynamic Page Migration Based on Memory Access Histograms.	International Conference on Computational Science	2002	DBLP DOI BibTeX RDF
2	Dimitrios S. Nikolopoulos	Quantifying and Resolving Remote Memory Access Contention on Hardware DSM Multiprocessors. (PDF / PS)	IPDPS	2002	DBLP DOI BibTeX RDF
2	Yunheung Paek, Jay Hoeflinger, David A. Padua	Efficient and precise array access analysis.	ACM Trans. Program. Lang. Syst.	2002	DBLP DOI BibTeX RDF	Array access analysis, linear memory access descriptors, internal representation
2	Stefan Manegold, Peter A. Boncz, Martin L. Kersten	Optimizing Main-Memory Join on Modern Hardware.	IEEE Trans. Knowl. Data Eng.	2002	DBLP DOI BibTeX RDF	memory access optimization, decomposed storage model, query processing, Main-memory databases, join algorithms, implementation techniques
2	Sung-Ming Yen, Sang-Jae Moon, JaeCheol Ha	Hardware Fault Attackon RSA with CRT Revisited.	ICISC	2002	DBLP DOI BibTeX RDF	Computational fault, Memory access fault, Cryptography, Side channel attack, Factorization, Chinese remainder theorem (CRT), Transient fault, Permanent fault, Physical cryptanalysis, Hardware fault cryptanalysis
2	Donglok Kim, Ravi Managuli, Yongmin Kim	Data Cache and Direct Memory Access in Programming Mediaprocessors.	IEEE Micro	2001	DBLP DOI BibTeX RDF
2	Zhao Zhang, Zhichun Zhu, Xiaodong Zhang	Cached DRAM for ILP Processor Memory Access Latency Reduction.	IEEE Micro	2001	DBLP DOI BibTeX RDF
2	Nai-Yin Sung, Tsung-Yi Wu	A Method of Embedded Memory Access Time Measurement.	ISQED	2001	DBLP DOI BibTeX RDF
2	Jie Tao, Wolfgang Karl, Martin Schulz	Visualizing the Memory Access Behavior of Shared Memory Applications on NUMA Architectures.	International Conference on Computational Science	2001	DBLP DOI BibTeX RDF
2	David A. Bader, Ajith K. Illendula, Bernard M. E. Moret, Nina R. Weisse-Bernstein	Using PRAM Algorithms on a Uniform-Memory-Access Shared-Memory Architecture.	Algorithm Engineering	2001	DBLP DOI BibTeX RDF
2	Francky Catthoor, Nikil D. Dutt, Christoforos E. Kozyrakis	How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level?	DATE	2000	DBLP DOI BibTeX RDF
2	Thomas Gleerup, Hans Holten-Lund, Jan Madsen, Steen Pedersen	Memory architecture for efficient utilization of SDRAM: a case study of the computation/memory access trade-off.	CODES	2000	DBLP DOI BibTeX RDF	case study, memory architecture, 3D graphics
2	Hua Lin, Wayne Wolf	Co-design of interleaved memory systems.	CODES	2000	DBLP DOI BibTeX RDF	data access locality, extracted data stream, in-dimension-stride vector, interleaved memory systems, memory access conflict, optimally reordered access
2	Sally A. McKee, William A. Wulf, James H. Aylor, Robert H. Klenke, Maximo H. Salinas, Sung I. Hong, Dee A. B. Weikle	Dynamic Access Ordering for Streamed Computations.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Memory systems architecture, memory access ordering, memory access scheduling, memory bandwidth, memory latency
2	B. Grayson, L. John, C. Chase	The effects of memory-access ordering on multiple-issue uniprocessor performance.	IPCCC	1999	DBLP DOI BibTeX RDF
2	Ravi R. Iyer, Laxmi N. Bhuyan	Switch Cache: A Framework for Improving the Remote Memory Access Latency of CC-NUMA Multiprocessors.	HPCA	1999	DBLP DOI BibTeX RDF
2	Mark Harman, Yoga Sivagurunathan, Sebastian Danicic	Analysis of Dynamic Memory Access Using Amorphous Slicing. (PDF / PS)	ICSM	1998	DBLP DOI BibTeX RDF
2	Tao Yang, Cong Fu	Space/Time-Efficient Scheduling and Execution of Parallel Irregular Computations.	ACM Trans. Program. Lang. Syst.	1998	DBLP DOI BibTeX RDF	direct remote memory access, irregular parallelism, run-time support, DAG scheduling
2	Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau	Exploiting off-chip memory access modes in high-level synthesis.	ICCAD	1997	DBLP DOI BibTeX RDF	High Level Synthesis, DRAM, Memory Synthesis
2	Gary S. Tyson, Todd M. Austin	Improving the Accuracy and Performance of Memory Communication Through Renaming.	MICRO	1997	DBLP BibTeX RDF	data fetching, data value speculation, heap segment, instruction loading, memory access latency, memory communication, memory references, memory renaming, memory segments, processor pipeline, register access techniques, stores, performance, delays, accuracy, instruction-level parallelism, execution time, storage allocation, data dependence speculation, address calculation
2	Ashoke Deb	Multiskewing-A Novel Technique for Optimal Parallel Memory Access.	IEEE Trans. Parallel Distrib. Syst.	1996	DBLP DOI BibTeX RDF	pipelined/vector processors, linear schemes, memory bank conflict, memory bandwidth, periodic, matrix computation, conflict-free access, Interleaved memory, skewing schemes
2	Luddy Harrison	Examination of a Memory Access Classification Scheme for Pointer-Intensive and Numeric Programs.	International Conference on Supercomputing	1996	DBLP DOI BibTeX RDF	CPU architecture, instruction profiling, memory access pattern classification, memory latency tolerance, data cache
2	Matthias A. Blumrich, Cezary Dubnicki, Edward W. Felten, Kai Li	Protected, User-Level DMA for the SHRIMP Network Interface.	HPCA	1996	DBLP DOI BibTeX RDF	SHRIMP network interface, User-level Direct Memory Access, DMA transfers, permission checking, virtual memory translation, operating system, computer networks, file organisation, network interfaces, DMA, address translation, computer interfaces