Search results for "memory architecture"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Minming Li, Chun Jason Xue, Tiantian Liu, Yingchao Zhao	Analysis and approximation for bank selection instruction minimization on partitioned memory architecture.	LCTES	2010	DBLP DOI BibTeX RDF	bank selection instruction minimization, partitioned memory architecture
3	Ralf Laue 0002, Sorin A. Huss	Parallel Memory Architecture for Elliptic Curve Cryptography over GF(p) Aimed at Efficient FPGA Implementation.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	FPGA, parallelization, elliptic curve cryptography, memory architecture
3	Håkan Zeffer, Zoran Radovic, Martin Karlsson, Erik Hagersten	TMA: a trap-based memory architecture.	ICS	2006	DBLP DOI BibTeX RDF	distributed shared memory (DSM), low complexity server design, node coherence checks, server design, simultaneous multi-threading (SMT), software coherence, trap-based memory architecture (TMA), chip multi processor (CMP)
3	Kentaro Sano, Chiaki Takagi, Ryusuke Egawa, Ken-ichi Suzuki, Tadao Nakamura	A Systolic Memory Architecture for Fast Codebook Design based on MMPDCL Algorithm.	ITCC	2004	DBLP DOI BibTeX RDF	systolic memory architecture, codebook design, MMPDCL algorithm, vector quantization
3	Chanik Park, Jaeyu Seo, Sunghwan Bae, Hyojun Kim, Shinhan Kim, Bumsoo Kim	A low-cost memory architecture with NAND XIP for mobile embedded systems.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	NAND XIP, priority-based caching, memory architecture
3	Thomas Gleerup, Hans Holten-Lund, Jan Madsen, Steen Pedersen	Memory architecture for efficient utilization of SDRAM: a case study of the computation/memory access trade-off.	CODES	2000	DBLP DOI BibTeX RDF	case study, memory architecture, 3D graphics
3	Gab Joong Jeong, Kyoung Hwan Kwon, Moon Key Lee, Seung Han An	A Scalable Memory System Design.	VLSI Design	1997	DBLP DOI BibTeX RDF	scalable memory system, pipeline technique, systolic data flow, sub-memory blocks, partial binary tree structure, multidirectional data flow, chip size, 4 kbit, 0.8 micron, 5.1 ns, 3.5 mm, throughput, latency, memory architecture, memory architecture, CMOS technology, communication channel, access time, operating speed, clock speed
3	Santanu Dutta, Wayne Wolf, Andrew Wolfe	VLSI issues in memory-system design for video signal processors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	VLSI issues, video signal processors, memory-system architectures, circuit-level issues, register-cache based hierarchy, general-purpose programmable microprocessors, VLSI, system architecture, utilization, memory architecture, memory architecture, video signal processing, area, cycle time, memory-system design
3	Wolfgang K. Giloi, C. Hastedt, Friedrich Schön, Wolfgang Schröder-Preikschat	A Distributed Implementation of Shared Virtual Memory with Strong and Weak Coherence.	EDMCC	1991	DBLP DOI BibTeX RDF	virtual shared memory architecture, strong and weak data coherence, communication hardware, parallelizing compilers, Distributed memory architecture
2	Baris Taskin, Andy Chiu, Jonathan Salkind, Daniel Venutolo	A shift-register-based QCA memory architecture.	JETC	2009	DBLP DOI BibTeX RDF	clocking, Quantum-dot cellular automata, memory design
2	Zhongbo Cao, Ramon Mercado, Diane T. Rover	System-level memory modeling for bus-based memory architecture exploration.	EIT	2009	DBLP DOI BibTeX RDF
2	Erick Amador, Renaud Pacalet, Vincent Rezard	Optimum LDPC decoder: a memory architecture problem.	DAC	2009	DBLP DOI BibTeX RDF	memory optimization, LDPC codes, low power architectures
2	Daisaku Seto, Minoru Watanabe	An 11, 424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Norma Alias, Roziha Darwis, Noriza Satam, Mohamed Othman	Parallelization of Temperature Distribution Simulations for Semiconductor and Polymer Composite Material on Distributed Memory Architecture.	PaCT	2009	DBLP DOI BibTeX RDF	Red-Black Gauss Seidel (RBGS), Parallel Performance evaluations, Parallel Virtual Machine (PVM)
2	Rangyu Deng, Weixia Xu, Qiang Dou, Hongwei Zhou, Zefu Dai, Haiyan Chen	An efficient stream memory architecture for heterogeneous multicore processor.	ISCC	2009	DBLP DOI BibTeX RDF
2	Sintiani Dewi Teddy, Chai Quek, Edmund Ming-Kit Lai	PSECMAC: A Novel Self-Organizing Multiresolution Associative Memory Architecture.	IEEE Transactions on Neural Networks	2008	DBLP DOI BibTeX RDF
2	Yong Ho Moon	An Advanced Total_Zeros Decoding Method Based on New Memory Architecture in H.264/AVC CAVLC.	IEEE Trans. Circuits Syst. Video Techn.	2008	DBLP DOI BibTeX RDF
2	T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan	Memory Architecture Exploration Framework for Cache Based Embedded SOC.	VLSI Design	2008	DBLP DOI BibTeX RDF
2	Caixia Liu, Jiaxin Li, Hongli Zhang, Qi Zuo	HHMA: A Hierarchical Hybrid Memory Architecture Sharing Multi-Port Memory.	ICYCS	2008	DBLP DOI BibTeX RDF
2	Vamsi Vankamamidi, Marco Ottavi, Fabrizio Lombardi	A Serial Memory by Quantum-Dot Cellular Automata (QCA).	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	memory architecture, emerging technologies, QCA
2	Wei Wang, Qigang Wang, Wei Wei, Dong Liu	Evaluating Heterogeneous Memory Model by Realistic Trace-Driven Hardware/Software Co-simulation.	Euro-Par	2008	DBLP DOI BibTeX RDF	Performance model, Memory architecture, Trace-driven simulation
2	T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan	MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip.	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Ryan Riley, Xuxian Jiang, Dongyan Xu	An Architectural Approach to Preventing Code Injection Attacks.	DSN	2007	DBLP DOI BibTeX RDF	Secure Memory Architecture, Code Injection
2	Mauricio Alvarez, Esther Salamí, Alex Ramírez, Mateo Valero	Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	auto vectorizing compiler, unaligned memory operations, SIMD extensions, video codec applications, unaligned memory accesses, H.264/AVC media codec, memory architecture, data level parallelism
2	Mohammed Sayed, Wael M. Badawy	A Computational Memory Architecture for MPEG-4 Applications with Mobile Devices.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	computational memory, motion estimation, MPEG-4
2	Sébastien Lafond, Johan Lilius	Static Energy Saving Through Multi-Bank Memory Architecture.	ICSAMOS	2006	DBLP DOI BibTeX RDF
2	Ali R. Iranpour, Krzysztof Kuchcinski	Memory Architecture Evaluation for Video Encoding on Enhanced Embedded Processors.	SAMOS	2006	DBLP DOI BibTeX RDF
2	Hanene Ben Fradj, Cécile Belleudy, Michel Auguin	Multi-Bank Main Memory Architecture with Dynamic Voltage Frequency Scaling for System Energy Optimization.	DSD	2006	DBLP DOI BibTeX RDF
2	Bernhard Scholz, Bernd Burgstaller, Jingling Xue	Minimizing bank selection instructions for partitioned memory architecture.	CASES	2006	DBLP DOI BibTeX RDF	PBQP, RAM allocation, bank-switching, partitioned memory architecture, compiler optimization, microcontrollers
2	Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi, Tetsushi Koide, Hans Jürgen Mattausch	Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search.	APCCAS	2006	DBLP DOI BibTeX RDF
2	Hiroki Sugano, Hiroshi Tsutsui, Takahiko Masuzaki, Takao Onoye, Hiroyuki Ochi, Yukihiro Nakamura	Efficient memory architecture for JPEG2000 entropy codec.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Bruno Bougard, M. Rullmann, Erik Brockmeyer, Liesbet Van der Perre, Francky Catthoor, Wim Dehaene	Energy Efficient Memory Architecture for High Speed Decoding of Block Turbo-Codes with the Fang-Buda Algorithm.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	Block Turbo Codes, low power, VLSI architecture, high throughput
2	Josef Kittler, William J. Christmas, Alexey Kostin, Fei Yan, Ilias Kolonias, David Windridge	A Memory Architecture and Contextual Reasoning Framework for Cognitive Vision.	SCIA	2005	DBLP DOI BibTeX RDF
2	Francesco Poletti, Antonio Poggiali, Paul Marchal	Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory Architecture.	DATE	2005	DBLP DOI BibTeX RDF
2	Nelson Yen-Chung Chang, Tian-Sheuan Chang	Combined frame memory architecture for motion compensation in video decoding.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Amit Kumar Gupta, Saeid Nooshabadi, David S. Taubman	Optimal 2 sub-bank memory architecture for bit plane coder of JPEG2000.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Justin Teller, Charles B. Silio Jr., Bruce L. Jacob	Performance characteristics of MAUI: an intelligent memory system architecture.	Memory System Performance	2005	DBLP DOI BibTeX RDF	MAUI memory architecture, SimpleScalar simulator, data-intensive calculations, intelligent memory, memory architecture, vector processing, SIMD processing
2	Vamsi Vankamamidi, Marco Ottavi, Fabrizio Lombardi	Tile-based design of a serial memory in QCA.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	quantum computing, memory architecture, emerging technologies, QCA
2	Jarno K. Tanskanen, Reiner Creutzburg, Jarkko Niittylahti	On Design of Parallel Memory Access Schemes for Video Coding.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	parallel memory access, SIMD memory architecture, video coding, MPEG-4, H.263, subword parallelism, conflict-free access, storage scheme, skewing scheme, data alignment
2	Jarno K. Tanskanen, Tero Sihvo, Jarkko Niittylahti	Byte and modulo addressable parallel memory architecture for video coding.	IEEE Trans. Circuits Syst. Video Techn.	2004	DBLP DOI BibTeX RDF
2	Manoranjan Dash, Simona Petrutiu, Peter Scheuermann	Efficient Parallel Hierarchical Clustering.	Euro-Par	2004	DBLP DOI BibTeX RDF	parallel algorithm, partitioning, hierarchical agglomerative clustering, shared memory architecture
2	Stefanos Kaxiras, Georgios Keramidas	IPStash: a Power-Efficient Memory Architecture for IP-lookup.	MICRO	2003	DBLP DOI BibTeX RDF	IP
2	Urs Kanus, Gregor Wetekam, Johannes Hirche	VoxelCache: a cache-based memory architecture for volume graphics.	Graphics Hardware	2003	DBLP DOI BibTeX RDF
2	Xiaoling Sun, Bruce F. Cockburn, Duncan G. Elliott	An Efficient Functional Test for the Massively-Parallel C ?RAM Logic-Enhanced Memory Architecture.	DFT	2003	DBLP DOI BibTeX RDF
2	A. Durga Kishore, S. Srinivasan	A Distributed Memory Architecture for Morphological Image Processing.	ITCC	2003	DBLP DOI BibTeX RDF
2	Chanik Park, Jaeyu Seo, Dongyoung Seo, Shinhan Kim, Bumsoo Kim	Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems.	ICCD	2003	DBLP DOI BibTeX RDF
2	Basilio B. Fraguela, Jose Renau, Paul Feautrier, David A. Padua, Josep Torrellas	Programming the FlexRAM parallel intelligent memory system.	PPOPP	2003	DBLP DOI BibTeX RDF	compiler directives, intelligent memory architecture, programming heterogeneous computers, parallel languages
2	Jarno Vanne, Eero Aho, Kimmo Kuusilinna, Timo D. Hämäläinen	Enhanced Configurable Parallel Memory Architecture.	DSD	2002	DBLP DOI BibTeX RDF
2	Yan Solihin, Jaejin Lee, Josep Torrellas	Automatic Code Mapping on an Intelligent Memory Architecture.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Intelligent memory architecture, compilers, performance prediction, heterogeneous system, processing-in-memory, adaptive execution
2	Sunho Chang, Jong-Sun Kim, Lee-Sup Kim	A Memory Architecture with 4-Address Configurations for Video Signal Processing.	DATE	2000	DBLP DOI BibTeX RDF
2	Takashi Matsuyama, Shinsaku Hiura, Toshikazu Wada, K. Murase, A. Yoshioka	Dynamic Memory: Architecture for Real Time Integration of Visual Perception, Camera Action, and Network Communication. (PDF / PS)	CVPR	2000	DBLP DOI BibTeX RDF
2	Pere Marès Martí, Antonio B. Martínez Velasco	Memory Architecture for Parallel Line Drawing Based on Non Incremental Algorithm.	EUROMICRO	2000	DBLP DOI BibTeX RDF
2	Chi-Min Lin, Tien-Fu Chen	Dynamic memory management for real-time embedded Java chips.	RTCSA	2000	DBLP DOI BibTeX RDF	storage management chips, dynamic runtime memory management, real-time embedded Java chips, CPU design, hardware-assisted scheme, dynamic garbage collection mechanism, predictable memory allocation time, data transition events, circular heap, simulation, Java, embedded systems, response time, memory architecture, memory architecture, storage allocation, coprocessors, resource constraints, real-time constraints, co-processor
2	David Crawley	A Multilevel Cache Memory Architecture for Nanoelectronics.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
2	Koji Matsuda, Kang G. Shin	Applicability of Cyclic-Memory Networks and IEEE1394 for Fine Motion Control and Arcade Games.	RTCSA	1999	DBLP DOI BibTeX RDF	arcade games, Cyclic Memory, IEEE1394, Isochronous mode, common-memory architecture, Motion control
2	Tadeusz J. Janik	Parallel implementation of the p-version of the finite element method for elliptic equations on a shared-memory architecture.	Adv. Comput. Math.	1998	DBLP DOI BibTeX RDF	numerical methods for PDEs, load-balance, speedup, 65N30, parallel implementation, shared-memory architecture, finite element approximation, 65Y05
2	David Parry	Scalability in computing for today and tomorrow.	ARVLSI	1997	DBLP DOI BibTeX RDF	synergistic combination, performance growth, current multiprocessor alternatives, scalable SMP, Silicon Graphics Origin multiprocessor, S/sup 2/MP memory architecture, core technologies, scalability, system architecture, shared-memory multiprocessors, shared memory systems
2	Jinseok Kong, Gyungho Lee	Relaxing the Inclusion Property in Cache Only Memory Architecture.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF
2	Wolfgang K. Giloi, Ulrich Brüning, Wolfgang Schröder-Preikschat	MANNA: Prototype of a Distributed Memory Architecture with Maximized Sustained Performance.	PDP	1996	DBLP DOI BibTeX RDF	maximized sustained performance, compiler problem, innovative architectural solutions, overlapping communication, MANNA computer, benchmark performance, performance evaluation, parallel computers, operating system, parallel machines, distributed memory systems, parallelizing compilers, operating systems (computers), programmability, virtual storage, parallelising compilers, latency hiding, distributed memory parallel computer, distributed memory architecture, virtual shared memory, global address space, superscalar microprocessors
2	Anders Landin, Fredrik Dahlgren	Bus-Based COMA - Reducing Traffic in Shared-Bus Multiprocessors.	HPCA	1996	DBLP DOI BibTeX RDF	bus-based COMA, standard UMA architecture, program-driven simulation, SPLASH, cache only memory architecture, shared-memory multiprocessors, shared memory systems, memory architecture, cache storage, shared-bus multiprocessors
2	Henk L. Muller, Paul W. A. Stallard, David H. D. Warren	The Role of Associative Memory in Virtual Shared Memory Architectures: A Price-Performance Comparison.	PDP	1996	DBLP DOI BibTeX RDF	virtual shared memory architectures, price-performance, set associative memory, large coherent cache, performance evaluation, benchmarks, parallel machines, memory hierarchy, shared memory systems, costing, cost, associative memory, memory architecture, content-addressable storage, application specific, virtual storage, CC-NUMA, COMA, miss ratios
2	Gyungho Lee	An assessment of COMA multiprocessors. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	Cache Only Memory Architecture, Perfect Club Benchmark Suite, coherence policy, performance evaluation, performance, discrete event simulation, memory hierarchy, shared memory systems, distributed memory systems, update, trace driven simulations, cache storage, network traffic, miss ratio, distributed shared memory multiprocessors, shared address space, invalidate
2	Sophie Chabridon, Erol Gelenbe	Dependable parallel computing with agents based on a task graph model.	PDP	1995	DBLP DOI BibTeX RDF	dependable parallel computing, task graph model, MIMD shared memory architecture, performance evaluation, parallel processing, parallel programming, parallel programs, agents, discrete event simulation, discrete-event simulator, fast Fourier transform, software performance evaluation, failure detection, application program
2	Roger Espasa, Mateo Valero, David A. Padua, Marta Jiménez, Eduard Ayguadé	Quantitative analysis of vector code.	PDP	1995	DBLP DOI BibTeX RDF	Convex C3480, Perfect Club benchmarks, cost/performance tradeoffs, single bus memory architecture, slow-down, vector register, vector programs, performance evaluation, virtual machines, simulation study, vector processor systems, vector code
2	Tadayuki Sakakibara, Katsuyoshi Kitai, Tadaaki Isobe, Shigeko Yazawa, Teruo Tanaka, Yasuhiro Inagami, Yoshiko Tamaki	Scalable Parallel Memory Architecture with a Skew Scheme.	International Conference on Supercomputing	1993	DBLP DOI BibTeX RDF	ILLIAC IV
2	Bin Qin	Meet Real-Time Requirements of Parallel Programs and Maximally Utilize System Resources.	IEEE Trans. Software Eng.	1993	DBLP DOI BibTeX RDF	time-cost behavior, real-time systems, performance analysis, parallel programs, parallel programming, multiprocessor system, programming theory, software cost estimation, real-time requirements, shared memory architecture, execution environment, system resources
2	Mark A. Holliday, Carla Schlatter Ellis	Accuracy of Memory Reference Traces of Parallel Computations in Trace-Driven Simulation.	IEEE Trans. Parallel Distrib. Syst.	1992	DBLP DOI BibTeX RDF	load sequences, memory reference traces, trace-drive simulation, global trace, shared memory multiprocessingenvironment, address change points, address affecting points, process traces, intrinsic trace, address flow graph, store sequences, partial program reexecution, graph-traceable, parallel program, parallel programming, parallel computations, memory management, storage management, memory architecture, path expressions
1	Minming Li, Tiantian Liu, Chun Jason Xue, Yingchao Zhao	Analysis and approximation for bank selection instruction minimization on partitioned memory architecture.	J. Comb. Optim.	2012	DBLP DOI BibTeX RDF
1	T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravikumar	On-chip memory architecture exploration framework for DSP processor-based embedded system on chip.	ACM Trans. Embedded Comput. Syst.	2012	DBLP DOI BibTeX RDF
1	Yahya Jan, Lech Józwiak	Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Ismael Marín Carrión, Enrique Arias Antúnez, M. M. Artigao Castillo, Juan José Miralles Canals	A distributed memory architecture implementation of the False Nearest Neighbors method based on distribution of dimensions.	The Journal of Supercomputing	2012	DBLP DOI BibTeX RDF
1	Jens Haupert	Towards a digital object memory architecture.	PerCom Workshops	2012	DBLP DOI BibTeX RDF
1	Eric S. Chung, Michael Papamichael, Gabriel Weisz, James C. Hoe, Ken Mai	Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing.	FPGA	2012	DBLP DOI BibTeX RDF
1	Vasilios I. Kelefouras, George Athanasiou, Nikolaos Alachiotis, Harris E. Michail, Angeliki Kritikakou, Costas E. Goutis	A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization.	IEEE Transactions on Signal Processing	2011	DBLP DOI BibTeX RDF
1	Chai Quek, Zaiyi Guo, Douglas L. Maskell	A Novel Fuzzy Associative Memory Architecture for Stock Market Prediction and Trading.	IJFSA	2011	DBLP BibTeX RDF
1	Cheng-Hung Lin, Shih-Chieh Chang	Efficient Pattern Matching Algorithm for Memory Architecture.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Josep Torrellas	Cache-Only Memory Architecture (COMA).	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
1		COMA (Cache-Only Memory Architecture).	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
1	Deepak Dasalukunte, Fredrik Rusek, Viktor Öwall	Improved Memory Architecture for Multicarrier Faster-than-Nyquist Iterative Decoder.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Po-Hao Hsu, Shao-Yi Chien	Reconfigurable cache memory architecture for integral image and integral histogram applications.	SiPS	2011	DBLP DOI BibTeX RDF
1	Jung-Ho Park, Choonki Jang, Jaejin Lee	A Software-Managed Coherent Memory Architecture for Manycores.	PACT	2011	DBLP DOI BibTeX RDF
1	Kun Fang, Long Chen, Zhao Zhang, Zhichun Zhu	Memory Architecture for Integrating Emerging Memory Technologies.	PACT	2011	DBLP DOI BibTeX RDF
1	Atsuya Okazaki, Yasunao Katayama, Seiji Munetoh	Universal optical multi-drop bus for heterogeneous memory architecture.	Conf. Computing Frontiers	2011	DBLP DOI BibTeX RDF
1	Guangyu Sun, Dimin Niu, Jin Ouyang, Yuan Xie	A frequent-value based PRAM memory architecture.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Eric S. Chung, James C. Hoe, Ken Mai	CoRAM: an in-fabric memory architecture for FPGA-based computing.	FPGA	2011	DBLP DOI BibTeX RDF
1	Bruno Zatt, Muhammad Shafique, Sergio Bampi, Jörg Henkel	A low-power memory architecture with application-aware power management for motion & disparity estimation in Multiview Video Coding.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Mohammad Arjomand, Amin Jadidi, Ali Shafiee, Hamid Sarbazi-Azad	A morphable phase change memory architecture considering frequent zero values.	ICCD	2011	DBLP DOI BibTeX RDF
1	Mark Elshaw, Roger K. Moore, Michael Klein	An attention-gating recurrent working memory architecture for emergent speech representation.	Connect. Sci.	2010	DBLP DOI BibTeX RDF
1	Hyunjin Lee, Sangyeun Cho, Bruce R. Childers	PERFECTORY: A Fault-Tolerant Directory Memory Architecture.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	chip yield, lifetime reliability, Chip multiprocessor, cache coherence
1	Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burger	Phase change memory architecture and the quest for scalability.	Commun. ACM	2010	DBLP DOI BibTeX RDF
1	Joo-Young Kim, Donghyun Kim, Seungjin Lee, Kwanho Kim, Hoi-Jun Yoo	Visual Image Processing RAM: Memory Architecture With 2-D Data Location Search and Data Consistency Management for a Multicore Object Recognition Processor.	IEEE Trans. Circuits Syst. Video Techn.	2010	DBLP DOI BibTeX RDF
1	Felipe Cabarcas, Alejandro Rico, Yoav Etsion, Alex Ramírez	Interleaving granularity on high bandwidth memory architecture for CMPs.	ICSAMOS	2010	DBLP DOI BibTeX RDF
1	Gavin Xiaoxu Yao, Ray C. C. Cheung, Kim Fung Man	Counter Embedded Memory architecture for trusted computing platform.	International Symposium on Rapid System Prototyping	2010	DBLP DOI BibTeX RDF
1	Arthur Mutter	A novel hybrid memory architecture with parallel DRAM for fast packet buffers.	HPSR	2010	DBLP DOI BibTeX RDF
1	Shant Chandrakar, Abraham Clements, Arvind Sudarsanam, Aravind Dasu	Memory architecture template for Fast Block Matching algorithms on FPGAs.	IPDPS Workshops	2010	DBLP DOI BibTeX RDF
1	Kun Fang, Hongzhong Zheng, Zhichun Zhu	Heterogeneous Mini-rank: Adaptive, Power-Efficient Memory Architecture.	ICPP	2010	DBLP DOI BibTeX RDF
1	Chunshu Li, Kai Huang, Xiaolang Yan, Jiong Feng, De Ma, Haitong Ge	A high efficient memory architecture for H.264/AVC motion compensation.	ASAP	2010	DBLP DOI BibTeX RDF
1	Xingsheng Tang, Binbin Wu, Tianzhou Chen, Wei Hu, Jiexiang Kang, Zhenwei Zheng	Network Main Memory Architecture for NoC-Based Chips.	CIT	2010	DBLP DOI BibTeX RDF	network on chip, memory bandwidth, main memory
1	Takahiro Hanyu	Special session 8B: New topic MOS/MTJ-hybrid circuit with nonvolatile logic-in-memory architecture and its impact.	VTS	2010	DBLP DOI BibTeX RDF
1	Yuan-Hsin Liao, Gwo-Long Li, Tian-Sheuan Chang	A high throughput VLSI design with hybrid memory architecture for H.264/AVC CABAC decoder.	ISCAS	2010	DBLP DOI BibTeX RDF