Search results for "memory bandwidth"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Daniel Jiménez-González, Xavier Martorell, Alex Ramírez	Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	arithmetic performance analysis, memory bandwidth application, synergistic processor element, DMA controller, direct memory access, element interconnect bus, bandwidth performance peak, processor component, message passing interface, data stream, single instruction multiple data, cell broadband engine, streaming programming model, processor speed
3	Paul Marchal, José Ignacio Gómez, Francky Catthoor	Optimizing the memory bandwidth with loop fusion.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	low power, memory bandwidth, loop fusion
3	Chen Ding, Ken Kennedy	The Memory Bandwidth Bottleneck and its Amelioration by a Compiler. (PDF / PS)	IPDPS	2000	DBLP DOI BibTeX RDF	memory performance model, array reduction, store elimination, memory hierarchy, compiler optimizations, Memory bandwidth, loop fusion
3	Jen-Chien Tuan, Chein-Wei Jen	An Architecture of Full-Search Block Matching for Minimum Memory Bandwidth Requirement.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	minimum memory bandwidth, motion estimation, full search block matching algorithms
3	Syed Masud Mahmud, L. Tissa Samaratunga	Memory Bandwidth Analysis of Hierarchical Multiprocessors using Model Decomposition and Steady-State Flow Analysis.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	memory bandwidth analysis, hierarchicalmultiprocessors, model decomposition, steady-state flow analysis, memory cycle, hierarchical interconnection network, performance evaluation, multiprocessor interconnection networks, shared memory systems, memory architecture, failure analysis
2	Jin Shi, Yici Cai	Scaling power/ground solvers on multi-core with memory bandwidth awareness.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	power/ground solver, multi-core
2	Chenjie Yu, Peter Petrov	Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms.	DAC	2010	DBLP DOI BibTeX RDF	L2 cache partitioning, off-chip bandwidth reduction
2	Mehmet Belgin, Godmar Back, Calvin J. Ribbens	Pattern-based sparse matrix representation for memory-efficient SMVM kernels.	ICS	2009	DBLP DOI BibTeX RDF	bcoo, bcsr, matrix splitting, pbr, smvm, spmv, prefetching, vectorization, memory bandwidth, iterative solvers, sparse computations, csr
2	Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken V. Vu, Xiaowei Jiang, Yan Solihin	Scaling the bandwidth wall: challenges in and avenues for CMP scaling.	ISCA	2009	DBLP DOI BibTeX RDF	analytical model, memory bandwidth, chip multi-processor
2	Guoping Long, Dongrui Fan, Junchao Zhang	Characterizing and Understanding the Bandwidth Behavior of Workloads on Multi-core Processors.	Euro-Par	2009	DBLP DOI BibTeX RDF	phase model, memory bandwidth, multi-core architecture
2	Kornilios Kourtis, Georgios I. Goumas, Nectarios Koziris	Optimizing sparse matrix-vector multiplication using index and value compression.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	data compression, memory bandwidth, sparse matrix
2	Lixia Liu, Zhiyuan Li, Ahmed H. Sameh	Analyzing memory access intensity in parallel programs on multicore.	ICS	2008	DBLP DOI BibTeX RDF	parallel, multicore, linear system, memory bandwidth, intensity
2	Guoping Long, Dongrui Fan, Junchao Zhang, Fenglong Song, Nan Yuan, Wei Lin	A Performance Model of Dense Matrix Operations on Many-Core Architectures.	Euro-Par	2008	DBLP DOI BibTeX RDF	dense matrix, performance model, memory bandwidth, many-core architecture
2	Sze-Wei Lee, Soon-Chieh Lim	An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	2-D DWT processing systems, memory mapping scheme, memeory access, memory bandwidth
2	Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim	A cost-effective VLSI architecture for anisotropic texture filtering in limited memory bandwidth.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	Tzu-Yun Kuo, Yu-Kun Lin, Tian-Sheuan Chang	A Memory Bandwidth Optimized Interpolator for Motion Compensation in the H.264 Video Decoding.	APCCAS	2006	DBLP DOI BibTeX RDF
2	Hongtu Jiang, Viktor Öwall, Håkan Ardö	Real-Time Video Segmentation with VGA Resolution and Memory Bandwidth Reduction.	AVSS	2006	DBLP DOI BibTeX RDF
2	Jeremiah Willcock, Andrew Lumsdaine	Accelerating sparse matrix computations via data compression.	ICS	2006	DBLP DOI BibTeX RDF	data compression, high-performance computing, memory bandwidth, sparse matrix
2	Ibrahim Hur, Calvin Lin	Adaptive History-Based Memory Schedulers for Modern Processors.	IEEE Micro	2006	DBLP DOI BibTeX RDF	Memory schedulers, IBM Power5, processors, DRAM, memory bandwidth
2	Hou Rui, Fuxin Zhang, Weiwu Hu	A Memory Bandwidth Effective Cache Store Miss Policy.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
2	Evangelos Koukis, Nectarios Koziris	Memory Bandwidth Aware Scheduling for SMP Cluster Nodes.	PDP	2005	DBLP DOI BibTeX RDF
2	Naga K. Govindaraju, Nikunj Raghuvanshi, Dinesh Manocha	Fast and Approximate Stream Mining of Quantiles and Frequencies Using Graphics Processors.	SIGMOD Conference	2005	DBLP DOI BibTeX RDF	data streams, sorting, sliding windows, memory bandwidth, graphics processors, frequencies, quantiles
2	Jeffrey T. Draper, Tim Barrett, Jeff Sondeen, Sumit D. Mediratta, Chang Woo Kang, Ihn Kim, Gokhan Daglikoca	A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	memory bandwidth, memory wall, processing-in-memory
2	Marc Leeman, David Atienza, Geert Deconinck, Vincenzo De Florio, José M. Mendías, Chantal Ykman-Couvreur, Francky Catthoor, Rudy Lauwereins	Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	dynamic data types, multimedia, low power, memory management, memory hierarchy, memory bandwidth, dynamic memory management, system-level exploration, memory footprint
2	Christos D. Antonopoulos, Dimitrios S. Nikolopoulos, Theodore S. Papatheodorou	Realistic Workload Scheduling Policies for Taming the Memory Bandwidth Bottleneck of SMPs.	HiPC	2004	DBLP DOI BibTeX RDF
2	José Ignacio Gómez, Paul Marchal, Sven Verdoolaege, Luis Piñuel, Francky Catthoor	Optimizing the Memory Bandwidth with Loop Morphing.	ASAP	2004	DBLP DOI BibTeX RDF
2	Chang-Hyo Yu, Lee-Sup Kim	A hierarchical depth buffer for minimizing memory bandwidth in 3D rendering engine: Depth Filter.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt	An algorithm for mapping loops onto coarse-grained reconfigurable architectures.	LCTES	2003	DBLP DOI BibTeX RDF	ALU array, memory bandwidth utilization, coarse-grained reconfigurable architecture, mapping algorithm
2	Rama Sangireddy, Arun K. Somani	Application-Specific Computing with Adaptive Register File Architectures.	ASAP	2003	DBLP DOI BibTeX RDF	Computing capacity, compute-intensive Function, Memory bandwidth, Register File
2	Catherine H. Gebotys	A network flow approach to memory bandwidth utilization in embedded DSP core processors.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
2	Julien Sébot, Nathalie Drach-Temam	Memory Bandwidth: The True Bottleneck of SIMD Multimedia Performance on a Superscalar Processor.	Euro-Par	2001	DBLP DOI BibTeX RDF
2	David Wonnacott	Using Time Skewing to Eliminate Idle Time due to Memory Bandwidth and Network Limitations. (PDF / PS)	IPDPS	2000	DBLP DOI BibTeX RDF	compute balance, machine balance, scalable locality, scalable parallelism, cache optimization, loop tiling
2	Wen-Tsong Shiue	Optimizing Memory Bandwidth with ILP Based Memory Exploration and Assignment for Low Power Embedded Systems.	MTDT	2000	DBLP DOI BibTeX RDF
2	Sally A. McKee, William A. Wulf, James H. Aylor, Robert H. Klenke, Maximo H. Salinas, Sung I. Hong, Dee A. B. Weikle	Dynamic Access Ordering for Streamed Computations.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Memory systems architecture, memory access ordering, memory access scheduling, memory bandwidth, memory latency
2	Sven Wuytack, Francky Catthoor, Gjalt G. de Jong, Hugo De Man	Minimizing the required memory bandwidth in VLSI system realizations.	IEEE Trans. VLSI Syst.	1999	DBLP DOI BibTeX RDF
2	Nitzan Weinberg, David Nagle	Dynamic Elimination of Pointer-Expressions.	IEEE PACT	1998	DBLP DOI BibTeX RDF	pointer-expression, sphinx, sub-expression, SPECint95, memory address, performance analysis, compiler, locality, speech recognition, dynamic, microprocessor, mpeg, cache memory, microarchitecture, jpeg, value, spatial, memory bandwidth, data reuse, temporal, pointer, conditional execution
2	David H. Albonesi, Israel Koren	Improving the Memory Bandwidth of Highly-Integrated, Wide-Issue, Microprocessor-Based Systems.	IEEE PACT	1997	DBLP DOI BibTeX RDF
2	Kumar N. Ganapathy, Benjamin W. Wah, Chien-Wei Li	Designing a Scalable Processor Array for Recurrent Computations.	IEEE Trans. Parallel Distrib. Syst.	1997	DBLP DOI BibTeX RDF	Access unit, affine dependencies, area index, clock-rate reduction, multimesh graph, uniform dependencies, scheduling, partitioning, memory bandwidth, processor array, dependence graph
2	Doug Burger, James R. Goodman, Alain Kägi	Memory Bandwidth Limitations of Future Microprocessors.	ISCA	1996	DBLP DOI BibTeX RDF
2	Sven Wuytack, Francky Catthoor, Gjalt G. de Jong, Bill Lin, Hugo De Man	Flow Graph Balancing for Minimizing the Required Memory Bandwidth. (PDF / PS)	ISSS	1996	DBLP DOI BibTeX RDF
2	A. M. del Corral, José M. Llabería	Increasing the Effective Memory Bandwidth in Multivector Processors.	EUROMICRO	1996	DBLP DOI BibTeX RDF	multivector processors, concurrent vector streams, access sequence, peak throughput, performance, memory bandwidth, vector processor systems
2	Sally A. McKee, William A. Wulf, Trevor C. Landon	Bounds on Memory Bandwidth in Streamed Computations.	Euro-Par	1995	DBLP DOI BibTeX RDF
2	Paul E. R. Lippens, Vijay Nagasamy, Wayne Wolf	CAD challenges in multimedia computing.	ICCAD	1995	DBLP DOI BibTeX RDF	CAD challenges, VLSI systems-on-chips, advanced CAD synthesis tools, high computation rates, high-volume chip, multimedia computer design, multirate computing problem, VLSI, circuit CAD, multimedia computing, memory bandwidth
2	Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia	Fast discrete function evaluation using decision diagrams.	ICCAD	1995	DBLP DOI BibTeX RDF	address lookups, cycle-based logic simulation, decision-diagram based function evaluation, fast discrete function evaluation, latch ports, orders-of-magnitude potential speedup, output ports, logic design, memory hierarchy, logic CAD, decision theory, circuit analysis computing, memory bandwidth, table lookup, digital circuits, logic simulators, logic function, function evaluation, multi-valued decision diagrams
2	A. Agrawal, A. Raju, S. Varadarajan, Magdy A. Bayoumi	A scalable shared buffer ATM switch architecture.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	electronic switching systems, field effect transistor switches, scalable shared buffer ATM switch architecture, memory bandwidth requirement, maximum crosspoint switch size, buffer memory size, access time reduction, multiple buffer memories, 8/spl times/8 switch, 1 mum, 622 Mbit/s, asynchronous transfer mode, asynchronous transfer mode, shared memory systems, buffer storage, CMOS technology, CMOS digital integrated circuits, B-ISDN, B-ISDN, switching circuits, parallel access
2	John L. Gustafson, Quinn Snell	HINT: A new way to measure computer performance.	HICSS	1995	DBLP DOI BibTeX RDF	computer performance measurement, computer speeds, hierarchical integration, QUIPS work measure, quality improvements per second, memory regimes, memory size, hand calculation, sequential programming environments, performance evaluation, algorithms, scalability, computer architecture, computer architectures, digital arithmetic, digital arithmetic, portability, supercomputers, execution times, precision, memory bandwidth, computational performance, HINT, parallel programming environments, storage capacity
2	Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor	A comparative evaluation of software techniques to hide memory latency.	HICSS	1995	DBLP DOI BibTeX RDF	comparative software evaluation, software oriented techniques, superscalar machines, superpipelined machines, software cache prefetching, data fetch request, software controlled prefetching, aggressive prefetching, memory bandwidth requirements, bus traffic, performance, parallel machines, program compilers, processor scheduling, software performance evaluation, software pipelining, pipeline processing, microarchitecture, cache storage, instruction set architecture, memory latency, loop unrolling, static scheduling, conditional branches
2	Sally A. McKee, Steven A. Moyer, William A. Wulf	Increasing Memory Bandwidth for Vector Computations.	Programming Languages and System Architectures	1994	DBLP DOI BibTeX RDF
2	Hee Yong Youn, Calvin Ching-Yuen Chen	A Comprehensive Performance Evaluation of Crossbar Networks.	IEEE Trans. Parallel Distrib. Syst.	1993	DBLP DOI BibTeX RDF	processor acceptanceprobability, rejected request handling, home memory concept, performance evaluation, performance evaluation, parallel architectures, multiprocessor interconnection networks, multiprocessing systems, memory bandwidth, crossbar networks, bus arbitration
2	Ravi Ganesan, Shlomo Weiss	Scalar Memory References in Pipelined Multiprocessors: A Performance Study.	IEEE Trans. Software Eng.	1992	DBLP DOI BibTeX RDF	scalar memory references, pipelined multiprocessors, high memory bandwidth, memory cycle, processor cycle time, bank reservation time, bank busy time, performance evaluation, probability, Markov chain, Markov processes, parallel machines, Markov models, storage management, simulation results, pipeline processing, state space, transition probabilities, pipelined computers, memory bank
2	Abdelaziz Mzoughi, Mustapha Lalam, Daniel Litaize	Very High Speed Vectorial Processors Using Serial Multiport Memory as Data Memory.	CONPAR	1992	DBLP DOI BibTeX RDF	serial multiport memory, realignment network, memory bandwidth, vector processor
2	B. Ramakrishna Rau	Interleaved Memory Bandwidth in a Model of a Muyltiprocessor Computer System.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	performance evaluation, multiprocessors, Analytical models, memory bandwidth, memory interference, interleaved memories
1	Vinicius Petrucci, Orlando Loques, Daniel Mossé, Rami G. Melhem, Neven Abou Gazala, Sameh Gobriel	Thread Assignment Optimization with Real-Time Performance and Memory Bandwidth Guarantees for Energy-Efficient Heterogeneous Multi-core Systems.	IEEE Real-Time and Embedded Technology and Applications Symposium	2012	DBLP DOI BibTeX RDF
1	Jui-Hung Hsieh, Wei-Cheng Tai, Tian-Sheuan Chang	Memory bandwidth-scalable motion estimation for mobile video coding.	EURASIP J. Adv. Sig. Proc.	2011	DBLP DOI BibTeX RDF
1	Chang Hoon Son, Seong Mo Park, Young Min Kim	An embedded compression algorithm integrated with Motion JPEG2000 system for reduction of off-chip video memory bandwidth.	IJISTA	2011	DBLP DOI BibTeX RDF
1	Ajit Gupte, Bharadwaj Amrutur, Mahesh Mehendale, Ajit V. Rao, Madhukar Budagavi	Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding.	IEEE Trans. Circuits Syst. Video Techn.	2011	DBLP DOI BibTeX RDF
1	David Boland, George A. Constantinides	Optimizing memory bandwidth use and performance for matrix-vector multiplication in iterative methods.	TRETS	2011	DBLP DOI BibTeX RDF
1	Michael Bauer, Henry Cook, Brucek Khailany	CudaDMA: optimizing GPU memory bandwidth via warp specialization.	SC	2011	DBLP DOI BibTeX RDF
1	Pedro Trancoso, Norbert Martínez-Bazan, Josep-Lluis Larriba-Pey	Memory-, Bandwidth-, and Power-Aware Multi-core for a Graph Database Workload.	ARCS	2011	DBLP DOI BibTeX RDF
1	Jens Breitbart	Analysis of a Memory Bandwidth Limited Scenario for NUMA and GPU Systems.	IPDPS Workshops	2011	DBLP DOI BibTeX RDF
1	Nicolas Melot, Kenan Avdic, Jörg Keller, Christoph W. Kessler	Investigation of main memory bandwidth on Intel Single-Chip Cloud Computer.	MARC Symposium	2011	DBLP BibTeX RDF
1	Kentaro Sano, Yoshiaki Hatsuda, Satoru Yamamoto	Scalable Streaming-Array of Simple Soft-Processors for Stencil Computations with Constant Memory-Bandwidth.	FCCM	2011	DBLP DOI BibTeX RDF
1	David Eklov, Nikos Nikoleris, David Black-Schaffer, Erik Hagersten	Cache Pirating: Measuring the Curse of the Shared Cache.	ICPP	2011	DBLP DOI BibTeX RDF	multicore performance, performance analysis, memory system, memory bandwidth, cache performance
1	Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto	Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video.	FPL	2010	DBLP DOI BibTeX RDF
1	Di Xu, Chenggang Wu, Pen-Chung Yew	On mitigating memory bandwidth contention through bandwidth-aware scheduling.	PACT	2010	DBLP DOI BibTeX RDF
1	Kazuya Katahira, Kentaro Sano, Satoru Yamamoto	FPGA-based lossless compressors of floating-point data streams to enhance memory bandwidth.	ASAP	2010	DBLP DOI BibTeX RDF
1	David Boland, George A. Constantinides	Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods.	ARC	2010	DBLP DOI BibTeX RDF
1	Fang Liu, Xiaowei Jiang, Yan Solihin	Understanding how off-chip memory bandwidth partitioning in Chip Multiprocessors affects system performance.	HPCA	2010	DBLP DOI BibTeX RDF
1	S. Arash Ostadzadeh, Marco Corina, Carlo Galuzzi, Koen Bertels	tQUAD - Memory Bandwidth Usage Analysis.	ICPP Workshops	2010	DBLP DOI BibTeX RDF
1	Kentaro Sano, Kazuya Katahira, Satoru Yamamoto	Segment-Parallel Predictor for FPGA-Based Hardware Compressor and Decompressor of Floating-Point Data Streams to Enhance Memory I/O Bandwidth.	DCC	2010	DBLP DOI BibTeX RDF	prediction-based compresson, hardware, floating point, memory bandwidth, lossless compression
1	Xingsheng Tang, Binbin Wu, Tianzhou Chen, Wei Hu, Jiexiang Kang, Zhenwei Zheng	Network Main Memory Architecture for NoC-Based Chips.	CIT	2010	DBLP DOI BibTeX RDF	network on chip, memory bandwidth, main memory
1	Surendra Byna, Jiayuan Meng, Anand Raghunathan, Srimat T. Chakradhar, Srihari Cadambi	Best-effort semantic document search on GPUs.	GPGPU	2010	DBLP DOI BibTeX RDF	best-effort computing, dependency relaxation, supervised semantic indexing, GPGPU, CUDA, document search
1	Yifeng Chen, Xiang Cui, Hong Mei	Large-scale FFT on GPU clusters.	ICS	2010	DBLP DOI BibTeX RDF	GPU clusters, array dimensions, FFT
1	Javier Lira, Carlos Molina, Antonio González	The auction: optimizing banks usage in Non-Uniform Cache Architectures.	ICS	2010	DBLP DOI BibTeX RDF	bank replacement policy, non-uniform cache architecture (NUCA), chip multiprocessors (CMP)
1	Lixia Liu, Zhiyuan Li	A compiler-automated array compression scheme for optimizing memory intensive programs.	ICS	2010	DBLP DOI BibTeX RDF	adaptive code selection, bandwidth consumption reduction, compiler implementation, memory intensive programs, compression
1	Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi, Christopher Batten, Vladimir Stojanovic, Krste Asanovic	Re-architecting DRAM memory systems with monolithically integrated silicon photonics.	ISCA	2010	DBLP DOI BibTeX RDF	dram architecture, energy-efficiency, silicon photonics
1	Srimat T. Chakradhar, Murugan Sankaradass, Venkata Jakkula, Srihari Cadambi	A dynamically configurable coprocessor for convolutional neural networks.	ISCA	2010	DBLP DOI BibTeX RDF	dynamic reconfiguration, parallel computer architecture, convolutional neural networks
1	Sunpyo Hong, Hyesoon Kim	An integrated GPU power and performance model.	ISCA	2010	DBLP DOI BibTeX RDF	GPU architecture, performance, energy, analytical model, CUDA, power estimation
1	Janghaeng Lee, Haicheng Wu, Madhumitha Ravichandran, Nathan Clark	Thread tailor: dynamically weaving threads together for efficient, adaptive parallel applications.	ISCA	2010	DBLP DOI BibTeX RDF	managed parallelism, threading, dynamic compilation
1	Martin Zabel, Rainer G. Spallek	Application requirements and efficiency of embedded Java bytecode multi-cores.	JTRES	2010	DBLP DOI BibTeX RDF	multi-core, multi-threaded, realtime, Java bytecode
1	Guoming He, Haijun Feng, Cuiping Li, Hong Chen	Parallel SimRank computation on large graphs with iterative aggregation.	KDD	2010	DBLP DOI BibTeX RDF	iterative aggregation, parallel, graph, gpu, simrank
1	Yi Yang, Ping Xiang, Jingfei Kong, Huiyang Zhou	A GPGPU compiler for memory optimization and parallelism management.	PLDI	2010	DBLP DOI BibTeX RDF	compiler, gpgpu
1	Lixia Liu, Zhiyuan Li	Improving parallelism and locality with asynchronous algorithms.	PPOPP	2010	DBLP DOI BibTeX RDF	parallel numerical programs, data locality, memory performance, loop tiling, asynchronous algorithms
1	Budirijanto Purnomo, Norman Rubin, Michael Houston	ATI Stream Profiler: a tool to optimize an OpenCL kernel on ATI Radeon GPUs.	SIGGRAPH Posters	2010	DBLP DOI BibTeX RDF
1	Changkyu Kim, Jatin Chhugani, Nadathur Satish, Eric Sedlar, Anthony D. Nguyen, Tim Kaldewey, Victor W. Lee, Scott A. Brandt, Pradeep Dubey	FAST: fast architecture sensitive tree search on modern CPUs and GPUs.	SIGMOD Conference	2010	DBLP DOI BibTeX RDF	compression, thread-level parallelism, cpu, gpu, tree search, data-level parallelism
1	Nadathur Satish, Changkyu Kim, Jatin Chhugani, Anthony D. Nguyen, Victor W. Lee, Daehyun Kim, Pradeep Dubey	Fast sort on CPUs and GPUs: a case for bandwidth oblivious SIMD sort.	SIGMOD Conference	2010	DBLP DOI BibTeX RDF	merge network, tlp, performance, databases, sorting, buffer, merge, many-core, simd, radix
1	Yuxiong He, Charles E. Leiserson, William M. Leiserson	The Cilkview scalability analyzer.	SPAA	2010	DBLP DOI BibTeX RDF	burdened parallelism, cilk++, cilkview, dag model, performance, scalability, parallel programming, parallelism, software tools, multithreading, speedup, work, span, multicore programming
1	Kyusik Chung, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim	Shader-based tessellation to save memory bandwidth in a mobile multimedia processor.	Computers & Graphics	2009	DBLP DOI BibTeX RDF
1	Dinesh K. Kaushik, Micheal Smith, Allan B. Wollaber, Barry F. Smith, Andrew Siegel, Won Sik Yang	Enabling high-fidelity neutron transport simulations on petascale architectures.	SC	2009	DBLP DOI BibTeX RDF	discrete ordinates, neutron transport, nuclear reactors, parallel scalability, memory bandwidth
1	Kanupriya Gulati, Sunil P. Khatri	Accelerating statistical static timing analysis using graphics processing units.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	David S. Kung, Ruchir Puri	CAD challenges for 3D ICs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Young-Su Kwon, Bontae Koo, Nak-Woong Eum	Partial conflict-relieving programmable address shuffler for parallel memories in multi-core processor.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Ronny Ronen	Larrabee: a many-core Intel architecture for visual computing.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	graphics architecture, many-core computing, parrallel processing, processor arechitecture, software rendering
1	Meikang Qiu, Lei Zhang, Edwin Hsing-Mean Sha	ILP optimal scheduling for multi-module memory.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	variable assignment, integer linear programming, energy saving, instruction scheduling
1	Timo Aila, Samuli Laine	Understanding the efficiency of ray traversal on GPUs.	High Performance Graphics	2009	DBLP DOI BibTeX RDF	SIMT, ray tracing, SIMD
1	Scott Beamer, Krste Asanovic, Christopher Batten, Ajay Joshi, Vladimir Stojanovic	Designing multi-socket systems using silicon photonics.	ICS	2009	DBLP DOI BibTeX RDF	multi-socket, silicon photonics
1	Konstantis Daloukas, Christos D. Antonopoulos, Nikolaos Bellas	Implementation of a wide-angle lens distortion correction algorithm on the cell broadband engine.	ICS	2009	DBLP DOI BibTeX RDF	cell b.e., heterogeneous multi-core processors, real-time, parallel programming, image warping, stencil computation
1	Rob van Nieuwpoort, John W. Romein	Using many-core hardware to correlate radio astronomy signals.	ICS	2009	DBLP DOI BibTeX RDF	lofar, correlator, many-core
1	Guangming Tan, Ziyu Guo, Mingyu Chen, Dan Meng	Single-particle 3d reconstruction from cryo-electron microscopy images on GPU.	ICS	2009	DBLP DOI BibTeX RDF	cryo-em, performance tuning, many-core, gpu
1	Pedro Diaz, Marcelo Cintra	Stream chaining: exploiting multiple levels of correlation in data prefetching.	ISCA	2009	DBLP DOI BibTeX RDF	data prefetching