Search results for "memory bound"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Mustafa M. Tikir, Laura Carrington, Erich Strohmaier, Allan Snavely	A genetic algorithms approach to modeling the performance of memory-bound computations.	SC	2007	DBLP DOI BibTeX RDF	cache bandwidth, memory bound applications, genetic algorithms, machine learning, performance modeling and prediction
2	Jason Loew, Dmitry Ponomarev	Two-Level Reorder Buffers: Accelerating Memory-Bound Applications on SMT Architectures.	ICPP	2008	DBLP DOI BibTeX RDF
2	Jongeun Lee, Aviral Shrivastava	Static analysis of processor stall cycle aggregation.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	memory bound loops, processor free time, stall cycle aggregation, embedded systems, low power, code transformation
2	Sujata Doshi, Fabian Monrose, Aviel D. Rubin	Efficient Memory Bound Puzzles Using Pattern Databases.	ACNS	2006	DBLP DOI BibTeX RDF
2	Martín Abadi, Michael Burrows, Mark S. Manasse, Ted Wobber	Moderately hard, memory-bound functions.	ACM Trans. Internet Techn.	2005	DBLP DOI BibTeX RDF	Spam
2	Christian Poellabauer, Leo Singleton, Karsten Schwan	Feedback-Based Dynamic Voltage and Frequency Scaling for Memory-Bound Real-Time Applications.	IEEE Real-Time and Embedded Technology and Applications Symposium	2005	DBLP DOI BibTeX RDF
2	Cynthia Dwork, Andrew Goldberg, Moni Naor	On Memory-Bound Functions for Fighting Spam.	CRYPTO	2003	DBLP DOI BibTeX RDF
1	Daren Lee, Ivo D. Dinov, Bin Dong, Boris Gutman, Igor Yanovsky, Arthur W. Toga	CUDA optimization strategies for compute- and memory-bound neuroimaging algorithms.	Computer Methods and Programs in Biomedicine	2012	DBLP DOI BibTeX RDF
1	Robert Strzodka, Mohammed Shaheen, Dawid Pajak, Hans-Peter Seidel	Cache Accurate Time Skewing in Iterative Stencil Computations.	ICPP	2011	DBLP DOI BibTeX RDF	memory bound, temporal blocking, memory wall, wavefront, stencil, banded matrix, time skewing
1	Robert Strzodka, Mohammed Shaheen, Dawid Pajak, Hans-Peter Seidel	Cache oblivious parallelograms in iterative stencil computations.	ICS	2010	DBLP DOI BibTeX RDF	memory bound, parallelism and locality, temporal blocking, cache oblivious, memory wall, stencil, time skewing
1	Todd A. Anderson	Optimizations in a private nursery-based garbage collector.	ISMM	2010	DBLP DOI BibTeX RDF	garbage collection, functional languages
1	Alexander S. van Amesfoort, Ana Lucia Varbanescu, Henk J. Sips, Rob van Nieuwpoort	Evaluating multi-core platforms for HPC data-intensive kernels.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	data-intensive kernels, memory-bound applications, the cell processor, multi-core processors, gpus
1	Vasileios Karakasis, Georgios I. Goumas, Nectarios Koziris	Exploring the effect of block shapes on the performance of sparse kernels.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Chad Scherrer, Tim Shippert, Andrès Márquez	Accelerating numerical calculation on the Cray XMT.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Joseph Gebis, Leonid Oliker, John Shalf, Samuel Williams, Katherine A. Yelick	Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture.	ARCS	2009	DBLP DOI BibTeX RDF
1	Stephen F. Siegel, Andrew R. Siegel	A Memory-Efficient Data Redistribution Algorithm.	PVM/MPI	2009	DBLP DOI BibTeX RDF	MADRE, memory-limited, MPI, distributed, redistribution
1	Mark Silberstein, Assaf Schuster, Dan Geiger, Anjul Patney, John D. Owens	Efficient computation of sum-products on GPUs through software-managed cache.	ICS	2008	DBLP DOI BibTeX RDF	sum-product, GPGPU, CUDA, software-managed cache
1	Wei-Ngan Chin, Huu Hai Nguyen, Corneliu Popeea, Shengchao Qin	Analysing memory resource bounds for low-level programs.	ISMM	2008	DBLP DOI BibTeX RDF	fixpoint analysis, heap space analysis, low level programs, stack space analysis
1	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero	Runahead Threads to improve SMT performance.	HPCA	2008	DBLP DOI BibTeX RDF
1	Thomas M. DuBois, Bryant Lee, Yi Wang, Marc Olano, Uzi Vishkin	XMT-GPU: A PRAM Architecture for Graphics Computation.	ICPP	2008	DBLP DOI BibTeX RDF
1	Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos	Temporal streams in commercial server applications.	IISWC	2008	DBLP DOI BibTeX RDF
1	Wen-Yew Liang, Shih-Chang Chen, Yang-Lang Chang, Jyh-Perng Fang	Memory-Aware Dynamic Voltage and Frequency Prediction for Portable Devices.	RTCSA	2008	DBLP DOI BibTeX RDF
1	Martin Thuresson, Lawrence Spracklen, Per Stenström	Memory-Link Compression Schemes: A Value Locality Perspective.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Memory Structures, Data compaction and compression, I/O and Data Communications
1	Manuel A. Ballester, Stephanie Wehner, Andreas Winter	State Discrimination With Post-Measurement Information.	IEEE Transactions on Information Theory	2008	DBLP DOI BibTeX RDF
1	Kun-Ta Chuang, Jiun-Long Huang, Ming-Syan Chen	Mining top-k frequent patterns in the presence of the memory constraint.	VLDB J.	2008	DBLP DOI BibTeX RDF
1	Konrad Malkowski, Padma Raghavan, Mahmut T. Kandemir, Mary Jane Irwin	Phase-aware adaptive hardware selection for power-efficient scientific computations.	ISLPED	2007	DBLP DOI BibTeX RDF	DVFS adaptive architecture prefetchers sparse scientific codes performance power energy
1	Samuel Williams, Leonid Oliker, Richard W. Vuduc, John Shalf, Katherine A. Yelick, James Demmel	Optimization of sparse matrix-vector multiplication on emerging multicore platforms.	SC	2007	DBLP DOI BibTeX RDF
1	Shivali Agarwal, Rajkishore Barik, Dan Bonachea, Vivek Sarkar, R. K. Shyamasundar, Katherine A. Yelick	Deadlock-free scheduling of X10 computations with bounded resources.	SPAA	2007	DBLP DOI BibTeX RDF	deadlock-free scheduling, X10, active messages
1	Robert Baxter, Stephen Booth, Mark Bull, Geoff Cawood, James Perry, Mark Parsons, Alan Simpson, Arthur S. Trew, Andrew McCormick, Graham Smart, Ronnie Smart, Allan Cantle, Richard Chamberlain, Gildas Genest	The FPGA High-Performance Computing Alliance Parallel Toolkit.	AHS	2007	DBLP DOI BibTeX RDF
1	Lei Shi, Yuyan Sun, Lin Wei	Effect of Scheduling Discipline on CPU-MEM Load Sharing System.	GCC	2007	DBLP DOI BibTeX RDF
1	Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez	Scavenger: A New Last Level Cache Architecture with Global Block Priority.	MICRO	2007	DBLP DOI BibTeX RDF
1	Ying Zhang, Gen Li 0002, Xuejun Yang	Recognition and Optimization of Loop-Carried Stream Reusing of Scientific Computing Applications on the Stream Processor.	International Conference on Computational Science	2007	DBLP DOI BibTeX RDF
1	A. Satheesh, S. Bama	Generalized Load Sharing for Distributed Operating Systems.	OTM Conferences	2007	DBLP DOI BibTeX RDF
1	Nilanjan Banerjee, Samir Saklikar, Subir Saha	Anti-vamming trust enforcement in peer-to-peer VoIP networks.	IWCMC	2006	DBLP DOI BibTeX RDF	vamming, trust, peer-to-peer networks, identity, voice over IP
1	Jaydeep Marathe, Frank Mueller	Hardware profile-guided automatic page placement for ccNUMA systems.	PPOPP	2006	DBLP DOI BibTeX RDF	page placement, NUMA, profile-guided optimization, hardware performance monitoring
1	Lap-Kei Lee, H. F. Ting	Maintaining significant stream statistics over sliding windows.	SODA	2006	DBLP DOI BibTeX RDF
1	Shiwen Hu, Lizy Kurian John	Impact of virtual execution environments on processor energy consumption and hardware adaptation.	VEE	2006	DBLP DOI BibTeX RDF	hardware adaptation, energy efficiency, power dissipation
1	Lixin Zhang 0002, Michael Parker, John B. Carter	Efficient address remapping in distributed shared-memory systems.	TACO	2006	DBLP DOI BibTeX RDF	Smart memory controller, address remapping, shadow address, performance evaluation, multiprocessors, cache coherence
1	Yingmin Li, Benjamin C. Lee, David Brooks, Zhigang Hu, Kevin Skadron	CMP design space exploration subject to physical constraints.	HPCA	2006	DBLP DOI BibTeX RDF
1	Joshua J. Yi, Resit Sendag, Lieven Eeckhout, Ajay Joshi, David J. Lilja, Lizy Kurian John	Evaluating Benchmark Subsetting Approaches.	IISWC	2006	DBLP DOI BibTeX RDF
1	Haakon Dybdahl, Per Stenström	Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
1	Pang Ko, Srinivas Aluru	Obtaining Provably Good Performance from Suffix Trees in Secondary Storage.	CPM	2006	DBLP DOI BibTeX RDF
1	Fabien Coelho	Exponential Memory-Bound Functions for Proof of Work Protocols.	IACR Cryptology ePrint Archive	2005	DBLP BibTeX RDF
1	Justin Teller, Charles B. Silio Jr., Bruce L. Jacob	Performance characteristics of MAUI: an intelligent memory system architecture.	Memory System Performance	2005	DBLP DOI BibTeX RDF	MAUI memory architecture, SimpleScalar simulator, data-intensive calculations, intelligent memory, memory architecture, vector processing, SIMD processing
1	Soraya Ghiasi, Tom W. Keller, Freeman L. Rawson III	Scheduling for heterogeneous processors in server systems.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	scheduling, performance, power, heterogeneous processors
1	Jahangir Hasan, T. N. Vijaykumar	Dynamic pipelining: making IP-lookup truly scalable.	SIGCOMM	2005	DBLP DOI BibTeX RDF	scalable, pipelined, IP-lookup, longest prefix matching, tries
1	Jian Li, José F. Martínez	Power-performance considerations of parallel computing on chip multiprocessors.	TACO	2005	DBLP DOI BibTeX RDF	Voltage/frequency scaling, granularity, parallel efficiency
1	Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez	Checkpointed Early Load Retirement.	HPCA	2005	DBLP DOI BibTeX RDF
1	Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadron	Performance, Energy, and Thermal Considerations for SMT and CMP Architectures.	HPCA	2005	DBLP DOI BibTeX RDF
1	Pradeep Nalabalapu, Ron Sass	Bandwidth Management with a Reconfigurable Data Cache.	IPDPS	2005	DBLP DOI BibTeX RDF
1	Weidong Shi, Hsien-Hsin S. Lee, Mrinmoy Ghosh, Chenghuai Lu, Alexandra Boldyreva	High Efficiency Counter Mode Security Architecture via Prediction and Precomputation.	ISCA	2005	DBLP DOI BibTeX RDF
1	Kihwan Choi, Ramakrishna Soma, Massoud Pedram	Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Cynthia Dwork, Moni Naor, Hoeteck Wee	Pebbling and Proofs of Work.	CRYPTO	2005	DBLP DOI BibTeX RDF
1	Tanping Wang, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos	smt- SPRINTS: Software Precomputation with Intelligent Streaming for Resource-Constrained SMTs.	Euro-Par	2005	DBLP DOI BibTeX RDF
1	YuXing Tang, Kun Deng, Xingming Zhou	The Design Space of CMP vs. SMT for High Performance Embedded Processor.	ICESS	2005	DBLP DOI BibTeX RDF
1	Gene Cooperman, Xiaoqin Ma, Viet Ha Nguyen	Static Performance Evaluation for Memory-Bound Computing: The MBRAM Model.	PDPTA	2004	DBLP BibTeX RDF
1	Kihwan Choi, Ramakrishna Soma, Massoud Pedram	Dynamic voltage and frequency scaling based on workload decomposition.	ISLPED	2004	DBLP DOI BibTeX RDF	workload decomposition, dynamic voltage and frequency scaling
1	Kihwan Choi, Ramakrishna Soma, Massoud Pedram	Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-Off Based on the Ratio of Off-Chip Access to On-Chip Computation Times.	DATE	2004	DBLP DOI BibTeX RDF
1	Srihari Makineni, Ravi R. Iyer	Architectural Characterization of TCP/IP Packet Processing on the Pentium M Microprocessor.	HPCA	2004	DBLP DOI BibTeX RDF
1	Christophe Lemuet, William Jalby, Sid Ahmed Ali Touati	Improving Load/Store Queues Usage in Scientific Computing.	ICPP	2004	DBLP DOI BibTeX RDF
1	Leonardo R. Bachega, Siddhartha Chatterjee, Kenneth A. Dockser, John A. Gunnels, Manish Gupta, Fred G. Gustavson, Christopher A. Lapkowski, Gary K. Liu, Mark P. Mendell, Charles D. Wait, T. J. Christopher Ward	A High-Performance SIMD Floating Point Unit for BlueGene/L: Architecture, Compilation, and Algorithm Design.	IEEE PACT	2004	DBLP DOI BibTeX RDF
1	Yuan Chou, Brian Fahs, Santosh G. Abraham	Microarchitecture Optimizations for Exploiting Memory-Level Parallelism.	ISCA	2004	DBLP DOI BibTeX RDF
1	Nastaran Baradaran, Pedro C. Diniz, Joonseok Park	Extending the Applicability of Scalar Replacement to Multiple Induction Variables.	LCPC	2004	DBLP DOI BibTeX RDF
1	Ittai Abraham, Cyril Gavoille, Dahlia Malkhi	Routing with Improved Communication-Space Trade-Off.	DISC	2004	DBLP DOI BibTeX RDF
1	David S. H. Rosenthal	On The Cost Distribution of a Memory Bound Function	CoRR	2003	DBLP BibTeX RDF
1	Martín Abadi, Michael Burrows, Ted Wobber	Moderately Hard, Memory-Bound Functions.	NDSS	2003	DBLP BibTeX RDF
1	Pao-Ann Hsiung, Feng-Shi Su	Synthesis of Real-Time Embedded Software by Timed Quasi-Static Scheduling.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Venkata K. Pingali, Sally A. McKee, Wilson C. Hsieh, John B. Carter	Restructuring Computations for Temporal Data Cache Locality.	International Journal of Parallel Programming	2003	DBLP DOI BibTeX RDF	optimization, data structures, Memory performance
1	Byoungro So, Mary W. Hall, Pedro C. Diniz	A Compiler Approach to Fast Hardware Design Space Exploration in FPGA-based Systems.	PLDI	2002	DBLP DOI BibTeX RDF	reuse analysis, design space exploration, loop transformations, data dependence analysis
1	Pao-Ann Hsiung, Trong-Yen Lee, Feng-Shi Su	Formal Synthesis and Code Generation of Real-Time Embedded Software using Time-Extended Quasi-Static Scheduling.	APSEC	2002	DBLP DOI BibTeX RDF	Time Complex-Choice Petri Nets, time-extended quasi-static scheduling, code generation, real-time embedded software
1	Dimitrios S. Nikolopoulos, Constantine D. Polychronopoulos	Adaptive Scheduling under Memory Pressure on Multiprogrammed Cluster.	CCGRID	2002	DBLP DOI BibTeX RDF
1	Jamison D. Collins, Dean M. Tullsen, Hong Wang 0003, John Paul Shen	Dynamic speculative precomputation.	MICRO	2001	DBLP DOI BibTeX RDF
1	Jason Liu, David M. Nicol	Learning not to share.	Workshop on Parallel and Distributed Simulation	2001	DBLP DOI BibTeX RDF
1	Lixin Zhang 0002, Zhen Fang, Michael Parker, Binu K. Mathew, Lambert Schaelicke, John B. Carter, Wilson C. Hsieh, Sally A. McKee	The Impulse Memory Controller.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Computer architecture, memory systems
1	Xiaodong Zhang, Yanxia Qu, Li Xiao	Improving Distributed Workload Performance by Sharing both CPU and Memory Resources.	ICDCS	2000	DBLP DOI BibTeX RDF
1	Chung-Hsing Hsu, Ulrich Kremer, Michael S. Hsiao	Compiler-Directed Dynamic Frequency and Voltage Scheduling.	PACS	2000	DBLP DOI BibTeX RDF
1	Parthasarathy Ranganathan, Sarita V. Adve, Norman P. Jouppi	Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions.	ISCA	1999	DBLP DOI BibTeX RDF
1	Vijay S. Pai, Parthasarathy Ranganathan, Hazim Abdel-Shafi, Sarita V. Adve	The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	performance evaluation, instruction-level parallelism, Shared-memory multiprocessors, software prefetching
1	F. Warren Burton	Guaranteeing Good Memory Bound for Parallel Programs.	IEEE Trans. Software Eng.	1996	DBLP DOI BibTeX RDF
1	Arjen K. Lenstra	Generating Standard DSA Signatures Without Long Inversion.	ASIACRYPT	1996	DBLP DOI BibTeX RDF
1	Hector Garcia-Molina, Arvin Park, Lawrence R. Rogers	Performance Through Memory.	SIGMETRICS	1987	DBLP DOI BibTeX RDF
1	R. M. Bryant	Maximum Processing Rates of Memory Bound Systems.	J. ACM	1982	DBLP DOI BibTeX RDF