Search results for "memory controller"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Benny Akesson, Kees Goossens, Markus Ringhofer	Predator: a predictable SDRAM memory controller.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	predictability, system-on-chip, SDRAM, memory controller
3	Chitra Natarajan, Bruce Christenson, Faye A. Briggs	A study of performance impact of memory controller features in multi-processor server environment.	WMPI	2004	DBLP DOI BibTeX RDF	memory transaction scheduling, server systems, multi-processors, memory controller, memory subsystem, performance impact
2	Dennis Abts, Natalie D. Enright Jerger, John Kim, Dan Gibson, Mikko H. Lipasti	Achieving predictable performance through better memory controller placement in many-core CMPs.	ISCA	2009	DBLP DOI BibTeX RDF	interconnection networks, chip multiprocessors, routing algorithms, memory controllers
2	Hassab Elgawi Osman	Architecture of behavior-based and robotics self-optimizing memory controller.	ICRA	2009	DBLP DOI BibTeX RDF
2	Hyuk-Jun Lee, Eui-Young Chung	Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Bas Breijer, Filipa Duarte, Stephan Wong	An OCM based shared Memory controller for Virtex 4.	FPL	2007	DBLP DOI BibTeX RDF
2	Mrinmoy Ghosh, Hsien-Hsin S. Lee	Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs.	MICRO	2007	DBLP DOI BibTeX RDF
2	Chih-Da Chien, Chih-Wei Wang, Chiun-Chau Lin, Tien-Wei Hsieh, Yuan-Hwa Chu, Jiun-In Guo	A Low Latency Memory Controller for Video Coding Systems.	ICME	2007	DBLP DOI BibTeX RDF
2	Dhiraj D. Kalamkar, Mainak Chaudhuri, Mark Heinrich	Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads.	ISPASS	2007	DBLP DOI BibTeX RDF	active memory cluster, directory protocol thread, active memory address remapping, parallel reduction, coherence protocol extension, software protocol, multi-threaded node, dual-core node, active memory architecture, distributed shared memory, multiprocessor architecture, memory controller, matrix transpose
2	Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang, Howard David	DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving.	ISPASS	2007	DBLP DOI BibTeX RDF	channel bandwidth utilization, DRAM-level prefetching, dynamic random access memory, fully-buffered DIMM, dual in-line memory module, redundant bandwidth, memory block, L2 cache block, DRAM power consumption, SPEC2000 program, software cache prefetching, idle memory latency, power saving, multicore processor, memory controller, interconnect structure, DRAM chip
2	Lixin Zhang 0002, Michael Parker, John B. Carter	Efficient address remapping in distributed shared-memory systems.	TACO	2006	DBLP DOI BibTeX RDF	Smart memory controller, address remapping, shadow address, performance evaluation, multiprocessors, cache coherence
2	Kun-Bin Lee, Tzu-Chieh Lin, Chein-Wei Jen	An Efficient Quality-Aware Memory Controller for Multimedia Platform SoC.	IEEE Trans. Circuits Syst. Video Techn.	2005	DBLP DOI BibTeX RDF
2	Artur Burchard, Ewa Hekstra-Nowacka, Atul Chauhan	A Real-Time Streaming Memory Controller.	DATE	2005	DBLP DOI BibTeX RDF
2	Scott Rixner	Memory Controller Optimizations for Web Servers.	MICRO	2004	DBLP DOI BibTeX RDF
2	Faye A. Briggs, Suresh Chittor, Kai Cheng	Micro-architecture techniques in the intel E8870 scalable memory controller.	WMPI	2004	DBLP DOI BibTeX RDF	distributed coherency, transaction flows, scalability, memory latency
2	Daehyun Kim, Mainak Chaudhuri, Mark Heinrich, Evan Speight	Architectural Support for Uniprocessor and Multiprocessor Active Memory Systems.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Active memory systems, address remapping, flexible memory controller architecture, distributed shared memory, cache coherence protocol
2	Xiaobo Fan, Carla Schlatter Ellis, Alvin R. Lebeck	Modeling of DRAM Power Control Policies Using Deterministic and Stochastic Petri Nets.	PACS	2002	DBLP DOI BibTeX RDF	Modeling, Petri Nets, DRAM, Memory Controller, Control Policy
2	R. Brett Tremaine, T. Basil Smith, Michael E. Wazlowski, David Har, Kwok-Ken Mak, Sujith Arramreddy	Pinnacle: IBM MXT in a Memory Controller Chip.	IEEE Micro	2001	DBLP DOI BibTeX RDF
2	Lixin Zhang 0002, Zhen Fang, Michael Parker, Binu K. Mathew, Lambert Schaelicke, John B. Carter, Wilson C. Hsieh, Sally A. McKee	The Impulse Memory Controller.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Computer architecture, memory systems
2	Xianglong Huang, Zhenlin Wang, Kathryn S. McKinley	Compiling for the Impulse Memory Controller.	IEEE PACT	2001	DBLP DOI BibTeX RDF
2	Mario Porrmann, Ulrich Rückert, Karl Michael Marks, Jörg Landmann	HiBRIC-MEM, a Memory Controller for PowerPC Based Systems.	EUROMICRO	1997	DBLP DOI BibTeX RDF
1	Marcelo Yuffe, Moty Mehalel, Ernest Knoll, Joseph Shor, Tsvika Kurts, Eran Altshuler, Eyal Fayneh, Kosta Luria, Michael Zelikson	A Fully Integrated Multi-CPU, Processor Graphics, and Memory Controller 32-nm Processor.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann	Automated construction of a cycle-approximate transaction level model of a memory controller.	DATE	2012	DBLP BibTeX RDF
1	Tassadaq Hussain, Muhammad Shafiq, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé	PPMC: A Programmable Pattern Based Memory Controller.	ARC	2012	DBLP DOI BibTeX RDF
1	Eyee Hyun Nam, Bryan Suk Joon Kim, Hyeonsang Eom, Sang Lyul Min	Ozone (O3): An Out-of-Order Flash Memory Controller Architecture.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
1	John Colby Hoffman, Marios S. Pattichis	A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback.	Int. J. Reconfig. Comp.	2011	DBLP DOI BibTeX RDF
1	Marius Grannæs, Magnus Jahre, Lasse Natvig	Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy.	ARCS	2011	DBLP DOI BibTeX RDF
1	Syed Minhaj Hassan, Dhruv Choudhary, Mitchelle Rasquinha, Sudhakar Yalamanchili	Regulating Locality vs. Parallelism Tradeoffs in Multiple Memory Controller Environments.	PACT	2011	DBLP DOI BibTeX RDF
1	Marcelo Yuffe, Ernest Knoll, Moty Mehalel, Joseph Shor, Tsvika Kurts	A fully integrated multi-CPU, GPU and memory controller 32nm processor.	ISSCC	2011	DBLP DOI BibTeX RDF
1	Yoann Congal, Mickael Cartron	Memory controller for globally uncoordinated and locally coordinated checkpointing.	ICECS	2011	DBLP DOI BibTeX RDF
1	Zefu Dai, Jianwen Zhu	A bursty multi-port memory controller with quality-of-service guarantees.	CODES+ISSS	2011	DBLP DOI BibTeX RDF
1	Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen	Optimal memory controller placement for chip multiprocessor.	CODES+ISSS	2011	DBLP DOI BibTeX RDF
1	Gary Thorpe, Nagi N. Mekhiel	Modeling an Adaptable Memory Controller.	I. J. Comput. Appl.	2010	DBLP BibTeX RDF
1	Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi	Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support.	SC	2010	DBLP DOI BibTeX RDF
1	Dongki Kim, Sungjoo Yoo, Sunggu Lee	A Network Congestion-Aware Memory Controller.	NOCS	2010	DBLP DOI BibTeX RDF	memory access scheduling, network-on-chip, Memory, congestion
1	Benny Akesson, Williston Hayes Jr., Kees Goossens	Classification and Analysis of Predictable Memory Patterns.	RTCSA	2010	DBLP DOI BibTeX RDF	memory patterns, burst count, classification, predictability, SDRAM, memory controller
1	Engin Ipek, Jeremy Condit, Edmund B. Nightingale, Doug Burger, Thomas Moscibroda	Dynamically replicated memory: building reliable systems from nanoscale resistive memories.	ASPLOS	2010	DBLP DOI BibTeX RDF	write endurance, phase-change memory
1	Sergey Zhuravlev, Sergey Blagodurov, Alexandra Fedorova	Addressing shared resource contention in multicore processors via scheduling.	ASPLOS	2010	DBLP DOI BibTeX RDF	shared resource contention, scheduling, multicore processors
1	Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi	Rethinking DRAM design and organization for energy-constrained multi-cores.	ISCA	2010	DBLP DOI BibTeX RDF	chipkill, dram architecture, subarrays, energy-efficiency, locality
1	Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Mateo Valero	An Analyzable Memory Controller for Hard Real-Time CMPs.	Embedded Systems Letters	2009	DBLP DOI BibTeX RDF
1	Gary Thorpe, Nagi N. Mekhiel	Modeling An Adaptable Memory Controller.	CAINE	2009	DBLP BibTeX RDF
1	Hassab Elgawi Osman	RL-Based Memory Controller for Scalable Autonomous Systems.	ICONIP	2009	DBLP DOI BibTeX RDF
1	George L. Yuan, Ali Bakhoda, Tor M. Aamodt	Complexity effective memory access scheduling for many-core accelerator architectures.	MICRO	2009	DBLP DOI BibTeX RDF	graphics processors, on-chip interconnection networks, memory controller
1	Banit Agrawal, Timothy Sherwood	High-bandwidth network memory system through virtual pipelines.	IEEE/ACM Trans. Netw.	2009	DBLP DOI BibTeX RDF	VPNM, bank conflicts, mean time to stall, packet reassembly, virtual pipeline, network, memory, DRAM, universal hashing, memory controller, MTS, packet buffering
1	Subhash Saini, Andrey Naraikin, Rupak Biswas, David Barkai, Timothy Sandstrom	Early performance evaluation of a "Nehalem" cluster using scientific and engineering applications.	SC	2009	DBLP DOI BibTeX RDF
1	David Roberts, Taeho Kgil, Trevor N. Mudge	Integrating NAND flash devices onto servers.	Commun. ACM	2009	DBLP DOI BibTeX RDF
1	Nikola Knezevic, Simon Schubert, Dejan Kostic	Towards a cost-effective networking testbed.	Operating Systems Review	2009	DBLP DOI BibTeX RDF
1	Ali Bakhoda, George L. Yuan, Wilson W. L. Fung, Henry Wong, Tor M. Aamodt	Analyzing CUDA workloads using a detailed GPU simulator.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Håkon Ording Bugge	An evaluation of Intel's core i7 architecture using a comparative approach.	Computer Science - R&D	2009	DBLP DOI BibTeX RDF	SPEC MPI2007, Nehalem, iCore7, Harpertown, Quad-Core, QuickPath Interconnect, Moore’s Law, Benchmarking, Stream, Micro-benchmarks
1	Yingpan Wu, Lixin Yu, Lidong Lan, Haiyang Zhou	A Coverage-Driven Constraint Random-Based Functional Verification Method of Memory Controller.	IEEE International Workshop on Rapid System Prototyping	2008	DBLP DOI BibTeX RDF
1	David Bermingham, Liu Zhen, Xiaojun Wang	SimNP: a flexible platform for the simulation of a network processing system.	ANCS	2008	DBLP DOI BibTeX RDF	network processing system, simulation, performance analysis
1	Major Bhadauria, Sally A. McKee	Optimizing thread throughput for multithreaded workloads on memory constrained CMPs.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	performance, efficiency, power, memory bandwidth
1	Kelly D. Larson	Translation of an existing VMM-based SystemVerilog testbench to OVM.	DAC	2008	DBLP DOI BibTeX RDF	OVM, VMM, testbenches, SystemVerilog
1	Yungang Bao, Mingyu Chen, Yuan Ruan, Li Liu, Jianping Fan 0002, Qingbo Yuan, Bo Song, Jianwei Xu	HMTT: a platform independent full-system memory trace monitoring system.	SIGMETRICS	2008	DBLP DOI BibTeX RDF	DIMM, HMTT, memory trace, real system
1	Guy E. Blelloch, Phillip B. Gibbons, Harsha Vardhan Simhadri	Combinable memory-block transactions.	SPAA	2008	DBLP DOI BibTeX RDF	memory-block transactions, priority write, read-modify-write, shared memory, transactional memory, queue, contention, combining, stack, linearizability, semaphore
1	Jelena Trajkovic, Alexander V. Veidenbaum, Arun Kejariwal	Improving SDRAM access energy efficiency for low-power embedded systems.	ACM Trans. Embedded Comput. Syst.	2008	DBLP DOI BibTeX RDF	embedded processors and low power, fetch buffer, write-combining buffer, SDRAM
1	Bharat Sukhwani, Alessandro Forin, Richard Neil Pittman	An Extensible I/O Subsystem.	FCCM	2008	DBLP DOI BibTeX RDF
1	Amit Hadke, Tony Benavides, S. J. Ben Yoo, Rajeevan Amirtharajah, Venkatesh Akella	OCDIMM: Scaling the DRAM Memory Wall Using WDM Based Optical Interconnects.	Hot Interconnects	2008	DBLP DOI BibTeX RDF
1	Ibrahim Hur, Calvin Lin	A comprehensive approach to DRAM power management.	HPCA	2008	DBLP DOI BibTeX RDF
1	Marius Grannæs, Magnus Jahre, Lasse Natvig	Low-cost open-page prefetch scheduling in chip multiprocessors.	ICCD	2008	DBLP DOI BibTeX RDF
1	Sean Whitty, Rolf Ernst	A bandwidth optimized SDRAM controller for the MORPHEUS reconfigurable architecture.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Thomas Lenart, Henrik Svensson, Viktor Öwall	Modeling and exploration of a reconfigurable architecture for digital holographic imaging.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt	Prefetch-Aware DRAM Controllers.	MICRO	2008	DBLP DOI BibTeX RDF
1	Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet	Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Xipeng Shen, Jonathan Shaw	Scalable Implementation of Efficient Locality Approximation.	LCPC	2008	DBLP DOI BibTeX RDF
1	Thomas Lenart, Mats Gustafsson, Viktor Öwall	A Hardware Acceleration Platform for Digital Holographic Imaging.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	digital holography, flexible FFT, data scaling, hybrid floating-point, burst oriented memory, matrix transpose
1	Mihir R. Choudhury, Kyle Ringgenberg, Scott Rixner, Kartik Mohanram	Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory.	DATE	2007	DBLP DOI BibTeX RDF
1	Simone Medardoni, Martino Ruggiero, Davide Bertozzi, Luca Benini, Giovanni Strano, Carlo Pistritto	Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms.	DATE	2007	DBLP DOI BibTeX RDF
1	Zhen Fang, Lixin Zhang 0002, John B. Carter, Ali Ibrahim, Michael Parker	Active memory operations.	ICS	2007	DBLP DOI BibTeX RDF	distributed shared memory, cache coherence, stream processing, DRAM, memory performance, thread synchronization
1	Dennis Abts, Abdulla Bataineh, Steve Scott, Greg Faanes, Jim Schwarzmeier, Eric Lundberg, Tim Johnson, Mike Bye, Gerald Schwoerer	The Cray BlackWidow: a highly scalable vector multiprocessor.	SC	2007	DBLP DOI BibTeX RDF	high-radix, architecture, multiprocessor, shared memory, distributed shared memory, vector, fat-tree, MPP
1	Arvind Seshadri, Mark Luk, Ning Qu, Adrian Perrig	SecVisor: a tiny hypervisor to provide lifetime kernel code integrity for commodity OSes.	SOSP	2007	DBLP DOI BibTeX RDF	code attestation, memory virtualization, hypervisor, code injection attacks, preventing, code integrity
1	Sang-Won Lee, Dong-Joo Park, Tae-Sun Chung, Dong-Ho Lee, Sangwon Park, Ha-Joo Song	A log buffer-based flash translation layer using fully-associative sector translation.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	associative mapping, log blocks, Flash memory, address translation, FTL
1	Ibrahim Hur, Calvin Lin	Memory scheduling for modern microprocessors.	ACM Trans. Comput. Syst.	2007	DBLP DOI BibTeX RDF	adaptive history-based scheduling, memory scheduling, Memory system performance
1	Yuechao Niu, Majid Baghaei Nejad, Hannu Tenhunen, Li-Rong Zheng	Design of a Digital Baseband Processor for UWB Transceiver on RFID Tag.	AINA Workshops	2007	DBLP DOI BibTeX RDF
1	Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee	An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems.	FPL	2007	DBLP DOI BibTeX RDF
1	Brinda Ganesh, Aamer Jaleel, David Wang, Bruce L. Jacob	Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling.	HPCA	2007	DBLP DOI BibTeX RDF
1	Christian A. Lang, Bishwaranjan Bhattacharjee, Timothy Malkemus, Ioana Stanoi	Improved Buffer Size Adaptation through Cache/Controller Coupling.	ICDE Workshops	2007	DBLP DOI BibTeX RDF
1	Lakshmana Rao Vittanala, Mainak Chaudhuri	Integrating Memory Compression and Decompression with Coherence Protocols in Distributed Shared Memory Multiprocessors.	ICPP	2007	DBLP DOI BibTeX RDF
1	Hongqi Hu, Jiadong Xu, Zhemin Duan, Jingnan Sun	High Efficiency Synchronous DRAM Controller for H.264 HDTV Encoder.	SiPS	2007	DBLP DOI BibTeX RDF
1	Pat Conway, Bill Hughes	The AMD Opteron Northbridge Architecture.	IEEE Micro	2007	DBLP DOI BibTeX RDF	system topology, northbridge, scalability, microarchitecture, point-to-point networking
1	Toshiharu Imai, Kiyofumi Tanaka	The Concept of Memory-Based Thread Execution by Highly Functional Memory Controller.	PDPTA	2006	DBLP BibTeX RDF
1	Sang Lyul Min, Eyee Hyun Nam	Current trends in flash memory technology: invited paper.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Alberto Ros, Manuel E. Acacio, José M. García	An efficient cache design for scalable glueless shared-memory multiprocessors.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	L2, directory structure, glueless shared-memory multiprocessors, cache, cache coherence, memory wall
1	Jike Chong, Chidamber Kulkarni, Gordon J. Brebner	Building a flexible and scalable DRAM interface for networking applications on FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF
1	Zhen Yang, Xudong Shi, Feiqi Su, Jih-Kwon Peir	Overlapping dependent loads with addressless preload.	PACT	2006	DBLP DOI BibTeX RDF	instruction and issue window, pointer-chasing loads, data prefetching, memory-level parallelism
1	Rich Oehler	Computer science - architecture - Re-inventing the x86 architecture: quad-core and beyond.	SC	2006	DBLP DOI BibTeX RDF
1	Qing K. Zhu, Paige Kolze	Metal Fix and Power Network Repair for SOC.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Ibrahim Hur, Calvin Lin	Memory Prefetching Using Adaptive Stream Detection.	MICRO	2006	DBLP DOI BibTeX RDF
1	S.-W. Lee, S.-C. Lim	VLSI Design of a Wavelet Processing Core.	IEEE Trans. Circuits Syst. Video Techn.	2006	DBLP DOI BibTeX RDF
1	Sang-Won Lee, Won-Kyoung Choi, Dong-Joo Park	FAST: An Efficient Flash Translation Layer for Flash Memory.	EUC Workshops	2006	DBLP DOI BibTeX RDF	Associative mapping, Operating Systems, Flash memory, Address translation, FTL
1	Seiji Miura, Satoru Akiyama	A memory controller that reduces latency of cached SDRAM.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Jun Shao, Brian T. Davis	The Bit-reversal SDRAM Address Mapping.	SCOPES	2005	DBLP DOI BibTeX RDF	address mapping, SDRAM, memory controller
1	Justin Teller, Charles B. Silio Jr., Bruce L. Jacob	Performance characteristics of MAUI: an intelligent memory system architecture.	Memory System Performance	2005	DBLP DOI BibTeX RDF	MAUI memory architecture, SimpleScalar simulator, data-intensive calculations, intelligent memory, memory architecture, vector processing, SIMD processing
1	Eric McCorkle	Programmable bus/memory controllers in modern computer architecture.	ACM Southeast Regional Conference	2005	DBLP DOI BibTeX RDF
1	Shuguang Gong, Huawei Li, Yufeng Xu, Tong Liu, Xiaowei Li	Design of an efficient memory subsystem for network processor.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Taeweon Suh, Daehyun Kim, Hsien-Hsin S. Lee	Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs.	DAC	2005	DBLP DOI BibTeX RDF	heterogeneous, cache coherence, MPSoC, real-time and embedded systems, inter-processor communication
1	Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar	A tunable bus encoder for off-chip data buses.	ISLPED	2005	DBLP DOI BibTeX RDF	TUBE, data bus, data bus encoding, tunable bus encoder
1	Sami Yehia, Jean-Francois Collard, Olivier Temam	Load squared: adding logic close to memory to reduce the latency of indirect loads with high miss ratios.	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF
1	Gregory S. Johnson, Juhyun Lee, Christopher A. Burns, William R. Mark	The irregular Z-buffer: Hardware acceleration for irregular data structures.	ACM Trans. Graph.	2005	DBLP DOI BibTeX RDF	Real-time graphics hardware, visible surface algorithms, architecture, computer graphics, shadow algorithms
1	Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Rotenberg	Tapping ZettaRAMTM for Low-Power Memory Systems.	HPCA	2005	DBLP DOI BibTeX RDF