Search results for "memory controllers"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt	Prefetch-Aware Memory Controllers.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	prefetching, DRAM, Memory systems, memory controllers, multi-core systems
2	Dennis Abts, Natalie D. Enright Jerger, John Kim, Dan Gibson, Mikko H. Lipasti	Achieving predictable performance through better memory controller placement in many-core CMPs.	ISCA	2009	DBLP DOI BibTeX RDF	interconnection networks, chip multiprocessors, routing algorithms, memory controllers
2	Georg Hager, Thomas Zeiser, Gerhard Wellein	Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers.	IPDPS	2008	DBLP DOI BibTeX RDF
2	Mainak Chaudhuri, Mark Heinrich	Integrated Memory Controllers with Parallel Coherence Streams.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF
1	Manu Awasthi, David W. Nellans, Kshitij Sudan, Rajeev Balasubramonian, Al Davis	Managing Data Placement in Memory Systems with Multiple Memory Controllers.	International Journal of Parallel Programming	2012	DBLP DOI BibTeX RDF
1	Benny Akesson, Kees Goossens	Architectures and modeling of predictable memory controllers for improved system integration.	DATE	2011	DBLP BibTeX RDF
1	Benny Akesson, Po-Chun Huang, Fabien Clermidy, Denis Dutoit, Kees Goossens, Yuan-Hao Chang, Tei-Wei Kuo, Pascal Vivet, Drew Wingard	Memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends.	CODES+ISSS	2011	DBLP DOI BibTeX RDF
1	José Carlos Sancho, Darren J. Kerbyson, Michael Lang 0003	On the Performance and Technological Impact of Adding Memory Controllers in Multi-Core Processors.	Parallel Processing Letters	2010	DBLP DOI BibTeX RDF
1	Manu Awasthi, David W. Nellans, Kshitij Sudan, Rajeev Balasubramonian, Al Davis	Handling the problems and opportunities posed by multiple on-chip memory controllers.	PACT	2010	DBLP DOI BibTeX RDF
1	José Carlos Sancho, Michael Lang 0003, Darren J. Kerbyson	Analyzing the trade-off between multiple memory controllers and memory channels on multi-core processor performance.	IPDPS Workshops	2010	DBLP DOI BibTeX RDF
1	Yoongu Kim, Dongsu Han, Onur Mutlu, Mor Harchol-Balter	ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers.	HPCA	2010	DBLP DOI BibTeX RDF
1	Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt	Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems.	ASPLOS	2010	DBLP DOI BibTeX RDF	fairness, shared memory systems, system performance, multi-core systems
1	Dong Hyuk Woo, Hsien-Hsin S. Lee	COMPASS: a programmable data prefetcher using idle GPU shaders.	ASPLOS	2010	DBLP DOI BibTeX RDF	compute shader, GPU, prefetch
1	Onur Mutlu, Thomas Moscibroda	Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Shared Memory Controllers.	IEEE Micro	2009	DBLP DOI BibTeX RDF
1	Boris Grot, Stephen W. Keckler, Onur Mutlu	Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip.	MICRO	2009	DBLP DOI BibTeX RDF
1	Daniel Hackenberg, Daniel Molka, Wolfgang E. Nagel	Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems.	MICRO	2009	DBLP DOI BibTeX RDF	Nehalem, Shanghai, benchmark, multi-core, coherency
1	Sheng Li, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi	McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures.	MICRO	2009	DBLP DOI BibTeX RDF
1	George L. Yuan, Ali Bakhoda, Tor M. Aamodt	Complexity effective memory access scheduling for many-core accelerator architectures.	MICRO	2009	DBLP DOI BibTeX RDF	graphics processors, on-chip interconnection networks, memory controller
1	Engin Ipek, Onur Mutlu, José F. Martínez, Rich Caruana	Self-Optimizing Memory Controllers: A Reinforcement Learning Approach.	ISCA	2008	DBLP DOI BibTeX RDF
1	Wilson J. Perez, Jaime Velasco-Medina, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda	A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs.	IOLTS	2008	DBLP DOI BibTeX RDF
1	Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt	Prefetch-Aware DRAM Controllers.	MICRO	2008	DBLP DOI BibTeX RDF
1	Georg Hager, Thomas Zeiser, Gerhard Wellein	Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers	CoRR	2007	DBLP BibTeX RDF
1	Ke Ning, David R. Kaeli	External memory page remapping for embedded multimedia systems.	LCTES	2007	DBLP DOI BibTeX RDF	memory coloring, memory page remapping, embedded systems, memory controllers
1	Ibrahim Hur, Calvin Lin	Memory scheduling for modern microprocessors.	ACM Trans. Comput. Syst.	2007	DBLP DOI BibTeX RDF	adaptive history-based scheduling, memory scheduling, Memory system performance
1	Albert Meixner, Daniel J. Sorin	Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures.	HPCA	2007	DBLP DOI BibTeX RDF
1	Jike Chong, Chidamber Kulkarni, Gordon J. Brebner	Building a flexible and scalable DRAM interface for networking applications on FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF
1	Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, Eric Martin	Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses.	ISVLSI	2005	DBLP DOI BibTeX RDF
1	Eric McCorkle	Programmable bus/memory controllers in modern computer architecture.	ACM Southeast Regional Conference	2005	DBLP DOI BibTeX RDF
1	Annie Foong, Gary L. McAlpine, Dave B. Minturn, Greg J. Regnier, Vikram A. Saletore	An Architecture for Software-Based iSCSI on Multiprocessor Servers.	IPDPS	2005	DBLP DOI BibTeX RDF
1	Poonacha Kongetira, Kathirgamar Aingaran, Kunle Olukotun	Niagara: A 32-Way Multithreaded Sparc Processor.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Microprocessors and microcomputers, Shared memory, Multithreaded processors
1	Faye A. Briggs, Suresh Chittor, Kai Cheng	Micro-architecture techniques in the intel E8870 scalable memory controller.	WMPI	2004	DBLP DOI BibTeX RDF	distributed coherency, transaction flows, scalability, memory latency
1	Mainak Chaudhuri, Mark Heinrich	SMTp: An Architecture for Next-generation Scalable Multi-threading.	ISCA	2004	DBLP DOI BibTeX RDF
1	Heon C. Kim, Hong Shin Jun, Xinli Gu, Sung Soo Chung	At-Speed Interconnect Test and Diagnosis of External Memories on a System.	ITC	2004	DBLP DOI BibTeX RDF
1	David Resnick	Embedded Test for a new Memory-Card Architecture.	ITC	2004	DBLP DOI BibTeX RDF
1	Eduardo Picatoste-Olloqui, Francisco Cardells-Tormo, Jordi Sempere-Agulló, Atilà Herms-Berenguer	Implementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGA.	FPL	2004	DBLP DOI BibTeX RDF
1	Timothe Litt	Support for Debugging in the Alpha 21364 Microprocessor.	ITC	2002	DBLP DOI BibTeX RDF
1	Daniel J. Sorin, Manoj Plakal, Anne Condon, Mark D. Hill, Milo M. K. Martin, David A. Wood	Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol.	IEEE Trans. Parallel Distrib. Syst.	2002	DBLP DOI BibTeX RDF	multicast snooping, Cache coherence, protocol verification, protocol specification, memory consistency
1	Wei-Fen Lin, Steven K. Reinhardt, Doug Burger	Reducing DRAM Latencies with an Integrated Memory Hierarchy Design.	HPCA	2001	DBLP DOI BibTeX RDF
1	Wei-Fen Lin, Steven K. Reinhardt, Doug Burger	Designing a Modern Memory Hierarchy with Hardware Prefetching.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Rambus DRAM, caches, Prefetching, memory bandwidth, spatial locality, memory system design
1	Alexander Gaysinsky, Alon Itai, Hadas Shachnai	Strongly Competitive Algorithms for Caching with Pipelined Prefetching.	ESA	2001	DBLP DOI BibTeX RDF
1	Matthias Gries	The Impact of Recent DRAM Architectures on Embedded Systems Performance.	EUROMICRO	2000	DBLP DOI BibTeX RDF
1	Sung I. Hong, Sally A. McKee, Maximo H. Salinas, Robert H. Klenke, James H. Aylor, William A. Wulf	Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory.	HPCA	1999	DBLP DOI BibTeX RDF
1	Ferran Lisa-Mingo, Jordi Carrabina	A Library of Memory Controllers for an Image Processing Prototyping System. (PDF / PS)	International Workshop on Rapid System Prototyping	1998	DBLP DOI BibTeX RDF
1	Koray Öner, Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Krishnan Ramamurthy, Michel Dubois	The Design of RPM: An FPGA-based Multiprocessor Emulator.	FPGA	1995	DBLP DOI BibTeX RDF	field-programmable gate arrays, VHDL, rapid prototyping, shared-memory multiprocessors, logic emulation, message-passing multicomputers
1	Rajeev Jog, Philip L. Vitale, James R. Callister	Performance Evaluation of a Commercial Cache-Coherent Shared Memory Multiprocessor.	SIGMETRICS	1990	DBLP DOI BibTeX RDF