Search results for "memory hierarchy"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Enric Herrero, José González, Ramon Canal	Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors.	ISCA	2010	DBLP DOI BibTeX RDF	elastic cooperative caching, tiled microarchitectures, chip multiprocessors, memory hierarchy
3	Tsu-Ming Liu, Chen-Yi Lee	Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	prediction, memory hierarchy, H.264/AVC, lookahead
3	Yuying Wang, Xingshe Zhou	Mutual Effect of Instruction Layout Optimization and Instruction Memory Hierarchy.	ICPP Workshops	2007	DBLP DOI BibTeX RDF	Instruction Layout Optimization, Instruction Cache Miss Rate, Cache Memory Hierarchy
3	Kamen Yotov, Keshav Pingali, Paul Stodghill	Automatic measurement of memory hierarchy parameters.	SIGMETRICS	2005	DBLP DOI BibTeX RDF	hardware parameters, optimization, caches, measurement, memory hierarchy, autonomic systems, self-tuning, micro-benchmarks
3	Wolfgang Raab, Hans-Martin Blüthgen, Ulrich Ramacher	A low-power memory hierarchy for a fully programmable baseband processor.	WMPI	2004	DBLP DOI BibTeX RDF	baseband processor, multi-tasked processor, task interleaving, memory hierarchy, low-power memory
3	Basilio B. Fraguela, Ramon Doallo, Emilio L. Zapata	Probabilistic Miss Equations: Evaluating Memory Hierarchy Performance.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	probabilistic miss estimation, Analytical modeling, performance prediction, memory hierarchy, compiler optimizations
3	Mahmut T. Kandemir, Alok N. Choudhary	Compiler-directed scratch pad memory hierarchy design and management.	DAC	2002	DBLP DOI BibTeX RDF	memory hierarchy, data reuse, scratch pad memory
3	Xing Du, Xiaodong Zhang, Zhichun Zhu	Memory Hierarchy Considerations for Cost-Effective Cluster Computing.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Clusters, performance evaluation, memory hierarchy, cost model, SMP, workstations
3	Thomas Kistler, Michael Franz	Automated data-member layout of help objects to improve memory-hierarchy performance.	ACM Trans. Program. Lang. Syst.	2000	DBLP DOI BibTeX RDF	dynmaic data structures, memory-hierarchy optimization, dynamic optimization
3	A. Pavlov, Jean-Luc Béchennec, Daniel Etiemble	Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces.	EUROMICRO	1997	DBLP DOI BibTeX RDF	memory hierarchy simulation, desktop PC, commodity chips, PC microcomputers, synthetic bus traces, dynamically scheduled superscalar microprocessor, performance evaluation, memory architecture
3	Martin C. Herbordt, Charles C. Weems	An empirical study of datapath, memory hierarchy, and network in SIMD array architectures. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	SIMD array architectures, SIMD arrays, ENPASSANT, router network, local transfers, performance evaluation, performance, parallel architectures, broadcast, virtual machines, memory hierarchy, reduction, associativity, memory architecture, cache storage, simulation environment, datapath, block size
2	Rodrígo González-Alberquilla, Fernando Castro, Luis Piñuel, Francisco Tirado	Stack oriented data cache filtering.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	power-performance efficient design, memory hierarchy, cache memory
2	Abel G. Silva-Filho, Cristiano C. de Araujo	A methodology for tuning two-level cache hierarchy considering energy and performance.	SBCCI	2009	DBLP DOI BibTeX RDF	exploration mechanism, two-level caches, embedded systems, system-on-chip, low power design, memory hierarchy
2	Lamia Youseff, Keith Seymour, Haihang You, Jack Dongarra, Richard Wolski	The impact of paravirtualized memory hierarchy on linear algebra computational kernels and software.	HPDC	2008	DBLP DOI BibTeX RDF	paravirtualization, cloud computing, high performance, linear algebra, virtual machine monitors, blas, autotuning
2	Radomir Jakovljevic, Aleksandar Beric	A method for improving the efficiency of a two-level memory hierarchy.	SiPS	2008	DBLP DOI BibTeX RDF
2	Xu Wang, Ge Gan, Joseph Manzano, Dongrui Fan, Shuxu Guo	A Quantitative Study of the On-Chip Network and Memory Hierarchy Design for Many-Core Processor.	ICPADS	2008	DBLP DOI BibTeX RDF
2	Ali El-Moursy, Ahmed El-Mahdy, Hisham El-Shishiny	An efficient in-place 3D transpose for multicore processors with software managed memory hierarchy.	IFMT	2008	DBLP DOI BibTeX RDF	3D transpose, vector programming, parallel programming, SIMD, multi-core systems
2	Guangming Tan, Dongrui Fan, Junchao Zhang, Andrew Russo, Guang R. Gao	Experience on optimizing irregular computation for memory hierarchy in manycore architecture.	PPOPP	2008	DBLP DOI BibTeX RDF	irregular computation., synchronization, memory hierarchy, percolation
2	Ioana Burcea, Stephen Somogyi, Andreas Moshovos, Babak Falsafi	Predictor virtualization.	ASPLOS	2008	DBLP DOI BibTeX RDF	predictor virtualization, caches, metadata, memory hierarchy
2	Ben Lickly, Isaac Liu, Sungjun Kim, Hiren D. Patel, Stephen A. Edwards, Edward A. Lee	Predictable programming on a precision timed architecture.	CASES	2008	DBLP DOI BibTeX RDF	pipeline, memory hierarchy, timing predictability
2	Manman Ren, Ji Young Park, Mike Houston, Alex Aiken, William J. Dally	A tuning framework for software-managed memory hierarchies.	PACT	2008	DBLP DOI BibTeX RDF	bulk decomposition, empirical tuning, software-managed memory hierarchy
2	John E. Savage, Mohammad Zubair	A unified model for multicore architectures.	IFMT	2008	DBLP DOI BibTeX RDF	multicore, memory hierarchy
2	Abhishek Das, William J. Dally	Stream Scheduling: A Framework to Manage Bulk Operations in Memory Hierarchies.	Euro-Par	2008	DBLP DOI BibTeX RDF	Stream Scheduling, Bulk Operations, Sequoia, GSOP Memory Hierarchy, Tunables, Software Pipelining
2	Akshat Verma, Sandeep Sen	Combating I-O bottleneck using prefetching: model, algorithms, and ramifications.	The Journal of Supercomputing	2008	DBLP DOI BibTeX RDF	Prediction sequence, Sorting, Prefetching, Memory hierarchy, External memory algorithms
2	Jason Zebchuk, Andreas Moshovos	A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy.	Computer Architecture Letters	2007	DBLP DOI BibTeX RDF
2	Benny Thörnberg, Martin Palkovic, Qubo Hu, Leif Olsson, Per Gunnar Kjeldsberg, Mattias O'Nils, Francky Catthoor	Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Bruno Zatt, Arnaldo Azevedo, Luciano Volcan Agostini, Altamiro Amadeu Susin, Sergio Bampi	Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Abhishek Das, William J. Dally	Stream Scheduling: A Framework to Manage Bulk Operations in a Memory Hierarchy.	PACT	2007	DBLP DOI BibTeX RDF
2	Zhiguo Ge, Weng-Fai Wong, Hock-Beng Lim	DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systems.	DATE	2007	DBLP DOI BibTeX RDF
2	Athanasios Milidonis, Nikolaos Alachiotis, Vasileios Porpodas, Haralambos Michail, Athanasios Kakarountas, Constantinos E. Goutis	Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy.	DATE	2007	DBLP DOI BibTeX RDF
2	Timothy J. Knight, Ji Young Park, Manman Ren, Mike Houston, Mattan Erez, Kayvon Fatahalian, Alex Aiken, William J. Dally, Pat Hanrahan	Compilation for explicitly managed memory hierarchies.	PPOPP	2007	DBLP DOI BibTeX RDF	bulk operations, software-managed memory hierarchy
2	Guangming Tan, Ninghui Sun, Guang R. Gao	A parallel dynamic programming algorithm on a multi-core architecture.	SPAA	2007	DBLP DOI BibTeX RDF	scalabilitiy, dynamic programming, multi-core, memory hierarchy, data dependence
2	Kamen Yotov, Thomas Roeder, Keshav Pingali, John A. Gunnels, Fred G. Gustavson	An experimental comparison of cache-oblivious and cache-conscious programs.	SPAA	2007	DBLP DOI BibTeX RDF	cache-conscious algorithms, memory hierarchy, memory bandwidth, memory latency, numerical software, cache-oblivious algorithms
2	Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad H. Hammoud, Rami G. Melhem	CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	high-performance search accelerator, high-performance memory substrate, search-intensive application, content addressable random access memory, search operation, memory hierarchy concept, direct hardware implementation, parallel key matching operation, hash function, memory access, application-specific processor, memory structure, hashing technique
2	Seongbeom Kim, Fang Liu, Yan Solihin, Ravi R. Iyer, Li Zhao, W. Cohen	Accelerating Full-System Simulation through Characterizing and Predicting Operating System Performance.	ISPASS	2007	DBLP DOI BibTeX RDF	memory hierarchy model, full-system simulation acceleration, operating system performance characterization, operating system performance prediction, computer hardware complexity, cycle-accurate processor system simulation overheads, system libraries, OS service performance behavior, processor hierarchy model, Linux, software complexity
2	Youcef Bouchebaba, Bruno Girodias, Fabien Coelho, Gabriela Nicolescu, El Mostapha Aboulhamid	Buffer and Register Allocation for Memory Space Optimization.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	program transformation, memory hierarchy, data locality, memory optimization
2	Akshat Verma, Sandeep Sen	Algorithmic Ramifications of Prefetching in Memory Hierarchy.	HiPC	2006	DBLP DOI BibTeX RDF
2	Sriram Krishnamoorthy, Ümit V. Çatalyürek, Jarek Nieplocha, Atanas Rountev, P. Sadayappan	Data management and query - Hypergraph partitioning for automatic memory hierarchy management.	SC	2006	DBLP DOI BibTeX RDF
2	Kayvon Fatahalian, Daniel Reiter Horn, Timothy J. Knight, Larkhoon Leem, Mike Houston, Ji Young Park, Mattan Erez, Manman Ren, Alex Aiken, William J. Dally, Pat Hanrahan	Memory - Sequoia: programming the memory hierarchy.	SC	2006	DBLP DOI BibTeX RDF
2	Xuejun Yang, Jing Du, Xiaobo Yan, Yu Deng	Matrix-Based Programming Optimization for Improving Memory Hierarchy Performance on Imagine.	ISPA	2006	DBLP DOI BibTeX RDF
2	Elena Perez Ramo, Javier Resano, Daniel Mozos, Francky Catthoor	A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead.	IPDPS	2006	DBLP DOI BibTeX RDF
2	Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin, Suleyman Tosun	Multi-Level On-Chip Memory Hierarchy Design for Embedded Chip Multiprocessors.	ICPADS	2006	DBLP DOI BibTeX RDF
2	Benny Thörnberg, Mattias O'Nils	Impact of bit-width specification on the memory hierarchy for a real-time video processing system.	DATE	2006	DBLP DOI BibTeX RDF
2	José Leandro D. Mendes, Luiza M. N. Coutinho, Carlos A. P. S. Martins	Web memory hierarchy learning and research environment.	WCAE	2006	DBLP DOI BibTeX RDF
2	Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil Dutt	Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies.	DAC	2006	DBLP DOI BibTeX RDF	customized memory hierarchy, multiprocessor data reuse analysis, scratch pad memory management
2	Apan Qasem, Ken Kennedy	Profitable loop fusion and tiling using model-driven empirical search.	ICS	2006	DBLP DOI BibTeX RDF	empirical tuning, memory hierarchy, tiling, loop fusion
2	Alexey L. Lastovetsky, Ravi Reddy, Robert Higgins	Building the functional performance model of a processor.	SAC	2006	DBLP DOI BibTeX RDF	grid computing, parallel computing, distributed computing, performance modeling, memory hierarchy, heterogeneous computing, processor performance
2	Peng Li, Dongsheng Wang, Songliu Guo, Tao Tian, Weimin Zheng	Live Range Aware Cache Architecture.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Live Range, Cache, Memory Hierarchy
2	Philip Machanick	The Value of a Small Microkernel for Dreamy Memory and the RAMpage Memory Hierarchy.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	low-power design, cache memories, virtual memory, microkernels, main memory
2	José R. Herrero, Juan J. Navarro	Adapting Linear Algebra Codes to the Memory Hierarchy Using a Hypermatrix Scheme.	PPAM	2005	DBLP DOI BibTeX RDF
2	Chun Chen, Jacqueline Chame, Mary W. Hall	Combining Models and Guided Empirical Search to Optimize for Multiple Levels of the Memory Hierarchy.	CGO	2005	DBLP DOI BibTeX RDF
2	Bert Geelen, Gauthier Lafruit, Vissarion Ferentinos, Rudy Lauwereins, Diederik Verkest	Memory Hierarchy Energy Cost of a Direct Filtering Implementation of the Wavelet Transform.	PATMOS	2005	DBLP DOI BibTeX RDF
2	Steve Carr, Soner Önder	A case for a working-set-based memory hierarchy.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	cache design, loop tiling
2	Chun Chen, Jacqueline Chame, Mary W. Hall, Kristina Lerman	A Systematic Approach to Model-Guided Empirical Search for Memory Hierarchy Optimization.	LCPC	2005	DBLP DOI BibTeX RDF
2	Evangelia Athanasaki, Kornilios Kourtis, Nikos Anastopoulos, Nectarios Koziris	Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures.	Panhellenic Conference on Informatics	2005	DBLP DOI BibTeX RDF
2	Erik G. Hallnor, Steven K. Reinhardt	A Unified Compressed Memory Hierarchy.	HPCA	2005	DBLP DOI BibTeX RDF
2	Philip Machanick	Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
2	Chuanjun Zhang, Frank Vahid	Using a Victim Buffer in an Application-Specific Memory Hierarchy.	DATE	2004	DBLP DOI BibTeX RDF
2	Erik G. Hallnor, Steven K. Reinhardt	A compressed memory hierarchy using an indirect index cache.	WMPI	2004	DBLP DOI BibTeX RDF
2	Federico Angiolini, Francesco Menichelli, Alberto Ferrero, Luca Benini, Mauro Olivieri	A post-compiler approach to scratchpad mapping of code.	CASES	2004	DBLP DOI BibTeX RDF	executable patching, post-compiler processing, dynamic programming, memory hierarchy, optimization algorithm, design automation, power saving, scratchpad memory, embedded design
2	Chia-Lin Yang, Alvin R. Lebeck, Hung-Wei Tseng, Chien-Hao Lee	Tolerating memory latency through push prefetching for pointer-intensive applications.	TACO	2004	DBLP DOI BibTeX RDF	linked data structures, pointer-chasing, Prefetch, memory hierarchy
2	Mohamed M. Zahran	On cache memory hierarchy for Chip-Multiprocessor.	SIGARCH Computer Architecture News	2003	DBLP DOI BibTeX RDF
2	Neungsoo Park, Bo Hong, Viktor K. Prasanna	Tiling, Block Data Layout, and Memory Hierarchy Performance.	IEEE Trans. Parallel Distrib. Syst.	2003	DBLP DOI BibTeX RDF	Block data layout, TLB misses, memory hierarchy, tiling, cache misses
2	Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas	A Dynamically Tunable Memory Hierarchy.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	High performance microprocessors, energy and performance of on-chip caches, memory hierarchy, reconfigurable architectures
2	Rich Vuduc, Attila Gyulassy, James Demmel, Katherine A. Yelick	Memory Hierarchy Optimizations and Performance ounds for Sparse A.	International Conference on Computational Science	2003	DBLP DOI BibTeX RDF
2	Jean-Loup Baer, Douglas Low, Patrick Crowley, Neal Sidhwaney	Memory Hierarchy Design for a Multiprocessor Look-up Engine.	IEEE PACT	2003	DBLP DOI BibTeX RDF
2	Tanja Van Achteren, Francky Catthoor, Rudy Lauwereins, Geert Deconinck	Search space definition and exploration for nonuniform data reuse opportunities in data-dominant applications.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	Memory hierarchy, power consumption, data reuse
2	Maciej Drozdowski, Pawel Wolniewicz	Out-of-Core Divisible Load Processing.	IEEE Trans. Parallel Distrib. Syst.	2003	DBLP DOI BibTeX RDF	scheduling, performance evaluation, memory hierarchy, communication delays, Divisible load theory
2	Daniel Chaver, Christian Tenllado, Luis Piñuel, Manuel Prieto, Francisco Tirado	-D Wavelet Transform Enhancement on General-Purpose Microprocessors: Memory Hierarchy and SIMD Parallelism Exploitation.	HiPC	2002	DBLP DOI BibTeX RDF
2	Michael A. Bender, Richard Cole, Erik D. Demaine, Martin Farach-Colton	Scanning and Traversing: Maintaining Data for Traversals in a Memory Hierarchy.	ESA	2002	DBLP DOI BibTeX RDF
2	Michael A. Bender, Erik D. Demaine, Martin Farach-Colton	Efficient Tree Layout in a Multilevel Memory Hierarchy.	ESA	2002	DBLP DOI BibTeX RDF
2	Murali Jayapala, Francisco Barat, Pieter Op de Beeck, Francky Catthoor, Geert Deconinck, Henk Corporaal	A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors.	PATMOS	2002	DBLP DOI BibTeX RDF
2	Neungsoo Park, Bo Hong, Viktor K. Prasanna	Analysis of Memory Hierarchy Performance of Block Data Layout. (PDF / PS)	ICPP	2002	DBLP DOI BibTeX RDF
2	Chia-Lin Yang, Alvin R. Lebeck	A Programmable Memory Hierarchy for Prefetching Linked Data Structures.	ISHPC	2002	DBLP BibTeX RDF
2	Susan Cotterell, Frank Vahid	Synthesis of customized loop caches for core-based embedded systems.	ICCAD	2002	DBLP DOI BibTeX RDF	customized architectures, embedded systems, low power, synthesis, estimation, memory hierarchy, low energy, tuning, instruction fetching, architecture tuning, loop cache
2	Konstantinos Tatas, Antonios Argyriou, Minas Dasygenis, Dimitrios Soudris, Nikolaos D. Zervas	Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1.	ISQED	2001	DBLP DOI BibTeX RDF
2	Nikolaos Kavvadias, Alexander Chatzigeorgiou, Nikolaos D. Zervas, Spiridon Nikolaidis	Memory hierarchy exploration for low power architectures in embedded multimedia applications.	ICIP	2001	DBLP DOI BibTeX RDF
2	Eric Debes	A new Petri net based model of data transfers in the PC workstation memory hierarchy for MPEG encoding.	ISCAS	2001	DBLP DOI BibTeX RDF
2	Vincent Loechner, Benoît Meister, Philippe Clauss	Data Sequence Locality: A Generalization of Temporal Locality.	Euro-Par	2001	DBLP DOI BibTeX RDF	cache and TLB performance, parameterized polyhedra, Ehrhart polynomials, Memory hierarchy, temporal locality, loop nests
2	Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation.	IEEE Design & Test of Computers	2000	DBLP DOI BibTeX RDF
2	Timothy Sherwood, Brad Calder	ToolBlocks: An Infrastructure for the Construction of Memory Hierarchy Analysis Tools (Research Note).	Euro-Par	2000	DBLP DOI BibTeX RDF
2	Nancy M. Amato, Jack Perdue, Mark M. Mathis, Andrea Pietracaprina, Geppino Pucci	Predicting Performance on SMPs. A Case Study: The SGI Power Challenge. (PDF / PS)	IPDPS	2000	DBLP DOI BibTeX RDF	Caches, Performance Modeling, Memory Hierarchy, SMPs
2	Chen Ding, Ken Kennedy	The Memory Bandwidth Bottleneck and its Amelioration by a Compiler. (PDF / PS)	IPDPS	2000	DBLP DOI BibTeX RDF	memory performance model, array reduction, store elimination, memory hierarchy, compiler optimizations, Memory bandwidth, loop fusion
2	Krister Dackland, Bo Kågström	Blocked algorithms and software for reduction of a regular matrix pair to generalized Schur form.	ACM Trans. Math. Softw.	1999	DBLP DOI BibTeX RDF	QZ-algorithm, Hessenberg-triangular reduction, generalized Schur form, parallelization, memory hierarchy, LAPACK, blocked algorithms
2	Peter Sanders	Accessing Multiple Sequences Through Set Associative Caches.	ICALP	1999	DBLP DOI BibTeX RDF	multi merge, memory hierarchy, external memory algorithm, Set associative cache
2	Philip Machanick, Pierre Salverda, Lance Pompe	Hardware-Software Trade-Offs in a Direct Rambus Implementation of the RAMpage Memory Hierarchy.	ASPLOS	1998	DBLP DOI BibTeX RDF
2	Bo Kågström, Per Ling, Charles Van Loan	GEMM-based level 3 BLAS: high-performance model implementations and performance evaluation benchmark.	ACM Trans. Math. Softw.	1998	DBLP DOI BibTeX RDF	GEMM-based level 3 BLAS, matrix-matrix kernels, parallelization, memory hierarchy, vectorization, FORTRAN 77, blocked algorithms
2	W. Lynn Gallagher, Chuan-lin Wu	Evaluation of a memory hierarchy for the MTS multithreaded processor. (PDF / PS)	ICPADS	1997	DBLP DOI BibTeX RDF	memory hierarchy evaluation, MTS multithreaded processor, hardware resource utilization, instruction throughput, multithreaded superscalar processor, multiple instruction streams, multiple functional unit architecture, parameter-driven simulator, SES/workbench, numerical benchmarks, memory system configurations, main memory latency, cache hit rates, realistic multilevel cache hierarchy, parallel processing, VLIW, superscalar processor, instruction cache
2	Andreas Moshovos, Gurindar S. Sohi	Streamlining Inter-Operation Memory Communication via Data Dependence Prediction.	MICRO	1997	DBLP BibTeX RDF	DEF-store-load-USE chains, address disambiguation, data cache access, data cache bandwidth requirements, data dependence prediction, inter-operation memory communication, memory dependences, memory hierarchy design, transient value cache, storage management, memory architecture, communication latency, instruction window, address calculation
2	Henk L. Muller, Paul W. A. Stallard, David H. D. Warren	The Role of Associative Memory in Virtual Shared Memory Architectures: A Price-Performance Comparison.	PDP	1996	DBLP DOI BibTeX RDF	virtual shared memory architectures, price-performance, set associative memory, large coherent cache, performance evaluation, benchmarks, parallel machines, memory hierarchy, shared memory systems, costing, cost, associative memory, memory architecture, content-addressable storage, application specific, virtual storage, CC-NUMA, COMA, miss ratios
2	Arun K. Nanda, Lionel M. Ni	MAD Kernels: An Experimental Testbed to Study Multiprocessor Memory System Behavior.	IEEE Trans. Parallel Distrib. Syst.	1996	DBLP DOI BibTeX RDF	memory access patterns, Performance evaluation, interconnection networks, memory hierarchy, shared-memory multiprocessors, resource contention, synchronization overhead
2	Wesley K. Kaplow, William Maniatty, Boleslaw K. Szymanski	Impact of memory hierarchy on program partitioning and scheduling.	HICSS	1995	DBLP DOI BibTeX RDF	parallel program scheduling, nonlinear cache-miss rates, loop nest execution simulation, architecturally parameterized cache simulator, loop range, cache-miss ratio, loop interchange, iteration-space blocking, program runtime estimation, IBM 9076 SP1, SuperSPARC, scheduling, parallel programming, optimisation, memory hierarchy, processor scheduling, software performance evaluation, memory architecture, cache storage, program optimization, cache performance, program control structures, program partitioning, Intel i860
2	Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia	Fast discrete function evaluation using decision diagrams.	ICCAD	1995	DBLP DOI BibTeX RDF	address lookups, cycle-based logic simulation, decision-diagram based function evaluation, fast discrete function evaluation, latch ports, orders-of-magnitude potential speedup, output ports, logic design, memory hierarchy, logic CAD, decision theory, circuit analysis computing, memory bandwidth, table lookup, digital circuits, logic simulators, logic function, function evaluation, multi-valued decision diagrams
2	Xiaohan Qin, Jean-Loup Baer	A comparative study of conservative and optimistic trace-driven simulations.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	optimistic trace-driven simulations, conservative trace-driven simulations, parallel trace driven simulation, parallel simulation schemes, shared references, Time Warp like algorithm, debugging effort, general architectural simulation, optimistic scheme, parallel algorithms, parallel architectures, virtual machines, multiprocessing systems, multiprocessor systems, memory hierarchy, memory architecture, comparative study, time warp simulation
2	Timothy J. Stanley, Trevor N. Mudge	Systematic objective-driven computer architecture optimization.	ARVLSI	1995	DBLP DOI BibTeX RDF	objective-driven optimization, microarchitectural configuration, directed search problem, genetic algorithms, genetic algorithm, CAD, computer-aided design, computer architecture, computer architecture, memory hierarchy, search problems, memory architecture, dimensionality
2	Zhiyong Li 0002, Peter Mills, John H. Reif	Models and resource metrics for parallel and distributed computation.	HICSS	1995	DBLP DOI BibTeX RDF	resource metrics, architectural details, generic parameters, network communication costs, LogP-HMM model, parameterized network model, sequential hierarchical memory model, multilevel memory, local cache, near-optimal sorting, parallel processing, parallel computation, distributed algorithms, distributed computation, resource allocation, sorting, fast Fourier transforms, parallel machines, memory hierarchy, cache storage, design principles, asynchrony, parallel models, input/output, synchronous models, fast Fourier transform algorithms
2	Gyungho Lee	An assessment of COMA multiprocessors. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	Cache Only Memory Architecture, Perfect Club Benchmark Suite, coherence policy, performance evaluation, performance, discrete event simulation, memory hierarchy, shared memory systems, distributed memory systems, update, trace driven simulations, cache storage, network traffic, miss ratio, distributed shared memory multiprocessors, shared address space, invalidate
2	Yang-Woo Kim, Sei-Woong Oh, Jin-Won Park	Design issues and the system architecture of TICOM-IV, a highly parallel commercial computer.	PDP	1995	DBLP DOI BibTeX RDF	TICOM-IV, highly parallel commercial computer, parallel commercial computer design, area analysis, performance scalability, performance evaluation, scalability, parallel architectures, virtual machines, availability, system design, parallel machines, network topology, memory hierarchy, reconfigurable architectures, system architecture, system performance
2	Bob Janssens, W. Kent Fuchs	The Performance of Cache-Based Error Recovery in Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	cache-based error recovery performance, cache-based checkpointing, rollback error recovery, shared-memorymultiprocessors, inherent redundancy, computation state, rollback propagation, EncoreMultimax, recovery schemes, cache-based schemes, low performance overhead, checkpoint interval, performance evaluation, performance evaluation, virtual machines, multiprocessors, redundancy, memory hierarchy, shared memory systems, system recovery, buffer storage, parallel applications, cache coherence protocol, transient errors, cache replacement policy, address traces
2	Terry A. Welch	Memory Hierarchy Configuration Analysis.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	speed-cost tradeoffs, Access time minimization, memory access probabilities, memory hierarchy analysis, memory performance bounds, memory systems