Search results for "memory modules"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Vincenzo Auletta, Amelia De Vivo, Vittorio Scarano	Multiple Templates Access of Trees in Parallel Memory Systems. (PDF / PS)	IPPS	1997	DBLP DOI BibTeX RDF	multiple template access, node mapping algorithms, subtree templates, root-to-leaf path templates, preprocessing phase, data structure, time complexity, tree data structures, load, complete binary trees, conflict-free access, parallel access, memory modules, parallel memory systems
2	A. M. del Corral, José M. Llabería	Access order to avoid inter-vector-conflicts in complex memory systems. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	access order, inter-vector-conflicts, complex memory systems, vector processor accessing vectors, concurrent memory access, inter-conflicts, performance evaluation, performance, vector processor systems, memory subsystem, memory modules
2	Chita R. Das, Prasant Mohapatra, Lei Tien, Laxmi N. Bhuyan	An Availability Model for MIN-Based Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	1993	DBLP DOI BibTeX RDF	MIN-based multiprocessors, task-based availability, HARP, steady state availabilities, transient availabilities, simulation, multiprocessor interconnection networks, Markov processes, multistage interconnection network, software package, processing elements, memory modules, availability model
2	Imadeldin O. Mahgoub, Ahmed K. Elmagarmid	Performance Analysis of a Generalized Class of M-Level Hierarchical Multiprocessor Systems.	IEEE Trans. Parallel Distrib. Syst.	1992	DBLP DOI BibTeX RDF	hierarchical multiprocessor systems, system bandwidth, hierarchically nonuniform reference, local requests, m-level system, crossbar system, performance evaluation, performance analysis, probability, multiprocessing systems, multiprocessorinterconnection networks, memory modules, multiple-bus system
1	Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama	Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Chinguo Kuo, Jen-Jun Chen	Development of a novel stack package to fabricate high density memory modules for high-end application.	Microelectronics Reliability	2010	DBLP DOI BibTeX RDF
1	Sanjeev Kumar, Alvaro Munoz	Comparison of Memory Assignment Schemes for Switch Architectures with Shareable Parallel Memory Modules.	J. Electrical and Computer Engineering	2010	DBLP DOI BibTeX RDF
1	Paul Vincent Mejia, Rajeevan Amirtharajah, Matthew K. Farrens, Venkatesh Akella	Performance Evaluation of a Multicore System with Optically Connected Memory Modules.	NOCS	2010	DBLP DOI BibTeX RDF	OC-DIMM, DWDM, Performance Evaluation, DRAM, Optics
1	Lan Luo, Qionghai Dai, Zhiguang Qin, Chunxiang Xu	Golden Fish: An Intelligent Stream Cipher Fuse Memory Modules.	IACR Cryptology ePrint Archive	2009	DBLP BibTeX RDF
1	Bithika Khargharia, Salim Hariri, Mazin S. Yousif	An Adaptive Interleaving Technique for Memory Performance-per-Watt Management.	IEEE Trans. Parallel Distrib. Syst.	2009	DBLP DOI BibTeX RDF
1	Aydin O. Balkan, Gang Qu, Uzi Vishkin	An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing.	DAC	2008	DBLP DOI BibTeX RDF	hybrid networks, on-chip networks, mesh-of-trees
1	Meikang Qiu, Jiande Wu	Energy saving for memory with loop scheduling and prefetching.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	multi-module memory, probability, partition, low power design, prefetching, loop scheduling
1	Arseni Vitkovski, Georgi Kuzmanov, Georgi Gaydadjiev	Memory Organization with Multi-Pattern Parallel Accesses.	DATE	2008	DBLP DOI BibTeX RDF
1	Masanori Hariyama, Kensaku Yamashita, Michitaka Kameyama	FPGA implementation of a vehicle detection algorithm using three-dimensional information.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Lukasz Masko, Marek Tudruj	Task Scheduling for SoC-Based Dynamic SMP Clusters with Communication on the Fly.	ISPDC	2008	DBLP DOI BibTeX RDF
1	Jarno Vanne, Eero Aho, Timo D. Hämäläinen, Kimmo Kuusilinna	A Parallel Memory System for Variable Block-Size Motion Estimation Algorithms.	IEEE Trans. Circuits Syst. Video Techn.	2008	DBLP DOI BibTeX RDF
1	Eero Aho, Jarno Vanne, Timo D. Hämäläinen	Configurable Data Memory for Multimedia Processing.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	stride access, configurable, parallel memory, skewing scheme, SIMD processing
1	Pilar Reyes, Pedro Reviriego, Juan Antonio Maestro, Oscar Ruano	Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	single event upsets (SEUs), multiple bit upsets (MBUs), fault tolerance, redundancy, soft errors, interleaving
1	Masahiko Omura, Toshiki Kanamoto, Michiko Tsukamoto, Mitsutoshi Shirota, Takashi Nakajima, Masayuki Terai	A Fast Characterizing Method for Large Embedded Memory Modules on SoC.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Chunyue Liu, Xiaolang Yan, Xing Qin	An optimized linear skewing interleave scheme for on-chip multi-access memory systems.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	interleave scheme, linear skewing, multi-access memory
1	Piti Piyachon, Yan Luo	Compact State Machines for High Performance Pattern Matching.	DAC	2007	DBLP DOI BibTeX RDF
1	William J. Dally	Interconnect-Centric Computing.	HPCA	2007	DBLP DOI BibTeX RDF
1	Abhishek Das, William J. Dally	Stream Scheduling: A Framework to Manage Bulk Operations in a Memory Hierarchy.	PACT	2007	DBLP DOI BibTeX RDF
1	Marek Tudruj, Lukasz Masko	Dynamic SMP Clusters with Communication on the Fly in SoC Technology Applied for Medium-Grain Parallel Matrix Multiplication.	PDP	2007	DBLP DOI BibTeX RDF
1	T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan	MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Gennaro Cordasco, Vittorio Scarano, Arnold L. Rosenberg	Bounded-Collision Memory-Mapping Schemes for Data Structures with Applications to Parallel Memories.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF	data structures for parallel systems, bounded-conflict parallel memory access, data structures, parallel architectures, parallel systems, data mapping, graph labeling, Parallel memory systems
1	Bithika Khargharia, Salim Hariri, Mazin S. Yousif	Self-optimization of Performance-per-Watt for Interleaved Memory Systems.	HiPC	2007	DBLP DOI BibTeX RDF
1	Jarno K. Tanskanen, Teemu Pitkänen, Risto Mäkinen, Jarmo Takala	Parallel Memory Architecture for TTA Processor.	SAMOS	2007	DBLP DOI BibTeX RDF
1	Frederick A. Ware, Craig Hampel	Improving Power and Data Efficiency with Threaded Memory Modules.	ICCD	2006	DBLP BibTeX RDF
1	Hongwei Zhu, Ilie I. Luican, Florin Balasa	Memory size computation for multimedia processing applications.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Esmail Amini, Mehrdad Najibi, Hossein Pedram	Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock Gating.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi	Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Lukasz Masko, Gregory Mounie, Denis Trystram, Marek Tudruj	Program Graph Structuring for Execution in Dynamic SMP Clusters Using Moldable Tasks.	PARELEC	2006	DBLP DOI BibTeX RDF
1	Adam Smyk, Marek Tudruj, Lukasz Masko	Open MP Extension for Multithreaded Computing with Dynamic SMP Processor Clusters with Communication on the Fly.	PARELEC	2006	DBLP DOI BibTeX RDF
1	Eero Aho, Jarno Vanne, Timo D. Hämäläinen	Parallel Memory Implementation for Arbitrary Stride Accesses.	ICSAMOS	2006	DBLP DOI BibTeX RDF
1	Abraham Gutierrez, Luis Fernández, Fernando Arroyo, Victor J. Martínez	Design of a Hardware Architecture Based on Microcontrollers for the Implementation of Membrane Systems.	SYNASC	2006	DBLP DOI BibTeX RDF
1	Martti Forsell	Realising constant time parallel algorithms with active memory modules.	IJEB	2005	DBLP DOI BibTeX RDF
1	Sanjeev Kumar, Alvaro Munoz	Performance comparison of switch architectures with shareable parallel memory modules.	IEEE Communications Letters	2005	DBLP DOI BibTeX RDF
1	Ozcan Ozturk, Mahmut T. Kandemir	Energy management in software-controlled multi-level memory hierarchies.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	software-managed memory, embedded systems
1	Wim Heirman, Joni Dambre, Jan Van Campenhout, Christof Debaes, Hugo Thienpont	Traffic Temporal Analysis for Reconfigurable Interconnects in Shared-Memory Systems.	IPDPS	2005	DBLP DOI BibTeX RDF
1	Lukasz Masko	Task Scheduling for Dynamic SMP Clusters with Communication on the Fly for Bounded Number of Resources.	ISPDC	2005	DBLP DOI BibTeX RDF
1	Christianto C. Liu, Ilya Ganusov, Martin Burtscher, Sandip Tiwari	Bridging the Processor-Memory Performance Gapwith 3D IC Technology.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	three-dimensional integration 3-D ICs microprocessor cache design stream prefetching embedded DRAM
1	Tuomas Järvinen, Perttu Salmela, Teemu Sipilä, Jarmo Takala	Systematic approach for path metric access in Viterbi decoders.	IEEE Transactions on Communications	2005	DBLP DOI BibTeX RDF
1	Lukasz Masko	Scheduling Task Graphs for Execution in Dynamic SMP Clusters with Bounded Number of Resources.	PPAM	2005	DBLP DOI BibTeX RDF
1	Marek Tudruj, Lukasz Masko	Dynamic SMP Clusters in SoC Technology - Towards Massively Parallel Fine Grain Numerics.	PPAM	2005	DBLP DOI BibTeX RDF
1	Orna Grumberg, Tamir Heyman, Assaf Schuster	Distributed Symbolic Model Checking for µ-Calculus.	Formal Methods in System Design	2005	DBLP DOI BibTeX RDF	model checking, distributed, hardware verification, symbolic, Mu-calculus
1	Jarno K. Tanskanen, Reiner Creutzburg, Jarkko Niittylahti	On Design of Parallel Memory Access Schemes for Video Coding.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	parallel memory access, SIMD memory architecture, video coding, MPEG-4, H.263, subword parallelism, conflict-free access, storage scheme, skewing scheme, data alignment
1	Qingfeng Zhuge, Edwin Hsing-Mean Sha, Bin Xiao, Chantana Chantrapornchai	Efficient variable partitioning and scheduling for DSP processors with multiple memory modules.	IEEE Transactions on Signal Processing	2004	DBLP DOI BibTeX RDF
1	Darren J. Kerbyson, Michael Lang 0003, Gene Patino, Hossein Amidi	An empirical performance analysis of commodity memories in commodity servers.	Memory System Performance	2004	DBLP DOI BibTeX RDF	performance analysis, performance measurement, memory modules, memory system performance
1	Jayaprakash Pisharath, Alok N. Choudhary, Mahmut T. Kandemir	Energy management schemes for memory-resident database systems.	CIKM	2004	DBLP DOI BibTeX RDF	hardware energy scheme, multiquery optimization, query-directed energy management, database, energy, power consumption, DRAM
1	Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen	A compact DSP core with static floating-point unit & its microcode generation.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	DSP core, digital signal processor, floating-point units
1	Baruch Awerbuch, Christian Scheideler	Consistent and compact data management in distributed storage systems.	SPAA	2004	DBLP DOI BibTeX RDF	load balancing, peer-to-peer systems, range queries, distributed data management
1	Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima	Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor.	FCCM	2004	DBLP DOI BibTeX RDF
1	Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich	Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration.	IPDPS	2004	DBLP DOI BibTeX RDF	Virtex, Compression, Decompression
1	Sajal K. Das, Irene Finocchi, Rossella Petreschi	Star-Coloring of Graphs for Conflict-Free Access to Parallel Memory Systems.	IPDPS	2004	DBLP DOI BibTeX RDF
1	Marek Tudruj, Lukasz Masko	Dynamic SMP Clusters with Communication on the Fly in NoC Technology for Very Fine Grain Computations.	ISPDC/HeteroPar	2004	DBLP DOI BibTeX RDF	Parallel System Architecture, Shared Memory Systems, Cluster Systems
1	Mark A. Franklin, Vinayak Joshi	SimplePipe: A Simulation Tool for Task Allocation and Design of Processor Pipelines with Application to Network Processors.	MASCOTS	2004	DBLP DOI BibTeX RDF
1	Lukasz Masko	Program Graph Scheduling for SMP Clusters with Communication on-the-Fly Based on Extended DS Approach.	PARELEC	2004	DBLP DOI BibTeX RDF
1	Marek Tudruj, Lukasz Masko	Fine-Grain Numerical Computations in Dynamic SMP Clusters with Communication on the Fly.	PARELEC	2004	DBLP DOI BibTeX RDF
1	Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan	Synthesis of Application Specific Multiprocessor Architectures for Process Networks.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Victor De La Luz, Mahmut T. Kandemir	Array Regrouping and Its Use in Compiling Data-Intensive Embedded Applications.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Array regrouping, memory energy consumption, embedded systems, cache locality, layout optimizations
1	Jong Won Park	Multiaccess Memory System for Attached SIMD Computer.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	prime memory system, multiaccess memory system, conflict-free memory system, routing circuit, SIMD computer, address calculation
1	Danian Gong, Yun He, Zhigang Cao	New cost-effective VLSI implementation of a 2-D discrete cosine transform and its inverse.	IEEE Trans. Circuits Syst. Video Techn.	2004	DBLP DOI BibTeX RDF
1	Jarno K. Tanskanen, Tero Sihvo, Jarkko Niittylahti	Byte and modulo addressable parallel memory architecture for video coding.	IEEE Trans. Circuits Syst. Video Techn.	2004	DBLP DOI BibTeX RDF
1	Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis	Visual Data Rectangular Memory.	Euro-Par	2004	DBLP DOI BibTeX RDF
1	Sanjeev Kumar	The sliding-window packet switch: a new class of packet switch architecture with plural memory modules and decentralized control.	IEEE Journal on Selected Areas in Communications	2003	DBLP DOI BibTeX RDF
1	Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex	Global interconnect trade-off for technology over memory modules to application level: case study.	SLIP	2003	DBLP DOI BibTeX RDF	Pareto-optimal energy/delay interconnect exploration, interconnect wire processing, intra/inter-memory interconnect
1	Hossam A. ElGindy, George Ferizis	On hiding latency in reconfigurable systems: the case of merge-sort for an FPGA-based system.	FPGA	2003	DBLP DOI BibTeX RDF
1	Peter Grun, Nikil D. Dutt, Alexandru Nicolau	Access pattern-based memory and connectivity architecture exploration.	ACM Trans. Embedded Comput. Syst.	2003	DBLP DOI BibTeX RDF	Memory, access patterns, architecture exploration
1	Jarmo Takala, Tuomas Järvinen, Harri Sorokin	Conflict-free parallel memory access scheme for FFT processors.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Minsu Choi, Noh-Jin Park, K. M. George, Byoungjae Jin, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi	Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems. (PDF / PS)	NCA	2003	DBLP DOI BibTeX RDF	Built-in-self-repair (BISR), Field Reconfiguration, HW/SW Co-reliability, Reliability Assurance, Reliability, High performance computing, Yield, Massively parallel computing, Fault-tolerant memory, Modular Redundancy
1	Gennaro Cordasco, Alberto Negro, Vittorio Scarano, Arnold L. Rosenberg	c-Perfect Hashing Schemes for Binary Trees, with Applications to Parallel Memories.	Euro-Par	2003	DBLP DOI BibTeX RDF
1	Christof Krick, Harald Räcke, Matthias Westermann	Approximation Algorithms for Data Management in Networks.	Theory Comput. Syst.	2003	DBLP DOI BibTeX RDF
1	Jayaprakash Pisharath, Alok N. Choudhary	An integrated approach to reducing power dissipation in memory hierarchies.	CASES	2002	DBLP DOI BibTeX RDF	RDRAM, dynamic cache, energy-saver buffers (ESB), power, integrated approach, energy-delay product
1	Victor Delaluz, Anand Sivasubramaniam, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin	Scheduler-based DRAM energy management.	DAC	2002	DBLP DOI BibTeX RDF	scheduler, operating systems, energy management, DRAM, energy estimation
1	Pedro C. Diniz, Joonseok Park	Data reorganization engines for the next generation of system-on-a-chip FPGAs.	FPGA	2002	DBLP DOI BibTeX RDF	field-programmable-gate-arrays (FPGAs), high-level synthesis, data reorganization
1	Sriram Swaminathan, Russell Tessier, Dennis Goeckel, Wayne Burleson	A dynamically reconfigurable adaptive viterbi decoder.	FPGA	2002	DBLP DOI BibTeX RDF	field-programmable-gate-arrays (FPGAs), high-level synthesis, data reorganization
1	Hassan Rabah, Hervé Mathias, Eril Mozef, Domingo Torres, Serge Weber	Linear array processors with multiple access modes memory for real-time image processing.	APCCAS	2002	DBLP DOI BibTeX RDF
1	Peter Grun, Nikil D. Dutt, Alexandru Nicolau	Memory System Connectivity Exploration.	DATE	2002	DBLP DOI BibTeX RDF
1	Minsu Choi, Nohpill Park, Fabrizio Lombardi	Hardware-Software Co-Reliability in Field Reconfigurable Multi-Processor-Memory Systems. (PDF / PS)	IPDPS	2002	DBLP DOI BibTeX RDF	Multi-Processor-Memory System, Field Reconfiguration, HW/SW Co-reliability, Modular Redundancy
1	Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha	Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP. (PDF / PS)	IPDPS	2002	DBLP DOI BibTeX RDF
1	Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha	Performance optimization of multiple memory architectures for DSP.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam, Ibrahim Kolcu	Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories.	VLSI Design	2002	DBLP DOI BibTeX RDF
1	Martti Forsell	A Scalable High-Performance Computing Solution for Networks on Chips.	IEEE Micro	2002	DBLP DOI BibTeX RDF
1	Der-Cheng Huang, Wen-Ben Jone	A parallel built-in self-diagnostic method for embedded memoryarrays.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Vincenzo Auletta, Sajal K. Das, Amelia De Vivo, Maria Cristina Pinotti, Vittorio Scarano	Optimal Tree Access by Elementary and Composite Templates in Parallel Memory Systems.	IEEE Trans. Parallel Distrib. Syst.	2002	DBLP DOI BibTeX RDF	complete trees, composite templates, elementary templates, mapping scheme, conflict-free access, parallel memory system
1	Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee	An efficient BIST method for distributed small buffers.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Preeti Ranjan Panda, Nikil D. Dutt	Memory Architectures for Embedded Systems-On-Chip.	HiPC	2002	DBLP DOI BibTeX RDF
1	Wei-Je Huang, Edward J. McCluskey	A memory coherence technique for online transient error recovery of FPGA configurations.	FPGA	2001	DBLP DOI BibTeX RDF	fault tolerance, FPGA, error recovery, memory coherence
1	Christof Krick, Harald Räcke, Matthias Westermann	Approximation algorithms for data management in networks.	SPAA	2001	DBLP DOI BibTeX RDF
1	Mohsen Guizani, Ala I. Al-Fuqaha	New Queuing Strategy for Large Scale ATM Switches.	Annual Simulation Symposium	2001	DBLP DOI BibTeX RDF
1	Jun Cao, Belle W. Y. Wei, Jie Cheng	High-Performance Architectures for Elementary Function Generation.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
1	Marco Ottavi, Gian-Carlo Cardarilli, P. Marinucci, Salvatore Pontarelli, Adelio Salsano	Development of a dynamic routing system for a fault tolerant solid state mass memory.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Wen-Tsong Shiue	Energy efficient memory assignment.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das	A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers.	VLSI Design	2001	DBLP DOI BibTeX RDF
1	Farzan Fallah, Srinivas Devadas, Kurt Keutzer	Functional vector generation for HDL models using linearprogramming and Boolean satisfiability.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	V. Carl Hamacher, Hong Jiang	Hierarchical Ring Network Configuration and Performance Modeling.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	hierarchical rings, message-passing performance, Interconnection networks, shared-memory multiprocessors, queuing models, slotted rings
1	Jong Won Park	An Efficient Buffer Memory System for Subarray Access.	IEEE Trans. Parallel Distrib. Syst.	2001	DBLP DOI BibTeX RDF	High-resolution graphical display, buffer memory system, block access, address routing, memory module selection, image processing, address calculation
1	Orna Grumberg, Tamir Heyman, Assaf Schuster	Distributed Symbolic Model Checking for µ-Calculus.	CAV	2001	DBLP DOI BibTeX RDF
1	Marek Tudruj, Lukasz Masko	An Architecture and Task Scheduling Algorithm for Systems Based on Dynamically Reconfigurable Shared Memory Clusters.	IWCC	2001	DBLP DOI BibTeX RDF