Search results for "memory optimization"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Yiannis Iosifidis, Arindam Mallik, Stylianos Mamagkakis, Eddy de Greef, Alexandros Bartzas, Dimitrios Soudris, Francky Catthoor	A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms.	DAC	2010	DBLP DOI BibTeX RDF	embedded systems, MPSoC, memory optimization
2	Bruno Girodias, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Pierre G. Paulin, Bruno Lavigueur	Multiprocessor, Multithreading and Memory Optimization for On-Chip Multimedia Applications.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Multiprocessors System on Chip (MPSoC), Optimizations, Multimedia, Parallelism, Memory, Multi-threading
2	Pingjing Lu, Yonggang Che, Zhenghua Wang	A Framework for Effective Memory Optimization of High Performance Computing Applications.	HPCC	2009	DBLP DOI BibTeX RDF
2	Tao Sheng, Mudar Sarem, Jingli Zhou, Shuai Hu	Memory Optimization for Embedded Systems Running H.264/AVC Video Encoder.	ICPP Workshops	2007	DBLP DOI BibTeX RDF
2	Sang-Il Han, Xavier Guerin, Soo-Ik Chae, Ahmed Amine Jerraya	Buffer memory optimization for video codec application modeled in Simulink.	DAC	2006	DBLP DOI BibTeX RDF	memory size reduction, video codec application, Simulink
2	Florian Marteil, Nathalie Julien, Eric Senn, Eric Martin	A Complete Methodology for Memory Optimization in DSP Applications.	DSD	2004	DBLP DOI BibTeX RDF
2	David Whelihan, Herman Schmit	Memory optimization in single chip network switch fabrics.	DAC	2002	DBLP DOI BibTeX RDF	network switch, SOC, memory optimization
2	Curt Schurgers, Francky Catthoor, Marc Engels	Memory optimization of MAP turbo decoder algorithms.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong	An integrated and automated memory optimization flow for FPGA behavioral synthesis.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Tarik Saidani, Lionel Lacassagne, Joel Falcou, Claude Tadonki, Samir Bouaziz	Parallelization Schemes for Memory Optimization on the Cell Processor: A Case Study on the Harris Corner Detector.	T. HiPEAC	2011	DBLP DOI BibTeX RDF
1	Duy Le, Haining Wang	An Effective Memory Optimization for Virtual Machine-Based Systems.	IEEE Trans. Parallel Distrib. Syst.	2011	DBLP DOI BibTeX RDF	security, virtual machine, Memory management
1	Ferrante Neri, Giovanni Iacca, Ernesto Mininno	Disturbed Exploitation compact Differential Evolution for limited memory optimization problems.	Inf. Sci.	2011	DBLP DOI BibTeX RDF
1	Vladimir Yanakiev, Elena Paunova	Static memory optimization by clustering and neural networks in embedded devices.	CompSysTech	2011	DBLP DOI BibTeX RDF
1	Dhruva R. Chakrabarti, Prithviraj Banerjee, Hans-Juergen Boehm, Pramod G. Joisha, Robert S. Schreiber	The runtime abort graph and its application to software transactional memory optimization.	CGO	2011	DBLP DOI BibTeX RDF
1	Seokjoong Kim, Matthew R. Guthaus	Low-power multiple-bit upset tolerant memory optimization.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Byunghyun Jang, Dana Schaa, Perhaad Mistry, David R. Kaeli	Exploiting Memory Access Patterns to Improve Memory Performance in Data-Parallel Architectures.	IEEE Trans. Parallel Distrib. Syst.	2011	DBLP DOI BibTeX RDF	General-purpose computation on GPUs (GPGPUs), memory access pattern, memory selection, memory coalescing, data-parallel architectures, vectorization, data parallelism, memory optimization, GPU computing
1	Yi Yang, Ping Xiang, Jingfei Kong, Huiyang Zhou	A GPGPU compiler for memory optimization and parallelism management.	PLDI	2010	DBLP DOI BibTeX RDF	compiler, gpgpu
1	Bruno Girodias, Luiza Gheorghe, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Michel Langevin, Pierre G. Paulin	Combining memory optimization with mapping of multimedia applications for multi-processors system-on-chip.	International Symposium on Rapid System Prototyping	2010	DBLP DOI BibTeX RDF
1	Yi He, Ju Ren, Mei Wen, Qianming Yang, Nan Wu 0003, Chunyuan Zhang	Software Managed Instruction Scratchpad Memory Optimization in Stream Architecture Based on Hot Code Analysis of Kernels.	DSD	2010	DBLP DOI BibTeX RDF
1	Yaqiong Li, Yongbing Huang	TMemCanal: A VM-oblivious Dynamic Memory Optimization Scheme for Virtual Machines in Cloud Computing.	CIT	2010	DBLP DOI BibTeX RDF	under-loaded memory, Xen
1	Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John	The virtual write queue: coordinating DRAM and last-level cache policies.	ISCA	2010	DBLP DOI BibTeX RDF	cmp many-core, ddr ddr2 ddr3, dram-parameters, memory-scheduling writeback, page-mode, write-queue, write-scheduling, dram, cache-replacement, last-level-cache
1	Peng Wu, Maged M. Michael, Christoph von Praun, Takuya Nakaike, Rajesh Bordawekar, Harold W. Cain, Calin Cascaval, Siddhartha Chatterjee, Stefanie Chiras, Rui Hou, Mark F. Mergen, Xiaowei Shen, Michael F. Spear, Huayong Wang, Kun Wang	Compiler and runtime techniques for software transactional memory optimization.	Concurrency and Computation: Practice and Experience	2009	DBLP DOI BibTeX RDF
1	Shang-Te Yang, Tsung-Kai Lin, Shao-Yi Chien	Real-time Motion Estimation for 1080p videos on graphics processing units with shared memory optimization.	SiPS	2009	DBLP DOI BibTeX RDF
1	Juraj Blaho, Jan Korenek, Viktor Pus	Memory optimization for packet classification algorithms.	ANCS	2009	DBLP DOI BibTeX RDF
1	Maryam Moazeni, Alex A. T. Bui, Majid Sarrafzadeh	A memory optimization technique for software-managed scratchpad memory in GPUs.	SASP	2009	DBLP DOI BibTeX RDF
1	Kong Woei Susanto, Tim Todman, José Gabriel F. Coutinho, Wayne Luk	Design Validation by Symbolic Simulation and Equivalence Checking: A Case Study in Memory Optimization for Image Manipulation.	SOFSEM	2009	DBLP DOI BibTeX RDF
1	Erick Amador, Renaud Pacalet, Vincent Rezard	Optimum LDPC decoder: a memory architecture problem.	DAC	2009	DBLP DOI BibTeX RDF	memory optimization, LDPC codes, low power architectures
1	Serge Burckel, Emeric Gioan, Emmanuel Thomé	Mapping Computation with No Memory.	UC	2009	DBLP DOI BibTeX RDF	mapping computation, boolean mapping, linear mapping, processor optimization, multistage interconnection network, circuit design, memory optimization, butterfly, program design, rearrangeability
1	Bert Geelen, Vissarion Ferentinos, Francky Catthoor, Spyridon Toulatos, Gauthier Lafruit, Thanos Stouraitis, Rudy Lauwereins, Diederik Verkest	Exploiting Varying Resource Requirements in Wavelet-based Applications in Dynamic Execution Environments.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Wavelets, Dynamism, Loop transformations, Memory optimization
1	Geoffrey Belter, Elizabeth R. Jessup, Ian Karlin, Jeremy G. Siek	Automating the generation of composed linear algebra kernels.	SC	2009	DBLP DOI BibTeX RDF
1	Yong Dou, Guiming Wu, Jinhui Xu, Xingming Zhou	A coarse-grained reconfigurable computing architecture with loop self-pipelining.	Science in China Series F: Information Sciences	2009	DBLP DOI BibTeX RDF	reconfigurable computing, data driven, loop pipelining, register promotion
1	Yong Dou, Lin Deng, Jinhui Xu, Yi Zheng	DMA Performance Analysis and Multi-core Memory Optimization for SWIM Benchmark on the Cell Processor.	ISPA	2008	DBLP DOI BibTeX RDF
1	Ozcan Ozturk, Mahmut T. Kandemir, Guangyu Chen	Access pattern-based code compression for memory-constrained systems.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	CFG, code access pattern, Embedded systems, code compression, memory optimization
1	Bita Gorjiara, Mehrdad Reshadi, Daniel Gajski	Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs.	TRETS	2008	DBLP DOI BibTeX RDF	Microcoded architectures, dictionary based compression, no-instruction-set computer, FPGA, memory optimization
1	Wenda Wang, Yanling Hao	A Wavelet Embedded Block Coding Method Based on Low-Memory and Bit-Length Search.	PACIIA	2008	DBLP DOI BibTeX RDF	Embedded block coding, Bit-length chart, Bit-length search, Low-memory optimization
1	Udai Shanker, Manoj Misra, Anil Kumar Sarje	Distributed real time database systems: background and literature review.	Distributed and Parallel Databases	2008	DBLP DOI BibTeX RDF	Distributed real time commit protocol, Priority assignment policy, Replication, Memory optimization, Distributed transaction processing
1	Per Gunnar Kjeldsberg, Francky Catthoor, Sven Verdoolaege, Martin Palkovic, Arnout Vandecappelle, Qubo Hu, Einar J. Aas	Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	Memory architecture exploration, High level synthesis, Memory optimization, Multi-media, Code transformation
1	Yijian Bai, Carlo Zaniolo	Minimizing latency and memory in DSMS: a unified approach to quasi-optimal scheduling.	SSPS	2008	DBLP DOI BibTeX RDF	data stream management systems, operator scheduling
1	Sujan Pandey, Rolf Drechsler	Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs.	DATE	2008	DBLP DOI BibTeX RDF
1	Jeremy G. Siek, Ian Karlin, Elizabeth R. Jessup	Build to order linear algebra kernels.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Jason Cong	A new generation of C-base synthesis tool and domain-specific computing.	SoCC	2008	DBLP DOI BibTeX RDF
1	Yongsoo Joo, Yongseok Choi, Jaehyun Park, Chanik Park, Sung Woo Chung, Eui-Young Chung, Naehyuck Chang	Energy and Performance Optimization of Demand Paging With OneNAND Flash.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozorgzadeh	Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Youcef Bouchebaba, Bruno Girodias, Gabriela Nicolescu, El Mostapha Aboulhamid, Bruno Lavigueur, Pierre G. Paulin	MPSoC memory optimization using program transformation.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	embedded systems, data cache, Data locality, compiler transformations
1	Xipeng Shen, Yutao Zhong, Chen Ding	Predicting locality phases for dynamic memory optimization.	J. Parallel Distrib. Comput.	2007	DBLP DOI BibTeX RDF
1	Chih-Chi Cheng, Chao-Tsung Huang, Ching-Yeh Chen, Chung-Jr Lian, Liang-Gee Chen	On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform.	IEEE Trans. Circuits Syst. Video Techn.	2007	DBLP DOI BibTeX RDF
1	Manish Verma, Peter Marwedel	Advanced memory optimization techniques for low-power embedded processors.		2007	RDF
1	Youcef Bouchebaba, Bruno Lavigueur, Bruno Girodias, Gabriela Nicolescu, Pierre G. Paulin	MPSoC memory optimization for digital camera applications.	DSD	2007	DBLP DOI BibTeX RDF
1	Marwan S. Sleiman, Lester Lipsky	Multi-tier data access and hierarchical memory optimization.	ISCA PDCS	2007	DBLP BibTeX RDF
1	Jiwon Hahn, Pai H. Chou	Buffer optimization and dispatching scheme for embedded systems with behavioral transparency.	EMSOFT	2007	DBLP DOI BibTeX RDF	behavioral transparency, model of computation, runtime system, memory optimization, component software, buffer allocation
1	Bita Gorjiara, Daniel Gajski	FPGA-friendly code compression for horizontal microcoded custom IPs.	FPGA	2007	DBLP DOI BibTeX RDF	dictionary-based compression, microcoded architectures, no-instruction-set computer, FPGA, memory optimization
1	Nathan Cooprider, John Regehr	Offline compression for on-chip ram.	PLDI	2007	DBLP DOI BibTeX RDF	sensor networks, static analysis, data compression, embedded software, TinyOS, memory optimization
1	Hongbin Zhu, Kai Bao, Enhua Wu, Xuehui Liu	Stable and efficient miscible liquid-liquid interactions.	VRST	2007	DBLP DOI BibTeX RDF	miscible mixture, subgrid model, stability, control, memory optimization, lattice Boltzmann method, multicore system, free surface
1	Ming-Yung Ko, Praveen K. Murthy, Shuvra S. Bhattacharyya	Beyond single-appearance schedules: Efficient DSP software synthesis using nested procedure calls.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	block diagram compiler, hierarchical graph decomposition, procedural implementation, embedded systems, design methodology, memory optimization, Synchronous dataflow
1	Youcef Bouchebaba, Bruno Girodias, Fabien Coelho, Gabriela Nicolescu, El Mostapha Aboulhamid	Buffer and Register Allocation for Memory Space Optimization.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	program transformation, memory hierarchy, data locality, memory optimization
1	Peter Vanbroekhoven, Gerda Janssens, Maurice Bruynooghe, Francky Catthoor	A practical dynamic single assignment transformation.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	reaching definitions, parallelization, Data flow analysis, arrays, single assignment
1	Ke Zhang, Xiaoyang Wu, Lu Yu	An Area-efficient VLSI Implementation of CA-2D-VLC Decoder for AVS.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Massimo Rovini, Giuseppe Gentile, Francesco Rossi, Luca Fanucci	A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Yong Dou, Jinhui Xu, Guiming Wu	The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining.	ARC	2007	DBLP DOI BibTeX RDF
1	Jinpyo Hong, J. Ramanujam	Memory Offset Assignment for DSPs.	ICESS	2007	DBLP DOI BibTeX RDF
1	Vincent Kerzerho, Serge Bernard, Philippe Cauvet, Jean-Marie Janik	A First Step for an INL Spectral-Based BIST: The Memory Optimization.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	integral non-linearity, polynomial fitting, Fourier series expansion, fast Fourier transform, analog-to-digital converter testing
1	Manish Verma	Advanced memory optimization techniques for low-power embedded processors.		2006	RDF
1	Bruno Girodias, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Pierre G. Paulin, Bruno Lavigueur	Application-Level Memory Optimization for MPSoC.	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF
1	Rachid Seghir, Vincent Loechner	Memory optimization by counting points in integer transformations of parametric polytopes.	CASES	2006	DBLP DOI BibTeX RDF	array linearization, cache access optimization, counting lattice points in polytopes, exact memory size computation, polytope model
1	Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitra	Integrated scratchpad memory optimization and task scheduling for MPSoC architectures.	CASES	2006	DBLP DOI BibTeX RDF	scheduling, MPSoC, scratchpad memory, task mapping
1	Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran	A novel instruction scratchpad memory optimization method based on concomitance metric.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Jeonghun Cho, Yunheung Paek	Run-Time Memory Optimization for DDMB Architecture Through a CCB Algorithm.	EUC Workshops	2006	DBLP DOI BibTeX RDF	dual data memory banks, compiler and on-chip memory, DSP, Run-time environment
1	Wen-ke Chen, Sanjay Bhansali, Trishul M. Chilimbi, Xiaofeng Gao, Weihaw Chuang	Profile-guided proactive garbage collection for locality optimization.	PLDI	2006	DBLP DOI BibTeX RDF	page optimization, data locality, memory optimization, cache optimization, garbage collectors
1	A. Allam, J. Ramanujam, Gerald Baumgartner, P. Sadayappan	Memory minimization for tensor contractions using integer linear programming.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Denis Barthou, Sébastien Donadio, Alexandre Duchateau, William Jalby, E. Courtois	Iterative Compilation with Kernel Exploration.	LCPC	2006	DBLP DOI BibTeX RDF
1	Qin Zhao, Rodric M. Rabbah, Weng-Fai Wong	Dynamic memory optimization using pool allocation and prefetching.	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF
1	Manish Verma, Peter Marwedel	Memory Optimization Techniques for Low-Power Embedded Processors.	GI Jahrestagung	2005	DBLP BibTeX RDF
1	Jilei Tian, Jani Nurminen, Imre Kiss	Duration modeling and memory optimization in a Mandarin TTS system.	INTERSPEECH	2005	DBLP BibTeX RDF
1	Hyunok Oh, Nikil D. Dutt, Soonhoi Ha	Single appearance schedule with dynamic loop count for minimum data buffer from synchronous dataflow graphs.	CASES	2005	DBLP DOI BibTeX RDF	automatic code synthesis, dynamic loop count, single appearance schedule, memory optimization, synchronous dataflow
1	Xipeng Shen, Yaoqing Gao, Chen Ding, Roch Archambault	Lightweight reference affinity analysis.	ICS	2005	DBLP DOI BibTeX RDF	data interleving, data regrouping, compiler, memory optimization, frequency, affinity
1	Min-Sik Jin, Min-Soo Jung	A Study on Fast JCVM by Moving Object from EEPROM to RAM.	RTCSA	2005	DBLP DOI BibTeX RDF
1	Peter Vanbroekhoven, Gerda Janssens, Maurice Bruynooghe, Francky Catthoor	Transformation to Dynamic Single Assignment Using a Simple Data Flow Analysis.	APLAS	2005	DBLP DOI BibTeX RDF
1	Mahmut T. Kandemir, Ismail Kadayif, Alok N. Choudhary, Ibrahim Kolcu	Compiler-directed scratch pad memory optimization for embedded multiprocessors.	IEEE Trans. VLSI Syst.	2004	DBLP BibTeX RDF
1	Sorinel Adrian Oprisan	Task Oriented Functional Self-organization of Mobile Agents Team: Memory Optimization Based on Correlation Feature.	ANTS Workshop	2004	DBLP DOI BibTeX RDF
1	Daniele Lo Iacono, Ettore Messina, Giuseppe Avellone, Agostino Galluzzo	Memory optimization techniques for UMTS code generation.	ISCAS	2004	DBLP BibTeX RDF
1	Praveen K. Murthy, Shuvra S. Bhattacharyya	Buffer merging - a powerful technique for reducing memory requirements of synchronous dataflow specifications.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	DSP and embedded systems, array lifetime, block diagram compiler, buffer overlaying, lifetime analysis, design methodology, graph coloring, dataflow, memory optimization, Synchronous dataflow, path covering
1	Hyunok Oh, Soonhoi Ha	Fractional Rate Dataflow Model for Efficient Code Synthesis.	VLSI Signal Processing	2004	DBLP DOI BibTeX RDF	synchronous dataflow (SDF), multimedia, memory optimization, code synthesis
1	Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu	A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories.	MTDT	2004	DBLP DOI BibTeX RDF
1	Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas	Data dependency size estimation for use in memory optimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Bruno Bougard, Liesbet Van der Perre, F. Maessen, A. Giulietti, V. Derudder, Francky Catthoor	Memory Power Reduction for High-Speed Implementation of Turbo Codes.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	MAP algorithm, low power, turbo codes, memory optimization, low latency
1	Mihai Budiu, Seth Copen Goldstein	Optimizing Memory Accesses For Spatial Computation.	CGO	2003	DBLP DOI BibTeX RDF
1	Surendra Byna, William D. Gropp, Xian-He Sun, Rajeev Thakur	Improving the Performance of MPI Derived Datatypes by Optimizing Memory-Access Cost.	CLUSTER	2003	DBLP DOI BibTeX RDF
1	Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li	A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories.	MTDT	2003	DBLP DOI BibTeX RDF
1	Paolo Gai, Marco Di Natale, Giuseppe Lipari, Alberto Ferrari, Claudio Gabellini, Paolo Marceca	A comparison of MPCP and MSRP when sharing resources in the Janus multiple-processor on a chip platform.	IEEE Real Time Technology and Applications Symposium	2003	DBLP DOI BibTeX RDF	scheduling, real-time, operating systems, multiprocessor, system-on-a-chip
1	Vissarion Ferentinos, M. Milia, Gauthier Lafruit, Jan Bormans, Francky Catthoor	Memory Compaction and Power Optimization for Wavelet-Based Coders.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Hui-Ming Su, Jing Chen	Framework-Based Development of Embedded Real-Time Systems Hui-Ming Su and Jing Chen.	RTCSA	2003	DBLP DOI BibTeX RDF
1	Hyunok Oh, Soonhoi Ha	Efficient code synthesis from extended dataflow graphs for multimedia applications.	DAC	2002	DBLP DOI BibTeX RDF	multimedia, dataflow, software synthesis, memory optimization
1	Aneesh Aggarwal	Software caching vs. prefetching.	MSP/ISMM	2002	DBLP DOI BibTeX RDF	memory optimization, software prefetching, software caching
1	Brendon Cahoon, Kathryn S. McKinley	Simple and effective array prefetching in Java.	Java Grande	2002	DBLP DOI BibTeX RDF	array prefetching, Java, static analysis, memory optimization
1	Preeti Ranjan Panda, Francky Catthoor, Nikil D. Dutt, Koen Danckaert, Erik Brockmeyer, Chidamber Kulkarni, Arnout Vandecappelle, Per Gunnar Kjeldsberg	Data and memory optimization techniques for embedded systems.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	data optimization, memory architecture customization, memory power dissipation, high-level synthesis, survey, SRAM, allocation, data cache, DRAM, register file, architecture exploration, code transformation, address generation, size estimation
1	Thomas Kistler, Michael Franz	Continuous Program Optimization: Design and Evaluation.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	profiling, Dynamic compilation, memory optimization, continuous optimization, trace scheduling
1	Lode Nachtergaele, Toon Gijbels, Jan Bormans, Francky Catthoor, Ivo Bolsens	Power and Speed-Efficient Code Transformation of Video Compression Algorithms for RISC Processors.	VLSI Signal Processing	2001	DBLP DOI BibTeX RDF	video coding, MPEG-4, memory optimization, H.263
1	Trishul M. Chilimbi	On the Stability of Temporal Data Reference Profiles.	IEEE PACT	2001	DBLP DOI BibTeX RDF
1	John Kriz, Tom Joyner, Ted Wilson, Greg McGraner	Correlated, Real Time Multi-spectral Sensor Test and Evaluation (T&E) in an Installed Systems Test Facility (ISTF) Using High Performance Computing.	International Conference on Computational Science	2001	DBLP DOI BibTeX RDF
1	Stefan Manegold, Peter A. Boncz, Martin L. Kersten	What Happens During a Join? Dissecting CPU and Memory Optimization Effects.	VLDB	2000	DBLP BibTeX RDF