Search results for "memory system"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
5	Jong Won Park	Multiaccess Memory System for Attached SIMD Computer.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	prime memory system, multiaccess memory system, conflict-free memory system, routing circuit, SIMD computer, address calculation
4	Justin Teller, Charles B. Silio Jr., Bruce L. Jacob	Performance characteristics of MAUI: an intelligent memory system architecture.	Memory System Performance	2005	DBLP DOI BibTeX RDF	MAUI memory architecture, SimpleScalar simulator, data-intensive calculations, intelligent memory, memory architecture, vector processing, SIMD processing
4	Santanu Dutta, Wayne Wolf, Andrew Wolfe	VLSI issues in memory-system design for video signal processors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	VLSI issues, video signal processors, memory-system architectures, circuit-level issues, register-cache based hierarchy, general-purpose programmable microprocessors, VLSI, system architecture, utilization, memory architecture, memory architecture, video signal processing, area, cycle time, memory-system design
4	Aaron Goldberg, John A. Trotter	Interrupt-based hardware support for profiling memory system performance. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	profiling memory system performance, superscalar technologies, Mprof prototype, data stall cycles, first level cache misses, Sun Sparc 10/41, performance evaluation, storage management, memory architecture, hardware support, sampling techniques, memory system performance
3	Hyungsoo Jung, Hyuck Han, Shin Gyu Kim, Heon Young Yeom	A practical evaluation of large-memory data processing on a reliable remote memory system.	SAC	2009	DBLP DOI BibTeX RDF	large-memory data processing, remote memory system, RDMA
3	David A. Wood	Keynote talk challenges in chip multiprocessor memory systems.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF
3	Shoaib Kamil, Parry Husbands, Leonid Oliker, John Shalf, Katherine A. Yelick	Impact of modern memory subsystems on cache optimizations for stencil computations.	Memory System Performance	2005	DBLP DOI BibTeX RDF	performance modeling, prefetch, stencil, cache blocking
3	Ilya Ganusov, Martin Burtscher	On the importance of optimizing the configuration of stream prefetchers.	Memory System Performance	2005	DBLP DOI BibTeX RDF	hardware prefetching, stream prefetcher, runahead execution
3	Darren J. Kerbyson, Michael Lang 0003, Gene Patino, Hossein Amidi	An empirical performance analysis of commodity memories in commodity servers.	Memory System Performance	2004	DBLP DOI BibTeX RDF	performance analysis, performance measurement, memory modules, memory system performance
3	Jong Won Park	An Efficient Buffer Memory System for Subarray Access.	IEEE Trans. Parallel Distrib. Syst.	2001	DBLP DOI BibTeX RDF	High-resolution graphical display, buffer memory system, block access, address routing, memory module selection, image processing, address calculation
3	Hiroyuki Sato, Takeshi Nanri, Masaaki Shimasaki	Design and implementation of PVM-based portable distributed shared memory system on the workstation cluster environment. (PDF / PS)	ICPADS	1997	DBLP DOI BibTeX RDF	PVM-based portable distributed shared memory system, workstation cluster environment, distributed memory systems, portability, cluster of workstations, performance problem
3	Thomas Stricker, Thomas R. Gross	Global Address Space, Non-Uniform Bandwidth: A Memory System Performance Characterization of Parallel Systems.	HPCA	1997	DBLP DOI BibTeX RDF	nonuniform bandwidth, memory system performance characterization, local memory accesses, remote write, cost benefit model, DEC Alpha based parallel systems, DEC-Alpha processor architecture, DEC 8400, scalability, compiler, parallel systems, empirical evaluation, memory architecture, coherency, cache storage, access pattern, spatial locality, local memory, global address space, Cray T3E, Cray T3D, clock speed
3	Chee Fen Yu, Benjamin W. Wah	Efficient Branch-and-Bound Algorithms on a Two-Level Memory System.	IEEE Trans. Software Eng.	1988	DBLP DOI BibTeX RDF	two-level memory system, storage management, virtual-memory, storage allocation, depth-first search, branch-and-bound algorithms, virtual storage, best-first search
2	Congchong Liu, Shujia Zhou	Local and Global Optimization of MapReduce Program Model.	SERVICES	2011	DBLP DOI BibTeX RDF	X10 parallel programming language, load balancing, shared-memory system, distributed memory system, MapReduce
2	Moinuddin K. Qureshi, Michele Franceschini, Luis Alfonso Lastras-Montaño, John P. Karidis	Morphable memory system: a robust architecture for exploiting multi-level phase change memories.	ISCA	2010	DBLP DOI BibTeX RDF	morphable memory, multi-level cell, phase change memory
2	Damien Imbs, Michel Raynal, Gadi Taubenfeld	On asymmetric progress conditions.	PODC	2010	DBLP DOI BibTeX RDF	fault-freedom, progress condition, liveness, process crash, wait-freedom, obstruction-freedom, asynchronous shared memory system, consensus number
2	Banit Agrawal, Timothy Sherwood	High-bandwidth network memory system through virtual pipelines.	IEEE/ACM Trans. Netw.	2009	DBLP DOI BibTeX RDF	VPNM, bank conflicts, mean time to stall, packet reassembly, virtual pipeline, network, memory, DRAM, universal hashing, memory controller, MTS, packet buffering
2		Hierarchical Memory System.	Encyclopedia of Database Systems	2009	DBLP DOI BibTeX RDF
2	Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu	Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices.	ISCA	2009	DBLP DOI BibTeX RDF	bandwidth decoupling, decoupled DIMM, DRAM memories
2	Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Jude A. Rivers	Scalable high performance main memory system using phase-change memory technology.	ISCA	2009	DBLP DOI BibTeX RDF	dram caching, phase change memory, wear leveling
2	Amin Firoozshahian, Alex Solomatnikov, Ofer Shacham, Zain Asgar, Stephen Richardson, Christos Kozyrakis, Mark Horowitz	A memory system design framework: creating smart memories.	ISCA	2009	DBLP DOI BibTeX RDF	memory access protocol, protocol controller, transactional memory, reconfigurable architecture, cache coherence, memory systems, multi-core processors, stream programming
2	Magnus Jahre, Marius Grannæs, Lasse Natvig	A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures.	HPCC	2009	DBLP DOI BibTeX RDF
2	Mengxiao Liu, Weixing Ji, Xing Pu, Jiaxin Li	A Parallel Memory System Model for Multi-core Processor.	NAS	2009	DBLP DOI BibTeX RDF
2	Alex Solomatnikov, Amin Firoozshahian, Ofer Shacham, Zain Asgar, Megan Wachs, Wajahat Qadeer, Stephen Richardson, Mark Horowitz	Using a configurable processor generator for computer architecture prototyping.	MICRO	2009	DBLP DOI BibTeX RDF	computer architecture prototyping, configurable/extensible processor generator, memory system architecture, reconfigurable architecture, VLSI design
2	Han-Lin Li, Chia-Lin Yang, Hung-Wei Tseng	Energy-Aware Flash Memory Management in Virtual Memory System.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Jarno Vanne, Eero Aho, Timo D. Hämäläinen, Kimmo Kuusilinna	A Parallel Memory System for Variable Block-Size Motion Estimation Algorithms.	IEEE Trans. Circuits Syst. Video Techn.	2008	DBLP DOI BibTeX RDF
2	Jianjun Guo, Ming-che Lai, Zhengyuan Pang, Libo Huang, Fangyuan Chen, Kui Dai, Zhiying Wang	Hierarchical memory system design for a heterogeneous multi-core processor.	SAC	2008	DBLP DOI BibTeX RDF	memory, heterogeneous, multi-core
2	Hiroko Midorikawa, Motoyoshi Kurokawa, Ryutaro Himeno, Mitsuhisa Sato	DLM: A distributed Large Memory System using remote memory swapping over cluster nodes.	CLUSTER	2008	DBLP DOI BibTeX RDF
2	Mohammad R. Nikseresht, David A. Hutchinson, Anil Maheshwari	Experiments with a Parallel External Memory System.	HiPC	2007	DBLP DOI BibTeX RDF
2	Dan Fay, Alex Shye, Sayantan Bhattacharya, Daniel A. Connors, Steve Wichmann	An Adaptive Fault-Tolerant Memory System for FPGA-based Architectures in the Space Environment.	AHS	2007	DBLP DOI BibTeX RDF
2	Qiankun Miao, Guangzhong Sun, Jiulong Shan, Guoliang Chen	Single Data Copying for MPI Communication Optimization on Shared Memory System.	International Conference on Computational Science	2007	DBLP DOI BibTeX RDF
2	Jun-Song Wang, Zhi-Wei Gao, Ning-Shou Xu	A Novel Associative Memory System Based Modeling and Prediction of TCP Network Traffic.	ISNN	2007	DBLP DOI BibTeX RDF
2	Antonio Fernández, Ernesto Jiménez, Michel Raynal	Electing an Eventual Leader in an Asynchronous Shared Memory System.	DSN	2007	DBLP DOI BibTeX RDF
2	Wai-Yeung Yip, Scott Best, Wendemagegnehu T. Beyene, Ralf Schmitt	System Co-Design and Co-Analysis Approach to Implementing the XDR Memory System of the Cell Broadband Engine Processor; Realizing 3.2 Gbps Data Rate per Memory Lane in Low Cost, High Volume Production.	ASP-DAC	2007	DBLP DOI BibTeX RDF
2	Vasily G. Moshnyaga, Hua Vo, Glenn Reinman, Miodrag Potkonjak	Reducing Energy of DRAM/Flash Memory System by OS-controlled Data Refresh.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Yide Shen	Transactive memory system development in virtual teams: the potential role of shared identity and shared context.	CPR	2007	DBLP DOI BibTeX RDF	shared identity, transactive memory system, virtual team, shared context
2	Wenlong Li, Eric Li, Aamer Jaleel, Jiulong Shan, Yurong Chen, Qigang Wang, Ravi R. Iyer, Ramesh Illikkal, Yimin Zhang, Dong Liu, Michael Liao, Wei Wei, Jinhua Du	Understanding the Memory Performance of Data-Mining Workloads on Small, Medium, and Large-Scale CMPs Using Hardware-Software Co-simulation.	ISPASS	2007	DBLP DOI BibTeX RDF	DRAM caches, small-scale CMP, medium-scale CMP, large-scale CMP, hardware-software co-simulation, terabyte-level workloads, multithreaded data mining applications, cache design, memory performance, multicore systems, memory system performance
2	Xiaochuan Pan, Minoru Tsukada	A Model of the Hippocampal-cortical Memory System.	Biological Cybernetics	2006	DBLP DOI BibTeX RDF
2	Antony L. Hosking, Ali-Reza Adl-Tabatabai (eds.)	Proceedings of the 2006 workshop on Memory System Performance and Correctness, San Jose, California, USA, October 11, 2006	Memory System Performance and Correctness	2006	DBLP BibTeX RDF
2	Hung-Wei Tseng, Han-Lin Li, Chia-Lin Yang	An energy-efficient virtual memory system with flash memory as the secondary storage.	ISLPED	2006	DBLP DOI BibTeX RDF	embedded storages, embedded systems, virtual memory, NAND flash memory, page replacement
2	Michael D. Adams 0001, David S. Wise	Seven at one stroke: results from a cache-oblivious paradigm for scalable matrix algorithms.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	Morton-hybrid, parallel processing, paging, quadtrees, Cholesky factorization, cache misses, TLB
2	Mark Aiken, Manuel Fähndrich, Chris Hawblitzel, Galen C. Hunt, James R. Larus	Deconstructing process isolation.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	hardware isolated process (HIP), hardware protection domain, software isolated process (SIP), singularity
2	Jinzhan Peng, Guei-Yuan Lueh, Gansha Wu, Xiaogang Gou, Ryan Rakvic	A comprehensive study of hardware/software approaches to improve TLB performance for java applications on embedded systems.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	TLB performance, Java, embedded system
2	Gregory Buehrer, Yen-Kuang Chen, Srinivasan Parthasarathy, Anthony D. Nguyen, Amol Ghoting, Daehyun Kim	Efficient pattern mining on shared memory systems: implications for chip multiprocessor architectures.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF
2	Shoaib Kamil, Kaushik Datta, Samuel Williams, Leonid Oliker, John Shalf, Katherine A. Yelick	Implicit and explicit optimizations for stencil computations.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF
2	Melissa E. O'Neill, F. Warren Burton	Smarter garbage collection with simplifiers.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	lightweight daemon, simplifier, weak pointer, finalizer
2	Lei Jin, Hyunjin Lee, Sangyeun Cho	A flexible data to L2 cache mapping approach for future multicore processors.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	non-uniform cache architecture (NUCA), page allocation
2	Mojtaba Mehrara, Todd M. Austin	Reliability-aware data placement for partial memory protection in embedded processors.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	memory lifetime, partial memory protection, selective data placement, embedded systems, soft errors
2	Kunal Agrawal, Charles E. Leiserson, Jim Sukha	Memory models for open-nested transactions.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF
2	Dan Grossman, Jeremy Manson, William Pugh	What do high-level memory models mean for transactions?	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF
2	Benjamin Hindman, Dan Grossman	Atomicity via source-to-source translation.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	Java, transactional memory, concurrent programming, atomicity
2	Chuan Yue, Richard Tran Mills, Andreas Stathopoulos, Dimitrios S. Nikolopoulos	Runtime Support for Memory Adaptation in Scientific Applications via Local Disk and Remote Memory.	HPDC	2006	DBLP DOI BibTeX RDF	memory server, memory adaptation, local disk memory, remote memory capability, shared computational resource, network memory, memory malleability, MPI communication, cache memory, scientific application, virtual memory system
2	Keun Soo Yim, Jae Don Lee, Jungkeun Park, Jeong-Joon Yoo, Chaeseok Im, Yeonseung Ryu	A Software Reproduction of Virtual Memory for Deeply Embedded Systems.	ICCSA	2006	DBLP DOI BibTeX RDF	memory system and heap management, Embedded system
2	David Wang, Brinda Ganesh, Nuengwong Tuaycharoen, Kathleen Baynes, Aamer Jaleel, Bruce L. Jacob	DRAMsim: a memory system simulator.	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF
2	Brad Calder, Benjamin G. Zorn (eds.)	Proceedings of the 2005 workshop on Memory System Performance, Chicago, Illinois, USA, June 12, 2005	Memory System Performance	2005	DBLP BibTeX RDF
2	Fu-ren Lin, Kuo-Lung Tsai, Pei-Chen Sun	The Design and Evaluation of P2P Transactive Memory System.	EEE	2005	DBLP DOI BibTeX RDF
2	Zhichun Zhu, Zhao Zhang	A Performance Comparison of DRAM Memory System Optimizations for SMT Processors.	HPCA	2005	DBLP DOI BibTeX RDF
2	Chris Lattner, Vikram S. Adve	Transparent pointer compression for linked data structures.	Memory System Performance	2005	DBLP DOI BibTeX RDF	pointer compression, cache, static analysis, data layout, recursive data structure
2	Easwaran Raman, David I. August	Recursive data structure profiling.	Memory System Performance	2005	DBLP DOI BibTeX RDF	RDS, dynamic shape graph, list linearization, memory profiling, shape profiling
2	Yi Feng, Emery D. Berger	A locality-improving dynamic memory allocator.	Memory System Performance	2005	DBLP DOI BibTeX RDF	vam, memory management, virtual memory, paging, fragmentation, allocator, cache locality
2	Kartik Sudeep, Ahmed Gheith	Application analysis using memory pressure.	Memory System Performance	2005	DBLP DOI BibTeX RDF
2	Chen Ding, Chengliang Zhang, Xipeng Shen, Mitsunori Ogihara	Gated memory control for memory monitoring, leak detection and garbage collection.	Memory System Performance	2005	DBLP DOI BibTeX RDF	memory usage monitoring, object life, preventive memory management, memory leak, program phase
2	Inho Park, Seon Wook Kim, Kyung Park	Characterization of OpenMP Applications on the InfiniBand-Based Distributed Virtual Shared Memory System.	HiPC	2004	DBLP DOI BibTeX RDF
2	Chen Ding, Stephen Blackburn (eds.)	Proceedings of the 2004 workshop on Memory System Performance, Washington, DC, USA, June 8, 2004	Memory System Performance	2004	DBLP BibTeX RDF
2	Kevin Ferreira, Shinichi Yamagiwa, Leonel Sousa, Keiichi Aoki, Koichi Wada, Luis Miguel Campos	Distributed Shared Memory System Based on the Maestro2 High Performance Cluster Network.	ISPDC/HeteroPar	2004	DBLP DOI BibTeX RDF	Clusters, Parallel computing, High Performance Computing, Distributed Shared Memory, High Performance Networks
2	Jay B. Brockman, Shyamkumar Thoziyoor, Shannon K. Kuntz, Peter M. Kogge	A low cost, multithreaded processing-in-memory system.	WMPI	2004	DBLP DOI BibTeX RDF	PIM, processing-in-memory
2	Rajeev Krishna, Scott A. Mahlke, Todd M. Austin	Memory system design space exploration for low-power, real-time speech recognition.	CODES+ISSS	2004	DBLP DOI BibTeX RDF
2	Motohiro Kawahito, Hideaki Komatsu, Toshio Nakatani	Instruction combining for coalescing memory accesses using global code motion.	Memory System Performance	2004	DBLP DOI BibTeX RDF	instruction combining, memory access coalescing, Java, JIT compilers, IA-64, 64-bit architectures
2	David Koes, Mihai Budiu, Girish Venkataramani	Programmer specified pointer independence.	Memory System Performance	2004	DBLP DOI BibTeX RDF	pointer independence, alias analysis, memory performance
2	Changpeng Fang, Steve Carr, Soner Önder, Zhenlin Wang	Reuse-distance-based miss-rate prediction on a per instruction basis.	Memory System Performance	2004	DBLP DOI BibTeX RDF	profiling, data locality, reuse distance
2	Qing Yi, Ken Kennedy, Haihang You, Keith Seymour, Jack Dongarra	Automatic blocking of QR and LU factorizations for locality.	Memory System Performance	2004	DBLP DOI BibTeX RDF	LU, locality, blocking, loop optimizations, LAPACK, QR
2	Muhammad Shaaban, Edward Mulrane	Improving trace cache hit rates using the sliding window fill mechanism and fill select table.	Memory System Performance	2004	DBLP DOI BibTeX RDF	branch promotion, fetch mechanisms, fill mechanisms, superscalar processors, cache performance, trace cache
2	Kathryn S. McKinley	Polar opposites: next generation languages and architectures.	Memory System Performance	2004	DBLP DOI BibTeX RDF
2	Michelle Mills Strout, Paul D. Hovland	Metrics and models for reordering transformations.	Memory System Performance	2004	DBLP DOI BibTeX RDF	inspector/executor, locality metrics, run-time reordering transformations, spatial locality graph, temporal locality hypergraph, optimization, data locality
2	Yoshinori Ojima, Mitsuhisa Sato, Hiroshi Harada, Yutaka Ishikawa	Performance of Cluster-enabled OpenMP for the SCASH Software Distributed Shared Memory System.	CCGRID	2003	DBLP DOI BibTeX RDF
2	Jie Tao	Supporting the Memory System Evaluation with a Monitor Simulator.	PDP	2003	DBLP DOI BibTeX RDF
2	Martin Karlsson, Kevin E. Moore, Erik Hagersten, David A. Wood	Memory System Behavior of Java-Based Middleware.	HPCA	2003	DBLP DOI BibTeX RDF
2	Soontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin	Partitioned instruction cache architecture for energy efficiency.	ACM Trans. Embedded Comput. Syst.	2003	DBLP DOI BibTeX RDF	Caches, energy, memory system
2	Hojun Shim, Yongsoo Joo, Yongseok Choi, Hyung Gyu Lee, Naehyuck Chang	Low-energy off-chip SDRAM memory systems for embedded applications.	ACM Trans. Embedded Comput. Syst.	2003	DBLP DOI BibTeX RDF	Low power, memory system, SDRAM
2	Achour Mostéfaoui, Sergio Rajsbaum, Michel Raynal, Matthieu Roy	A Hierarchy of Conditions for Asynchronous Interactive Consistency.	PaCT	2003	DBLP DOI BibTeX RDF	Erroneous Value, Fault-Tolerance, Error-Correcting Code, Hamming Distance, Condition, Crash Failure, Atomic Register, Interactive Consistency, Asynchronous Shared Memory System
2	Lanfranco Lopriore	Access Control Mechanisms in a Distributed, Persistent Memory System.	IEEE Trans. Parallel Distrib. Syst.	2002	DBLP DOI BibTeX RDF	single address space, distributed system, Access control, memory management, protection, persistent system
2	Rong Yu, Laxmi N. Bhuyan, Ravi R. Iyer	Comparing the Memory System Performance of DSS Workloads on the HP V-Class and SGI Origin 2000. (PDF / PS)	IPDPS	2002	DBLP DOI BibTeX RDF
2	Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan	The performance advantage of applying compression to the memory system.	MSP/ISMM	2002	DBLP DOI BibTeX RDF	address compression, instruction compression, cache, data compression, entropy, memory, latency, Markov models, bandwidth, storage, traffic, register file, lossless compression
2	David T. Croasdell, David B. Paradice	TOOMS: In Pursuit of Designing an Organizational Memory System for Category Manager.	HICSS	2002	DBLP DOI BibTeX RDF
2	Peter Grun, Nikil D. Dutt, Alexandru Nicolau	Memory System Connectivity Exploration.	DATE	2002	DBLP DOI BibTeX RDF
2	Jui-Hua Li, JoAnne Holliday, George Fegan	General applications 2: decision making of embedded I/O buffer sizes using the queueing simulation model for a shared-memory system.	Winter Simulation Conference	2002	DBLP DOI BibTeX RDF
2	Witawas Srisa-an, Chia-Tien Dan Lo, J. Morris Chang	Performance Enhancements to the Active Memory System.	ICCD	2002	DBLP DOI BibTeX RDF	Java, embedded system, garbage collection, reference counting, hardware support
2	Yongsoo Joo, Yongseok Choi, Hojun Shim, Hyung Gyu Lee, Kwanho Kim, Naehyuck Chang	Energy exploration and reduction of SDRAM memory systems.	DAC	2002	DBLP DOI BibTeX RDF	low power, memory system, SDRAM
2	Wei-Fen Lin, Steven K. Reinhardt, Doug Burger	Designing a Modern Memory Hierarchy with Hardware Prefetching.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Rambus DRAM, caches, Prefetching, memory bandwidth, spatial locality, memory system design
2	G. Esakkimuthu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Memory system energy (poster session): influence of hardware-software optimizations.	ISLPED	2000	DBLP DOI BibTeX RDF
2	Frank Habermann, August-Wilhelm Scheer	Knowing the Impacts of Information Technology: Towards an Organizational Memory System as a Tool for IT-Management. (PDF / PS)	HICSS	2000	DBLP DOI BibTeX RDF
2	Binu K. Mathew, Sally A. McKee, John B. Carter, Al Davis	Algorithmic foundations for a parallel vector access memory system.	SPAA	2000	DBLP DOI BibTeX RDF
2	Jin-Soo Kim, Yarsun Hsu	Memory system behavior of Java programs: methodology and analysis.	SIGMETRICS	2000	DBLP DOI BibTeX RDF	Java
2	Sanjive Agarwala, Charles Fuoco, Tim Anderson, Dave Comisky, Christopher Mobley	A Multi-Level Memory System Architecture for High-Performance DSP Applications. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
2	Luiz André Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Ben Verghese	Impact of Chip-Level Integration on Performance of OLTP Workloads.	HPCA	2000	DBLP DOI BibTeX RDF	chip-level integration, database workloads, multiprocessors, memory system performance
2	Rajeev Barua, Walter Lee, Saman P. Amarasinghe, Anant Agarwal	Maps: A Compiler-Managed Memory System for Raw Machines.	ISCA	1999	DBLP DOI BibTeX RDF
2	Lixin Zhang 0002, John B. Carter, Wilson C. Hsieh, Sally A. McKee	Memory System Support for Image Processing.	IEEE PACT	1999	DBLP DOI BibTeX RDF	bus utilization, image processing, virtual memory, memory architecture, memory bandwidth, memory latency, cache efficiency
2	Kichul Kim	Shuffle Memory System. (PDF / PS)	IPPS/SPDP	1999	DBLP DOI BibTeX RDF
2	Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim	A Selective Compressed Memory System by On-Line Data Decompressing.	EUROMICRO	1999	DBLP DOI BibTeX RDF
2	Cristina Nicolescu, Bas Albers, Pieter Jonker	Parallel Watershed Algorithm on Images from Cranial CT-Scans Using PVM and MPI on Distributed Memory System.	PVM/MPI	1999	DBLP DOI BibTeX RDF