Search results for "memory system architecture"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Justin Teller, Charles B. Silio Jr., Bruce L. Jacob	Performance characteristics of MAUI: an intelligent memory system architecture.	Memory System Performance	2005	DBLP DOI BibTeX RDF	MAUI memory architecture, SimpleScalar simulator, data-intensive calculations, intelligent memory, memory architecture, vector processing, SIMD processing
2	Sanjive Agarwala, Charles Fuoco, Tim Anderson, Dave Comisky, Christopher Mobley	A Multi-Level Memory System Architecture for High-Performance DSP Applications. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
1	Doe Hyun Yoon, Mattan Erez	Virtualized and flexible ECC for main memory.	ASPLOS	2010	DBLP DOI BibTeX RDF	fault tolerance, reliability, error correction, memory systems
1	Massoud Pedram, Naehyuck Chang, Younghyun Kim, Yanzhi Wang	Hybrid electrical energy storage systems.	ISLPED	2010	DBLP DOI BibTeX RDF	electrical storage, energy storage, hybrid storage, management, energy, charge
1	Alex Solomatnikov, Amin Firoozshahian, Ofer Shacham, Zain Asgar, Megan Wachs, Wajahat Qadeer, Stephen Richardson, Mark Horowitz	Using a configurable processor generator for computer architecture prototyping.	MICRO	2009	DBLP DOI BibTeX RDF	computer architecture prototyping, configurable/extensible processor generator, memory system architecture, reconfigurable architecture, VLSI design
1	Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Functional Self-Testing for Bus-Based Symmetric Multiprocessors.	DATE	2008	DBLP DOI BibTeX RDF
1	Yi Liu, Xin Zhang, He Li, Mingxiu Li, Depei Qian	Hardware Transactional Memory Supporting I/O Operations within Transactions.	HPCC	2008	DBLP DOI BibTeX RDF
1	Lixin Zhang 0002, Michael Parker, John B. Carter	Efficient address remapping in distributed shared-memory systems.	TACO	2006	DBLP DOI BibTeX RDF	Smart memory controller, address remapping, shadow address, performance evaluation, multiprocessors, cache coherence
1	Lukasz Masko, Gregory Mounie, Denis Trystram, Marek Tudruj	Program Graph Structuring for Execution in Dynamic SMP Clusters Using Moldable Tasks.	PARELEC	2006	DBLP DOI BibTeX RDF
1	Marek Tudruj, Lukasz Masko	Fast Matrix Multiplication in Dynamic SMP Clusters with Communication on the Fly in Systems on Chip Technology.	PARELEC	2006	DBLP DOI BibTeX RDF
1	Quynh-Lien Nguyen-Phuc, Carolina Miro Sorolla	An MPEG-4 Renderer for High Quality Video Composition and Texture Mapping.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	main profile level3, hybrid visual profile, 3D engines, natural video, rendering, MPEG-4, 2D-mesh, perspective transformation
1	Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin	Hardware and Software Techniques for Controlling DRAM Power Modes.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	low power compilation, software-directed energy management, low power, Memory architecture
1	Lixin Zhang 0002, Zhen Fang, Michael Parker, Binu K. Mathew, Lambert Schaelicke, John B. Carter, Wilson C. Hsieh, Sally A. McKee	The Impulse Memory Controller.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Computer architecture, memory systems
1	Derek L. Eager, Daniel J. Sorin, Mary K. Vernon	AMVA techniques for high service time variability.	SIGMETRICS	2000	DBLP DOI BibTeX RDF
1	Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mary K. Vernon, David A. Wood	Analytic Evaluation of Shared-memory Systems with ILP Processors.	ISCA	1998	DBLP DOI BibTeX RDF
1	Thomas Alexander, Gershon Kedem	Distributed Prefetch-buffer/Cache Design for High-Performance Memory Systems.	HPCA	1996	DBLP DOI BibTeX RDF	Prefetch-buffer, cache, prediction, memory
1	Kalyani Bogineni, Patrick W. Dowd	An Optically Interconnected Distributed Shared Memory System: Architecture and Performance Analysis.	International Journal of High Speed Computing	1992	DBLP DOI BibTeX RDF