Search results for "memory system performance"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Aaron Goldberg, John A. Trotter	Interrupt-based hardware support for profiling memory system performance. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	profiling memory system performance, superscalar technologies, Mprof prototype, data stall cycles, first level cache misses, Sun Sparc 10/41, performance evaluation, storage management, memory architecture, hardware support, sampling techniques, memory system performance
3	Ilya Ganusov, Martin Burtscher	On the importance of optimizing the configuration of stream prefetchers.	Memory System Performance	2005	DBLP DOI BibTeX RDF	hardware prefetching, stream prefetcher, runahead execution
3	Darren J. Kerbyson, Michael Lang 0003, Gene Patino, Hossein Amidi	An empirical performance analysis of commodity memories in commodity servers.	Memory System Performance	2004	DBLP DOI BibTeX RDF	performance analysis, performance measurement, memory modules, memory system performance
3	Thomas Stricker, Thomas R. Gross	Global Address Space, Non-Uniform Bandwidth: A Memory System Performance Characterization of Parallel Systems.	HPCA	1997	DBLP DOI BibTeX RDF	nonuniform bandwidth, memory system performance characterization, local memory accesses, remote write, cost benefit model, DEC Alpha based parallel systems, DEC-Alpha processor architecture, DEC 8400, scalability, compiler, parallel systems, empirical evaluation, memory architecture, coherency, cache storage, access pattern, spatial locality, local memory, global address space, Cray T3E, Cray T3D, clock speed
2	Wenlong Li, Eric Li, Aamer Jaleel, Jiulong Shan, Yurong Chen, Qigang Wang, Ravi R. Iyer, Ramesh Illikkal, Yimin Zhang, Dong Liu, Michael Liao, Wei Wei, Jinhua Du	Understanding the Memory Performance of Data-Mining Workloads on Small, Medium, and Large-Scale CMPs Using Hardware-Software Co-simulation.	ISPASS	2007	DBLP DOI BibTeX RDF	DRAM caches, small-scale CMP, medium-scale CMP, large-scale CMP, hardware-software co-simulation, terabyte-level workloads, multithreaded data mining applications, cache design, memory performance, multicore systems, memory system performance
2	Antony L. Hosking, Ali-Reza Adl-Tabatabai (eds.)	Proceedings of the 2006 workshop on Memory System Performance and Correctness, San Jose, California, USA, October 11, 2006	Memory System Performance and Correctness	2006	DBLP BibTeX RDF
2	Michael D. Adams 0001, David S. Wise	Seven at one stroke: results from a cache-oblivious paradigm for scalable matrix algorithms.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	Morton-hybrid, parallel processing, paging, quadtrees, Cholesky factorization, cache misses, TLB
2	Mark Aiken, Manuel Fähndrich, Chris Hawblitzel, Galen C. Hunt, James R. Larus	Deconstructing process isolation.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	hardware isolated process (HIP), hardware protection domain, software isolated process (SIP), singularity
2	Jinzhan Peng, Guei-Yuan Lueh, Gansha Wu, Xiaogang Gou, Ryan Rakvic	A comprehensive study of hardware/software approaches to improve TLB performance for java applications on embedded systems.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	TLB performance, Java, embedded system
2	Gregory Buehrer, Yen-Kuang Chen, Srinivasan Parthasarathy, Anthony D. Nguyen, Amol Ghoting, Daehyun Kim	Efficient pattern mining on shared memory systems: implications for chip multiprocessor architectures.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF
2	Shoaib Kamil, Kaushik Datta, Samuel Williams, Leonid Oliker, John Shalf, Katherine A. Yelick	Implicit and explicit optimizations for stencil computations.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF
2	David A. Wood	Keynote talk challenges in chip multiprocessor memory systems.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF
2	Melissa E. O'Neill, F. Warren Burton	Smarter garbage collection with simplifiers.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	lightweight daemon, simplifier, weak pointer, finalizer
2	Lei Jin, Hyunjin Lee, Sangyeun Cho	A flexible data to L2 cache mapping approach for future multicore processors.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	non-uniform cache architecture (NUCA), page allocation
2	Mojtaba Mehrara, Todd M. Austin	Reliability-aware data placement for partial memory protection in embedded processors.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	memory lifetime, partial memory protection, selective data placement, embedded systems, soft errors
2	Kunal Agrawal, Charles E. Leiserson, Jim Sukha	Memory models for open-nested transactions.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF
2	Dan Grossman, Jeremy Manson, William Pugh	What do high-level memory models mean for transactions?	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF
2	Benjamin Hindman, Dan Grossman	Atomicity via source-to-source translation.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	Java, transactional memory, concurrent programming, atomicity
2	Brad Calder, Benjamin G. Zorn (eds.)	Proceedings of the 2005 workshop on Memory System Performance, Chicago, Illinois, USA, June 12, 2005	Memory System Performance	2005	DBLP BibTeX RDF
2	Chris Lattner, Vikram S. Adve	Transparent pointer compression for linked data structures.	Memory System Performance	2005	DBLP DOI BibTeX RDF	pointer compression, cache, static analysis, data layout, recursive data structure
2	Easwaran Raman, David I. August	Recursive data structure profiling.	Memory System Performance	2005	DBLP DOI BibTeX RDF	RDS, dynamic shape graph, list linearization, memory profiling, shape profiling
2	Shoaib Kamil, Parry Husbands, Leonid Oliker, John Shalf, Katherine A. Yelick	Impact of modern memory subsystems on cache optimizations for stencil computations.	Memory System Performance	2005	DBLP DOI BibTeX RDF	performance modeling, prefetch, stencil, cache blocking
2	Yi Feng, Emery D. Berger	A locality-improving dynamic memory allocator.	Memory System Performance	2005	DBLP DOI BibTeX RDF	vam, memory management, virtual memory, paging, fragmentation, allocator, cache locality
2	Kartik Sudeep, Ahmed Gheith	Application analysis using memory pressure.	Memory System Performance	2005	DBLP DOI BibTeX RDF
2	Justin Teller, Charles B. Silio Jr., Bruce L. Jacob	Performance characteristics of MAUI: an intelligent memory system architecture.	Memory System Performance	2005	DBLP DOI BibTeX RDF	MAUI memory architecture, SimpleScalar simulator, data-intensive calculations, intelligent memory, memory architecture, vector processing, SIMD processing
2	Chen Ding, Chengliang Zhang, Xipeng Shen, Mitsunori Ogihara	Gated memory control for memory monitoring, leak detection and garbage collection.	Memory System Performance	2005	DBLP DOI BibTeX RDF	memory usage monitoring, object life, preventive memory management, memory leak, program phase
2	Chen Ding, Stephen Blackburn (eds.)	Proceedings of the 2004 workshop on Memory System Performance, Washington, DC, USA, June 8, 2004	Memory System Performance	2004	DBLP BibTeX RDF
2	Motohiro Kawahito, Hideaki Komatsu, Toshio Nakatani	Instruction combining for coalescing memory accesses using global code motion.	Memory System Performance	2004	DBLP DOI BibTeX RDF	instruction combining, memory access coalescing, Java, JIT compilers, IA-64, 64-bit architectures
2	David Koes, Mihai Budiu, Girish Venkataramani	Programmer specified pointer independence.	Memory System Performance	2004	DBLP DOI BibTeX RDF	pointer independence, alias analysis, memory performance
2	Changpeng Fang, Steve Carr, Soner Önder, Zhenlin Wang	Reuse-distance-based miss-rate prediction on a per instruction basis.	Memory System Performance	2004	DBLP DOI BibTeX RDF	profiling, data locality, reuse distance
2	Qing Yi, Ken Kennedy, Haihang You, Keith Seymour, Jack Dongarra	Automatic blocking of QR and LU factorizations for locality.	Memory System Performance	2004	DBLP DOI BibTeX RDF	LU, locality, blocking, loop optimizations, LAPACK, QR
2	Muhammad Shaaban, Edward Mulrane	Improving trace cache hit rates using the sliding window fill mechanism and fill select table.	Memory System Performance	2004	DBLP DOI BibTeX RDF	branch promotion, fetch mechanisms, fill mechanisms, superscalar processors, cache performance, trace cache
2	Kathryn S. McKinley	Polar opposites: next generation languages and architectures.	Memory System Performance	2004	DBLP DOI BibTeX RDF
2	Michelle Mills Strout, Paul D. Hovland	Metrics and models for reordering transformations.	Memory System Performance	2004	DBLP DOI BibTeX RDF	inspector/executor, locality metrics, run-time reordering transformations, spatial locality graph, temporal locality hypergraph, optimization, data locality
2	Rong Yu, Laxmi N. Bhuyan, Ravi R. Iyer	Comparing the Memory System Performance of DSS Workloads on the HP V-Class and SGI Origin 2000. (PDF / PS)	IPDPS	2002	DBLP DOI BibTeX RDF
2	Amer Diwan, David Tarditi, J. Eliot B. Moss	Memory System Performance of Programs with Intensive Heap Allocation	ACM Trans. Comput. Syst.	1995	DBLP DOI BibTeX RDF	automatic storage reclamation, copying garbage collection, heap allocation, page mode, subblock placement, write through, write-back, write-miss policy, garbage collection, generational garbage collection, write-policy, write-buffer
1	Zoltan Majo, Thomas R. Gross	Memory system performance in a NUMA multicore multiprocessor.	SYSTOR	2011	DBLP DOI BibTeX RDF
1	Yangyang Pan, Guiqiang Dong, Tong Zhang	Exploiting Memory Device Wear-Out Dynamics to Improve NAND Flash Memory System Performance.	FAST	2011	DBLP BibTeX RDF
1	Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos	Temporal streams in commercial server applications.	IISWC	2008	DBLP DOI BibTeX RDF
1	Ibrahim Hur, Calvin Lin	Memory scheduling for modern microprocessors.	ACM Trans. Comput. Syst.	2007	DBLP DOI BibTeX RDF	adaptive history-based scheduling, memory scheduling, Memory system performance
1	Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil Dutt	DRDU: A data reuse analysis technique for efficient scratch-pad memory management.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Scratch-pad memory management, data reuse analysis, memory hierarchy, compiler analysis
1	Onur Mutlu, Thomas Moscibroda	Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors.	MICRO	2007	DBLP DOI BibTeX RDF
1	Laura Grigori, Xiaoye S. Li	Towards an accurate performance modeling of parallel sparse factorization.	Appl. Algebra Eng. Commun. Comput.	2007	DBLP DOI BibTeX RDF	Parallel sparse factorization, Distributed parallel machine, Performance modeling
1	Trishul M. Chilimbi, Ran Shaham	Cache-conscious coallocation of hot data streams.	PLDI	2006	DBLP DOI BibTeX RDF	data profiling, hot data streams, data locality, cache optimization, memory layout, dynamic allocation
1	Nana B. Sam, Martin Burtscher	Improving memory system performance with energy-efficient value speculation.	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF
1	David Wang, Brinda Ganesh, Nuengwong Tuaycharoen, Kathleen Baynes, Aamer Jaleel, Bruce L. Jacob	DRAMsim: a memory system simulator.	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF
1	Resit Sendag, Ying Chen, David J. Lilja	The Impact of Incorrectly Speculated Memory Operations in a Multithreaded Architecture.	IEEE Trans. Parallel Distrib. Syst.	2005	DBLP DOI BibTeX RDF	mispredicted loads, wrong execution, wrong execution cache, prefetching, Speculation, multithreaded architecture
1	Ravi R. Iyer, Jack Perdue, Lawrence Rauchwerger, Nancy M. Amato, Laxmi N. Bhuyan	An Experimental Evaluation of the HP V-Class and SGI Origin 2000 Multiprocessors using Microbenchmarks and Scientific Applications.	International Journal of Parallel Programming	2005	DBLP DOI BibTeX RDF	performance analysis, Parallel architectures, shared memory
1	William Jalby, Christophe Lemuet, X. Le Pasteur	WBTK: a New Set of Microbenchmarks to Explore Memory System Performance for Scientific Computing.	IJHPCA	2004	DBLP DOI BibTeX RDF
1	Daehyun Kim, Mainak Chaudhuri, Mark Heinrich, Evan Speight	Architectural Support for Uniprocessor and Multiprocessor Active Memory Systems.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Active memory systems, address remapping, flexible memory controller architecture, distributed shared memory, cache coherence protocol
1	Yonghong Song, Rong Xu, Cheng Wang, Zhiyuan Li	Improving Data Locality by Array Contraction.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	array contraction, loop shifting, optimization, performance, Compiler, memory, optimizing compilers, data locality
1	Luiz De Rose, Kattamuri Ekanadham, Simone Sbaraglia	An Approach for Symbolic Mapping of Memory References.	Euro-Par	2004	DBLP DOI BibTeX RDF
1	Ravishankar K. Iyer	Performance implications of chipset caches in web servers.	ISPASS	2003	DBLP DOI BibTeX RDF
1	Keith D. Cooper, Li Xu	An efficient static analysis algorithm to detect redundant memory operations.	MSP/ISMM	2002	DBLP DOI BibTeX RDF
1	Siddhartha Chatterjee, Alvin R. Lebeck, Praveen K. Patnala, Mithuna Thottethodi	Recursive Array Layouts and Fast Matrix Multiplication.	IEEE Trans. Parallel Distrib. Syst.	2002	DBLP DOI BibTeX RDF	matrix multiplication, Data layout
1	Abdel-Hameed A. Badawy, Aneesh Aggarwal, Donald Yeung, Chau-Wen Tseng	Evaluating the impact of memory system performance on software prefetching and locality optimizations.	ICS	2001	DBLP DOI BibTeX RDF
1	Sohum Sohoni, Rui Min, Zhiyong Xu, Yiming Hu	A study of memory system performance of multimedia applications.	SIGMETRICS/Performance	2001	DBLP DOI BibTeX RDF
1	Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, J. Ramanujam	Morphable Cache Architectures: Potential Benefits.	LCTES/OM	2001	DBLP DOI BibTeX RDF
1	Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge	High-Performance DRAMs in Workstation Environments.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	DRAM architectures, DRAM performance, DRAM systems, DDR DRAM, Direct Rambus DRAM, PC100 SDRAM, DDR2 DRAM, system modeling
1	Joan-Manuel Parcerisa, Antonio González	Improving Latency Tolerance of Multithreading through Decoupling.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Access/execute decoupling, instruction-level parallelism, simultaneous multithreading, latency hiding, hardware complexity
1	Luiz André Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Ben Verghese	Impact of Chip-Level Integration on Performance of OLTP Workloads.	HPCA	2000	DBLP DOI BibTeX RDF	chip-level integration, database workloads, multiprocessors, memory system performance
1	Ashley Saulsbury, Fredrik Dahlgren, Per Stenström	Recency-based TLB preloading.	ISCA	2000	DBLP DOI BibTeX RDF
1	Siddhartha Chatterjee, Sandeep Sen	Cache-Efficient Matrix Transposition.	HPCA	2000	DBLP DOI BibTeX RDF
1	Lars Friebe, Yoshikazu Yabe, Masato Motomura	A Study of Channeled DRAM Memory Architectures. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
1	Laxmi N. Bhuyan, Ravi R. Iyer, Hu-Jun Wang, Akhilesh Kumar	Impact of CC-NUMA Memory Management Policies on the Application Performance of Multistage Switching Networks.	IEEE Trans. Parallel Distrib. Syst.	2000	DBLP DOI BibTeX RDF	Memory management, shared-memory multiprocessor, wormhole routing, scientific applications, execution-driven simulation, switch design
1	Felix Rauch, Christian Kurmann, Thomas Stricker	Partition Cast - Modelling and Optimizing the Distribution of Large Data Sets in PC Clusters (Distinguished Paper).	Euro-Par	2000	DBLP DOI BibTeX RDF
1	Ravi R. Iyer, Nancy M. Amato, Lawrence Rauchwerger, Laxmi N. Bhuyan	Comparing the memory system performance of the HP V-class and SGI Origin 2000 multiprocessors using microbenchmarks and scientific applications.	International Conference on Supercomputing	1999	DBLP DOI BibTeX RDF
1	Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge	A Performance Comparison of Contemporary DRAM Architectures.	ISCA	1999	DBLP DOI BibTeX RDF
1	Tor E. Jeremiassen	A DSP with Caches-A Study of the GSM-EFR Codec on the TI C6211.	ICCD	1999	DBLP DOI BibTeX RDF	GSM-EFR Speech Codec, Performance, Cache, DSP
1	Doug Joseph, Dirk Grunwald	Prefetching Using Markov Predictors.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	cache, memory, Prefetching
1	Vijay S. Pai, Parthasarathy Ranganathan, Hazim Abdel-Shafi, Sarita V. Adve	The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	performance evaluation, instruction-level parallelism, Shared-memory multiprocessors, software prefetching
1	Sivan Toledo	Improving the memory-system performance of sparse-matrix vector multiplication.	IBM Journal of Research and Development	1997	DBLP DOI BibTeX RDF
1	Sivan Toledo	Improving Memory-System Performance of Sparse Matrix-Vector Multiplication.	PPSC	1997	DBLP BibTeX RDF
1	Doug Burger, Stefanos Kaxiras, James R. Goodman	DataScalar Architectures.	ISCA	1997	DBLP DOI BibTeX RDF
1	Evan Torrie, Margaret Martonosi, Chau-Wen Tseng, Mary W. Hall	Characterizing the Memory Behavior of Compiler-Parallelized Applications.	IEEE Trans. Parallel Distrib. Syst.	1996	DBLP DOI BibTeX RDF	false and true sharing, parallelism granularity, memory hierarchies, shared-memory multiprocessors, Parallelizing compilers, cache performance
1	Thomas Stricker, Thomas R. Gross	Optimizing Memory System Performance for Communication in Parallel Computers.	ISCA	1995	DBLP DOI BibTeX RDF
1	John Chapin, Stephen Alan Herrod, Mendel Rosenblum, Anoop Gupta	Memory System Performance of UNIX on CC-NUMA Multiprocessors.	SIGMETRICS	1995	DBLP DOI BibTeX RDF
1	Jennifer-Ann M. Anderson, Saman P. Amarasinghe, Monica S. Lam	Data and Computation Transformations for Multiprocessors.	PPOPP	1995	DBLP DOI BibTeX RDF
1	Jenlong Wang, Russell W. Quong	The Feasibility of Using Compression to Increase Memory System Performance.	MASCOTS	1994	DBLP BibTeX RDF
1	Karim Harzallah, Kenneth C. Sevcik	Evaluating Memory System Performance of a Large-Scale NUMA Multiprocessor.	MASCOTS	1994	DBLP BibTeX RDF
1	Wen-mei W. Hwu, Thomas M. Conte	The Susceptibility of Programs to Context Switching.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	program susceptibility, memory system performance degradation, single-pass method, recurrence/conflict model, voluntary context switches, involuntary context switches, length distribution, address referencing, cache flushing, SPEC89 benchmarks, simulation, performance evaluation, performance analysis, memory hierarchy, cache memories, memory architecture, buffer storage, multiprogramming, multiprogramming, design space, context switching
1	Jeffrey D. Gee, Alan Jay Smith	The effectiveness of caches for vector processors.	International Conference on Supercomputing	1994	DBLP DOI BibTeX RDF
1	Phillip B. Gibbons, Ephraim Korach	On Testing Cache-Coherent Shared Memories.	SPAA	1994	DBLP DOI BibTeX RDF
1	J. Bradley Chen, Brian N. Bershad	The Impact of Operating System Structure on Memory System Performance.	SOSP	1993	DBLP DOI BibTeX RDF	UNIX, Mach
1	Richard P. LaRowe Jr., Mark A. Holliday, Carla Schlatter Ellis	An Analysis of Dynamic Page Replacement on a NUMA Multiprocessor.	SIGMETRICS	1992	DBLP DOI BibTeX RDF
1	Richard P. LaRowe Jr., Carla Schlatter Ellis, Mark A. Holliday	Evaluation of NUMA Memory Management Through Modeling and Measurements.	IEEE Trans. Parallel Distrib. Syst.	1992	DBLP DOI BibTeX RDF	NUMA memory management, nonuniform memory access time, shared-memoryarchitectures, experimental DUnX operating system kernel, BBNGP1000, highly parameterized dynamic page placement policy, memorysystem performance, local/remote NUMA architecture, approximate mean-value analysistechniques, model predictions, dynamic multiple-copy pageplacement, replication/coherency fault errors, remotely referenced, parallel programs, parallel programming, analytic model, shared memory systems, storage management, storage allocation, experimental data
1	Gaetano Borriello, Andrew R. Cherenson, Peter B. Danzig, Michael N. Nelson	RISCs versus CISCs for Prolog: A Case Study.	ASPLOS	1987	DBLP DOI BibTeX RDF	Prolog, RISC, CISC
1	Yonathan Bard	Application of the Page Survival Index (PSI) to Virtual-Memory System Performance.	IBM Journal of Research and Development	1975	DBLP BibTeX RDF