Search results for "memory wall"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Peter A. Boncz, Martin L. Kersten, Stefan Manegold	Breaking the memory wall in MonetDB.	Commun. ACM	2008	DBLP DOI BibTeX RDF
2	Xian-He Sun	Remove the memory wall: from performance modeling to architecture optimization.	IPDPS	2006	DBLP DOI BibTeX RDF
2	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero	Kilo-instruction processors, runahead and prefetching.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	runahead, prefetching, speculative execution, memory wall, Kilo-instruction processors
2	Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero	Kilo-Instruction Processors: Overcoming the Memory Wall.	IEEE Micro	2005	DBLP DOI BibTeX RDF	in-flight instructions, ROB, superscalar processors, memory wall, issue queue, Kilo-instruction processors
2	Sally A. McKee	Reflections on the memory wall.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	system balance, memory performance
2	Michel Dubois	Fighting the memory wall with assisted execution.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	prefetching, cache memories, superscalar processors, simultaneous multithreading, latency tolerance
2	Marco Galluzzi, Valentin Puente, Adrián Cristal, Ramón Beivide, José-Ángel Gregorio, Mateo Valero	A first glance at Kilo-instruction based multiprocessors.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	ROB, in-flight instructions, shared-memory multiprocessors, CC-NUMA, memory wall, instruction window, Kilo-instruction processors
2	Steven Derrien, Sanjay V. Rajopadhye	FCCMS and the Memory Wall.	FCCM	2000	DBLP DOI BibTeX RDF
1	Rei Odaira, Toshio Nakatani	Continuous object access profiling and optimizations to overcome the memory wall and bloat.	ASPLOS	2012	DBLP DOI BibTeX RDF
1	Niall Douglas	User Mode Memory Page Management: An old idea applied anew to the memory wall problem	CoRR	2011	DBLP BibTeX RDF
1	Sally A. McKee, Robert W. Wisniewski	Memory Wall.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
1	Robert Strzodka, Mohammed Shaheen, Dawid Pajak, Hans-Peter Seidel	Cache Accurate Time Skewing in Iterative Stencil Computations.	ICPP	2011	DBLP DOI BibTeX RDF	memory bound, temporal blocking, memory wall, wavefront, stencil, banded matrix, time skewing
1	Robert Strzodka, Mohammed Shaheen, Dawid Pajak, Hans-Peter Seidel	Cache oblivious parallelograms in iterative stencil computations.	ICS	2010	DBLP DOI BibTeX RDF	memory bound, parallelism and locality, temporal blocking, cache oblivious, memory wall, stencil, time skewing
1	Hui-Dong Zhu, Ye Li	Constant Distance Prefetching for Linked Data Structure Based on CMP.	FCST	2010	DBLP DOI BibTeX RDF	Linked data structure, multi-core and multi-threading, data prefetching, cache misses, memory wall
1	Qi Wu, Jian-Qiang Lu, Kenneth Rose, Tong Zhang	Efficient implementation of decoupling capacitors in 3D processor-dram integrated computing systems.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	three-dimentional integration, dram, decoupling capacitor
1	Konstantis Daloukas, Christos D. Antonopoulos, Nikolaos Bellas	Implementation of a wide-angle lens distortion correction algorithm on the cell broadband engine.	ICS	2009	DBLP DOI BibTeX RDF	cell b.e., heterogeneous multi-core processors, real-time, parallel programming, image warping, stencil computation
1	Susmit Biswas, Diana Franklin, Alan Savage, Ryan Dixon, Timothy Sherwood, Frederic T. Chong	Multi-execution: multicore caching for data-similar executions.	ISCA	2009	DBLP DOI BibTeX RDF	data similar execution, multicore cache design, cmp
1	Pedro Diaz, Marcelo Cintra	Stream chaining: exploiting multiple levels of correlation in data prefetching.	ISCA	2009	DBLP DOI BibTeX RDF	data prefetching
1	Gabriel H. Loh	Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy.	MICRO	2009	DBLP DOI BibTeX RDF
1	Yi Zhao, Jin Shi, Kai Zheng, Haichuan Wang, Haibo Lin, Ling Shao	Allocation wall: a limiting factor of Java applications on emerging multi-core platforms.	OOPSLA	2009	DBLP DOI BibTeX RDF	java, scalability, allocation
1	Seunghwa Kang, David A. Bader	An efficient transactional memory algorithm for computing minimum spanning forest of sparse graphs.	PPOPP	2009	DBLP DOI BibTeX RDF	minimum spanning forest, transactional memory, minimum spanning tree
1	Kamal Sharma, Sanjeev Aggarwal	Energy aware scheduling on desktop grid environment with static performance prediction.	SpringSim	2009	DBLP DOI BibTeX RDF	performance prediction, power-aware computing, resource utilization, execution time estimation
1	Lei Shi, Jun Pang, Lei Yang, Tiejun Zhang, Donghui Wang	Fair-Priority-Expression-Based burst scheduling to enhance performance and fairness of shared dram systems.	CCECE	2009	DBLP DOI BibTeX RDF
1	Pingjing Lu, Yonggang Che, Zhenghua Wang	A Framework for Effective Memory Optimization of High Performance Computing Applications.	HPCC	2009	DBLP DOI BibTeX RDF
1	Vasileios Karakasis, Georgios I. Goumas, Nectarios Koziris	Exploring the effect of block shapes on the performance of sparse kernels.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Mengxiao Liu, Weixing Ji, Xing Pu, Jiaxin Li	A Parallel Memory System Model for Multi-core Processor.	NAS	2009	DBLP DOI BibTeX RDF
1	Amit Hadke, Tony Benavides, S. J. Ben Yoo, Rajeevan Amirtharajah, Venkatesh Akella	OCDIMM: Scaling the DRAM Memory Wall Using WDM Based Optical Interconnects.	Hot Interconnects	2008	DBLP DOI BibTeX RDF
1	Zhimin Gu, Ninghan Zheng, Jie Tang Yan Huang	An analysis and experimental approach to teaching data prefetching on CMP.	Summit on Computing Education in China	2008	DBLP DOI BibTeX RDF	data push, data prefetching
1	Xiaodong Zhang	Research Issues and Challenges to Advance System Software for Multicore Processors and Data-Intensive Applications.	EUC	2008	DBLP DOI BibTeX RDF
1	O. Wohlmuth	Keynote: High performance computing based on FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
1	Marius Grannæs, Magnus Jahre, Lasse Natvig	Low-cost open-page prefetch scheduling in chip multiprocessors.	ICCD	2008	DBLP DOI BibTeX RDF
1	Satyanarayana Nekkalapu, Haitham Akkary, Komal Jothi, Renjith Retnamma, Xiaoyu Song	A simple latency tolerant processor.	ICCD	2008	DBLP DOI BibTeX RDF
1	Craig B. Stunkel	Harnessing massive parallelism in the era of parallelism for the masses.	ICS	2007	DBLP DOI BibTeX RDF
1	Andrew G. Schmidt, Ron Sass	Quantifying Effective Memory Bandwidth of Platform FPGAs.	FCCM	2007	DBLP DOI BibTeX RDF
1	Yu Deng, Xuejun Yang, Xiaobo Yan, Ying Zhang, Jing Du	Implementation and Evaluation of Specific Data-Intensive Scientific Applications on the FT64 Stream Processor.	CIT	2007	DBLP DOI BibTeX RDF
1	Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Ruben Gonzalez, Daniel A. Jiménez, Mateo Valero	A Flexible Heterogeneous Multi-Core Architecture.	PACT	2007	DBLP DOI BibTeX RDF
1	Srinivas Vadlamani, Stephen Jenks	Architectural Considerations for Efficient Software Execution on Parallel Microprocessors.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Partha Biswas, Nikil D. Dutt, Laura Pozzi, Paolo Ienne	Introduction of Architecturally Visible Storage in Instruction Set Extensions.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Yu Deng, Xuejun Yang, Xiaobo Yan, Kun Zeng	Laplace Transformation on the FT64 Stream Processor.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
1	Peng Li, Dongsheng Wang, Haixia Wang, Meijuan Lu, Weimin Zheng	LIRAC: Using Live Range Information to Optimize Memory Access.	ARCS	2007	DBLP DOI BibTeX RDF	LIRAC, Live Range, Cache, Memory Hierarchy, Write Buffer
1	Alberto Ros, Manuel E. Acacio, José M. García	An efficient cache design for scalable glueless shared-memory multiprocessors.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	L2, directory structure, glueless shared-memory multiprocessors, cache, cache coherence, memory wall
1	Ilya Ganusov, Martin Burtscher	Future execution: A prefetching mechanism that uses multiple cores to speed up single threads.	TACO	2006	DBLP DOI BibTeX RDF	Future execution, chip multiprocessors, prefetching, memory wall
1	Alexander Gendler, Avi Mendelson, Yitzhak Birk	A PAB-Based Multi-Prefetcher Mechanism.	International Journal of Parallel Programming	2006	DBLP DOI BibTeX RDF	cache tag pressure, Prefetching, memory wall
1	Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi	Automatic identification of application-specific functional units with architecturally visible storage.	DATE	2006	DBLP DOI BibTeX RDF
1	Jianhua Liu, Michael Chang, Chung-Kuan Cheng	An iterative division algorithm for FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	FPGA, low power, high performance, division
1	Marc Tremblay	A modern high-performance processor pipeline.	ICS	2006	DBLP DOI BibTeX RDF
1	Michael DeLorimier, Nachiket Kapre, Nikil Mehta, Dominic Rizzo, Ian Eslick, Raphael Rubin, Tomas E. Uribe, Thomas F. Knight Jr., André DeHon	GraphStep: A System Architecture for Sparse-Graph Algorithms.	FCCM	2006	DBLP DOI BibTeX RDF
1	Miquel Pericàs, Adrián Cristal, Ruben Gonzalez, Daniel A. Jiménez, Mateo Valero	A decoupled KILO-instruction processor.	HPCA	2006	DBLP DOI BibTeX RDF
1	Peng Li, Dongsheng Wang, Songliu Guo, Tao Tian, Weimin Zheng	Live Range Aware Cache Architecture.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Live Range, Cache, Memory Hierarchy
1	Jason M. McGuiness, Colin Egan, Bruce Christianson, Guang Gao	The Challenges of Efficient Code-Generation for Massively Parallel Architectures.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
1	Kyriakos Stavrou, Pedro Trancoso, Paraskevas Evripidou	Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
1	Xuejun Yang, Yong Dou, Qingfeng Hu	Progress and Challenges in High Performance Computer Technology.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	high performance computer, supercomputer, massively parallel processing
1	Jayaram Mudigonda, Harrick M. Vin, Raj Yavatkar	Overcoming the memory wall in packet processing: hammers or ladders?	ANCS	2005	DBLP DOI BibTeX RDF	multithreading, network processors, data-caches
1	Thomas Y. Yeh, Glenn Reinman	Fast and fair: data-stream quality of service.	CASES	2005	DBLP DOI BibTeX RDF	NUCA, non-uniform access, per thread degradation, cluster, adaptive, cache, distributed, data-stream, partition, embedded, CMP, chip multiprocessor, migration, bandwidth, QOS, phase, memory wall, PDAS
1	Malik Silva	Sparse matrix storage revisited.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	sparse matrix storage, spatial and temporal locality, caches, memory wall, sparse matrix computations
1	Jeffrey T. Draper, Tim Barrett, Jeff Sondeen, Sumit D. Mediratta, Chang Woo Kang, Ihn Kim, Gokhan Daglikoca	A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	memory bandwidth, memory wall, processing-in-memory
1	Kartik Sudeep, Ahmed Gheith	Application analysis using memory pressure.	Memory System Performance	2005	DBLP DOI BibTeX RDF
1	Erich Strohmaier, Hongzhang Shan	Apex-Map: A Global Data Access Benchmark to Analyze HPC Systems and Parallel Programming Paradigms.	SC	2005	DBLP DOI BibTeX RDF
1	Antonis Papanikolaou, Miguel Miranda, Francky Catthoor	Overcoming the "Memory Wall" by improved system design exploration and a link to process technology options.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	combined system design and process technology exploration, optimal energy/delay trade-off exploration in memories
1	Chun Liu, Anand Sivasubramaniam, Mahmut T. Kandemir	Organizing the Last Line of Defense before Hitting the Memory Wall for CMP.	HPCA	2004	DBLP DOI BibTeX RDF
1	Marco Galluzzi, Ramón Beivide, Valentin Puente, José-Ángel Gregorio, Adrián Cristal, Mateo Valero	Evaluating kilo-instruction multiprocessors.	WMPI	2004	DBLP DOI BibTeX RDF	ROB, shared-memory multiprocessors, CC-NUMA, memory wall, instruction window, kilo-instruction processors
1	Adrián Cristal, Oliverio J. Santana, Mateo Valero, José F. Martínez	Toward kilo-instruction processors.	TACO	2004	DBLP DOI BibTeX RDF	multicheckpointing, instruction-level parallelism, Memory wall, kilo-instruction processors
1	Arun Rodrigues, Richard C. Murphy, Peter M. Kogge, Jay B. Brockman, Ron Brightwell, Keith D. Underwood	Implications of a PIM Architectural Model for MPI.	CLUSTER	2003	DBLP DOI BibTeX RDF
1	Jonathan Mangnall, Steven F. Quigley	System Level Simulation of a SIMD Active Memory Enhanced PC (Or, Why We Don't Want 100% Bandwidth Utilisation.	IPDPS	2003	DBLP DOI BibTeX RDF
1	Gene Cooperman, Victor Grinberg	Scalable Parallel Coset Enumeration: Bulk Definition and the Memory Wall.	J. Symb. Comput.	2002	DBLP DOI BibTeX RDF
1	Daehyun Kim, Mainak Chaudhuri, Mark Heinrich	Leveraging cache coherence in active memory systems.	ICS	2002	DBLP DOI BibTeX RDF	active memory, address re-mapping, cache coherence
1	Mark D. Hill	How computer architecture trends may affect future distributed systems: from infiniBand clusters to inter-processor speculation (abstract).	PODC	2000	DBLP DOI BibTeX RDF
1	Krishna M. Kavi, Hyong-Shik Kim, Joseph Arul, Ali R. Hurson	A Decoupled Scheduled Dataflow Multithreaded Architecture.	ISPAN	1999	DBLP DOI BibTeX RDF	Decoupling of memory access, Separate synchronization processor, Multithreaded architecture, Memory wall, Dataflow architecture
1	Ashley Saulsbury, Fong Pong, Andreas Nowatzyk	Missing the Memory Wall: The Case for Processor/Memory Integration.	ISCA	1996	DBLP DOI BibTeX RDF