Search results for "microarchitecture"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
5	Wangyuan Zhang, Xin Fu, Tao Li, José A. B. Fortes	An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures.	ISPASS	2007	DBLP DOI BibTeX RDF	thread-aware reliability optimization, microarchitecture vulnerability, simultaneous multithreaded architecture, semiconductor transient fault, microprocessor reliability, processor throughput, soft error vulnerability analysis, SPEC CPU 2000 benchmark, microarchitecture structure, microarchitecture reliability profile, fetch policy, thread-level parallelism, multithreading architecture
4	John Kim	Low-cost router microarchitecture for on-chip networks.	MICRO	2009	DBLP DOI BibTeX RDF	router microarchitecture, complexity, on-chip network
3	Daniel Schwartz-Narbonne, Carven Chan, Yogesh S. Mahajan, Sharad Malik	Supporting RTL flow compatibility in a microarchitecture-level design framework.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	microarchitecture level, transactions, formal models, hierarchical design, hardware resources
3	Yuchun Ma, Yongxiang Liu, Eren Kursun, Glenn Reinman, Jason Cong	Investigating the effects of fine-grain three-dimensional integration on microarchitecture design.	JETC	2008	DBLP DOI BibTeX RDF	3D packing, microarchitecture, 3D integration, thermal
3	Xin Fu, Tao Li, José A. B. Fortes	NBTI tolerant microarchitecture design in the presence of process variation.	MICRO	2008	DBLP DOI BibTeX RDF
3	Wangyuan Zhang, Tao Li	Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology.	MICRO	2008	DBLP DOI BibTeX RDF
3	Pedro A. Castillo Valdivieso, G. Fernández, Juan Julián Merelo Guervós, José Luis Bernier, Antonio Miguel Mora, Juan Luís Jiménez Laredo, Pablo García-Sánchez	Evolving Machine Microprograms: Application to the CODE2 Microarchitecture.	DCAI	2008	DBLP DOI BibTeX RDF	evolutionary computation techniques, optimization, computer architecture, microarchitecture, microprogramming, automatic design
3	Ronny Ronen, Antonio González	Guest Editors' Introduction: Micro's Top Picks from the Microarchitecture Conferences.	IEEE Micro	2007	DBLP DOI BibTeX RDF	programmable architecture, performance evaluation, fault tolerance, microarchitecture, multicore systems, wireless protocols
3	Chang-Burm Cho, Wangyuan Zhang, Tao Li	Informed Microarchitecture Design Space Exploration Using Workload Dynamics.	MICRO	2007	DBLP DOI BibTeX RDF
3	Niti Madan, Rajeev Balasubramonian	Leveraging 3D Technology for Improved Reliability.	MICRO	2007	DBLP DOI BibTeX RDF	redundant multi-threading, 3D die-stacking, dynamic timing errors, power-efficient microarchitecture, on-chip temperature, reliability, soft errors, parameter variation
3	Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe	Statistical sampling of microarchitecture simulation.	ACM Trans. Model. Comput. Simul.	2006	DBLP DOI BibTeX RDF	Microarchitecture simulation, SPEC CPU2000 simulation, cold-start bias, simulation sampling, statistical sampling
3	Grigorios Magklis, Pedro Chaparro, José González, Antonio González	Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture.	ISLPED	2006	DBLP DOI BibTeX RDF	MCD, energy efficiency, DVS, microarchitecture, GALS
3	Vidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar	Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis.	ISLPED	2006	DBLP DOI BibTeX RDF	floorplanning, microarchitecture, transient analysis
3	Bryan Black, Murali Annavaram, Ned Brekelbaum, John DeVale, Lei Jiang, Gabriel H. Loh, Don McCaule, Pat Morrow, Donald W. Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadasivan Shankar, John Paul Shen, Clair Webb	Die Stacking (3D) Microarchitecture.	MICRO	2006	DBLP DOI BibTeX RDF
3	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Application-specific customization of soft processor microarchitecture.	FPGA	2006	DBLP DOI BibTeX RDF	Nios, RTL generation, SPREE, FPGA, customization, embedded processor, ASIP, microarchitecture, application specific, soft processor
3	Sarita V. Adve, Pia Sanda	Guest Editors' Introduction: Reliability-Aware Microarchitecture.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Reliability-aware microarchitecture, reliability management, soft errors, CMOS scaling
3	Tzvetan S. Metodi, Darshan D. Thaker, Andrew W. Cross	A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation.	MICRO	2005	DBLP DOI BibTeX RDF
3	Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar	Microarchitecture-aware floorplanning using a statistical design of experiments approach.	DAC	2005	DBLP DOI BibTeX RDF	floorplanning, microarchitecture, wire pipelining
3	Stamatis Vassiliadis, Leonel Sousa, Georgi Gaydadjiev	The Midlifekicker Microarchitecture Evaluation Metric.	ASAP	2005	DBLP DOI BibTeX RDF	pipeline, microarchitecture, ILP
3	Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan	The microarchitecture of FPGA-based soft processors.	CASES	2005	DBLP DOI BibTeX RDF	Nios, RTL generation, SPREE, application specic tradeoff, FPGA, pipeline, exploration, embedded processor, ASIP, microarchitecture, soft processor
3	Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe	TurboSMARTS: accurate microarchitecture simulation sampling in minutes.	SIGMETRICS	2005	DBLP DOI BibTeX RDF	checkpointed microarchitecture simulation, simulation sampling
3	Jason Cong, Ashok Jagannathan, Glenn Reinman, Michail Romesis	Microarchitecture evaluation with physical planning.	DAC	2003	DBLP DOI BibTeX RDF	microarchitecture evaluation, physical planning
3	Greg Semeraro, David H. Albonesi, Steve Dropsho, Grigorios Magklis, Sandhya Dwarkadas, Michael L. Scott	Dynamic frequency and voltage control for a multiple clock domain microarchitecture.	MICRO	2002	DBLP DOI BibTeX RDF
3	Chen-Yong Cher, T. N. Vijaykumar	Skipper: a microarchitecture for exploiting control-flow independence.	MICRO	2001	DBLP DOI BibTeX RDF
3	Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen	A Buffer-Oriented Methodology for Microarchitecture Validation.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	processor validation, superscalar microarchitecture, design validation
3	Balakrishnan Iyer, Ramesh Karri, Israel Koren	Phantom redundancy: a high-level synthesis approach for manufacturability.	ICCAD	1995	DBLP DOI BibTeX RDF	fabrication-time reconfigurability, functional unit failure, microarchitecture synthesis, phantom redundancy, genetic algorithm, high level synthesis, high-level synthesis, redundancy, logic design, reconfigurable architectures, manufacturability, microarchitecture, circuit CAD
3	Rahul Razdan, Michael D. Smith	A high-performance microarchitecture with hardware-programmable functional units.	MICRO	1994	DBLP DOI BibTeX RDF	automatic instruction set design, compile-time optimization, general-purpose microarchitectures, logic synthesis, programmable logic
3	Yale N. Patt	Microarchitecture choices (implementation of the VAX).	MICRO	1989	DBLP DOI BibTeX RDF	VAX
3	Edil S. Tavares Fernandes	Microarchitecture modelling through ADL.	MICRO	1988	DBLP DOI BibTeX RDF
3	James E. Wilson, Stephen W. Melvin, Michael Shebanow, Wen-mei W. Hwu, Yale N. Patt	On tuning the microarchitecture of an HPS implementation of the VAX.	MICRO	1987	DBLP DOI BibTeX RDF
2	Jason Cong, Yiping Fan, Junjuan Xu	Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	distributed register file, Behavioral synthesis, resource binding
2	Radu Marculescu, Ümit Y. Ogras, Li-Shiuan Peh, Natalie D. Enright Jerger, Yatin Vasant Hoskote	Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
2	Gabriel H. Loh, Samantika Subramaniam, Yuejian Xie	Zesto: A cycle-level simulator for highly detailed microarchitecture exploration.	ISPASS	2009	DBLP DOI BibTeX RDF
2	Mahesh Ketkar, Eli Chiprout	A microarchitecture-based framework for pre- and post-silicon power delivery analysis.	MICRO	2009	DBLP DOI BibTeX RDF
2	Andrew Brownfield, Cindy Norris	LC3uArch: a graphical simulator of the LC-3 microarchitecture.	SIGCSE	2009	DBLP DOI BibTeX RDF	computer architecture, computer organization
2	Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu, Siva Kumar Sastry Hari, Sarita V. Adve	Accurate microarchitecture-level fault modeling for studying hardware faults.	HPCA	2009	DBLP DOI BibTeX RDF
2	Christophe Dubach, Timothy M. Jones, Edwin V. Bonilla, Grigori Fursin, Michael F. P. O'Boyle	Portable compiler optimisation across embedded programs and microarchitectures using machine learning.	MICRO	2009	DBLP DOI BibTeX RDF	architecture/compiler co-design, machine learning, design-space exploration
2	Balaram Sinharoy	POWER7 multi-core processor design.	MICRO	2009	DBLP DOI BibTeX RDF
2	Pedro Chaparro, José González, Qiong Cai, Greg Chrysler	Dynamic thermal management using thin-film thermoelectric cooling.	ISLPED	2009	DBLP DOI BibTeX RDF	thermal control, thin-film thermoelectric cooling, low-power, microarchitecture, dynamic thermal management
2	Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González, Oguz Ergin	Exploring the limits of early register release: Exploiting compiler analysis.	TACO	2009	DBLP DOI BibTeX RDF	compiler, energy efficiency, Low-power design, microarchitecture, register file
2	Francesco Vitullo, Nicola E. L'Insalata, Esa Petri, Sergio Saponara, Luca Fanucci, Michele Casula, Riccardo Locatelli, Marcello Coppola	Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
2	Xin Fu, Tao Li, José A. B. Fortes	Combined circuit and microarchitecture techniques for effective soft error robustness in SMT processors.	DSN	2008	DBLP DOI BibTeX RDF
2	Man-Lap Li, Pradeep Ramachandran, Swarup Kumar Sahoo, Sarita V. Adve, Vikram S. Adve, Yuanyuan Zhou	Trace-based microarchitecture-level diagnosis of permanent hardware faults.	DSN	2008	DBLP DOI BibTeX RDF
2	Vimal K. Reddy, Eric Rotenberg	Coverage of a microarchitecture-level fault check regimen in a superscalar processor.	DSN	2008	DBLP DOI BibTeX RDF
2	Charles R. Moore	Microarchitecture in the system-level integration era.	MICRO	2008	DBLP DOI BibTeX RDF
2	Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason A. Blome, Scott A. Mahlke	StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems.	CASES	2008	DBLP DOI BibTeX RDF	reliability, architecture, pipeline, multicore
2	Frederico Pratas, Georgi Gaydadjiev, Mladen Berekovic, Leonel Sousa, Stefanos Kaxiras	Low power microarchitecture with instruction reuse.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	loop reusing technique, reorder buffer optimization, superscalar processor, power reduction
2	Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari, Josep Torrellas	EVAL: Utilizing processors with variation-induced timing errors.	MICRO	2008	DBLP DOI BibTeX RDF
2	Pedro A. Castillo Valdivieso, G. Fernández, Antonio Mora García, Juan Julián Merelo Guervós, José Luis Bernier, Alberto Prieto	Evolving machine microprograms.	GECCO	2008	DBLP DOI BibTeX RDF	evolutionary computation techniques, optimization, computer architecture, microarchitecture, microprogramming, automatic design
2	Zhonglei Wang, Antonio Sanchez, Andreas Herkersdorf	SciSim: a software performance estimation framework using source code instrumentation.	WOSP	2008	DBLP DOI BibTeX RDF	debugging information, software performance estimation, source code instrumentation, microarchitecture
2	José Manuel Colmenar, Noelia Morón, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo	Modelling Asynchronous Systems using Probability Distribution Functions.	PDP	2008	DBLP DOI BibTeX RDF	modelling, asynchronous, microarchitecture
2	Kenneth Hoste, Lieven Eeckhout	Microarchitecture-Independent Workload Characterization.	IEEE Micro	2007	DBLP DOI BibTeX RDF	workload characterization, modeling techniques, measurement techniques, performance attributes
2	Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He	Microarchitecture Configurations and Floorplanning Co-Optimization.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Yogesh S. Mahajan, Carven Chan, Ali Alphan Bayazit, Sharad Malik, Wei Qin	Verification Driven Formal Architecture and Microarchitecture Modeling.	MEMOCODE	2007	DBLP DOI BibTeX RDF
2	Kapil Vaswani, Matthew J. Thazhuthaveetil, Y. N. Srikant, P. J. Joseph	Microarchitecture Sensitive Empirical Models for Compiler Optimizations.	CGO	2007	DBLP DOI BibTeX RDF
2	Martin Zabel, Thomas B. Preußer, Peter Reichel, Rainer G. Spallek	Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture.	DSD	2007	DBLP DOI BibTeX RDF
2	Yogesh S. Mahajan, Sharad Malik	Automating Hazard Checking in Transaction-Level Microarchitecture Models.	FMCAD	2007	DBLP DOI BibTeX RDF
2	Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato	VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors.	PACT	2007	DBLP DOI BibTeX RDF
2	Stijn Eyerman, Lieven Eeckhout, James E. Smith	Studying Compiler-Microarchitecture Interactions through Interval Analysis.	PACT	2007	DBLP DOI BibTeX RDF
2	Kyoung-Hwan Lim, YongHwan Kim, Taewhan Kim	Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture.	DAC	2007	DBLP DOI BibTeX RDF
2	Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee	Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling.	ASP-DAC	2007	DBLP DOI BibTeX RDF	wire-length driven floorplan, noise-direct, power supply noise aware floorplanning, microarchitecture profiling, aggressive power saving techniques, power delivery network, power consumption reduction, self weighting, correlation weighting, force-directed floorplanning algorithm, power pin affinity, current consumption, di/dt control, supply-noise margin violations, clock-gating, microprocessor designers, power constraints, inductive noise, decoupling capacitances
2	Hushrav Mogal, Kia Bazargan	Microarchitecture floorplanning for sub-threshold leakage reduction.	DATE	2007	DBLP DOI BibTeX RDF
2	Rong Ji, Xianjun Zeng, Liang Chen, Junfeng Zhang	The Implementation and Design of a Low-Power Clock Distribution Microarchitecture.	IEEE NAS	2007	DBLP DOI BibTeX RDF
2	Kiran Puttaswamy, Gabriel H. Loh	Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors.	HPCA	2007	DBLP DOI BibTeX RDF
2	Phillip Stanley-Marbell, Diana Marculescu	Sunflower : Full-System, Embedded Microarchitecture Evaluation.	HiPEAC	2007	DBLP DOI BibTeX RDF
2	Fei Guo, Yan Solihin, Li Zhao, Ravishankar Iyer	A Framework for Providing Quality of Service in Chip Multi-Processors.	MICRO	2007	DBLP DOI BibTeX RDF
2	Christophe Dubach, Timothy M. Jones, Michael F. P. O'Boyle	Microarchitectural Design Space Exploration Using an Architecture-Centric Approach.	MICRO	2007	DBLP DOI BibTeX RDF
2	Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks	Process Variation Tolerant 3T1D-Based Cache Architectures.	MICRO	2007	DBLP DOI BibTeX RDF
2	Ahmed M. Amin, Mithuna Thottethodi, T. N. Vijaykumar, Steven Wereley, Stephen C. Jacobson	Aquacore: a programmable architecture for microfluidics.	ISCA	2007	DBLP DOI BibTeX RDF	fluidic, fluidic microarchitecture, programmable lab on a chip, microfluidics, instruction set
2	Niranjan Soundararajan, Angshuman Parashar, Anand Sivasubramaniam	Mechanisms for bounding vulnerabilities of processor structures.	ISCA	2007	DBLP DOI BibTeX RDF	redundant threading, microarchitecture, transient faults
2	Xianfeng Li, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra, Xu Cheng	A Retargetable Software Timing Analyzer Using Architecture Description Language.	ASP-DAC	2007	DBLP DOI BibTeX RDF	retargetable software timing analyzer, static WCET analysis, program path analysis, microarchitecture modeling, graph-based execution models, pipeline model, real-time systems, architecture description language, worst case execution time, embedded processors, branch prediction, schedulability analysis
2	David H. Albonesi	Standing on Solid Ground.	IEEE Micro	2007	DBLP DOI BibTeX RDF	interconnects for multicore chips, special-purpose chips, debugging, human-computer interface, microarchitecture, programmability
2	Tingting Sha, Milo M. K. Martin, Amir Roth	NoSQ: Store-Load Communication without a Store Queue.	IEEE Micro	2007	DBLP DOI BibTeX RDF	microarchitecture, RISC, pipeline processors, VLIW architectures, CISC
2	Toshinori Sato, Yuji Kunitake	Exploiting Input Variations for Energy Reduction.	PATMOS	2007	DBLP DOI BibTeX RDF	typical-case design, dynamic retiming, reliable microarchitecture, robust microarchitecture, DVFS, deep sub-micron
2	Olivier Rochecouste, Gilles Pokam, André Seznec	A case for a complexity-effective, width-partitioned microarchitecture.	TACO	2006	DBLP DOI BibTeX RDF	Power analysis
2	Pradip Bose	Workload characterization: A key aspect of microarchitecture design.	IEEE Micro	2006	DBLP DOI BibTeX RDF	target workloads, microarchitecture design, workload characterization
2	Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter	Leveraging Wire Properties at the Microarchitecture Level.	IEEE Micro	2006	DBLP DOI BibTeX RDF	interconnections, multiprocessor systems, interprocessor communications, energy-aware systems, interconnection architectures, advanced technologies
2	Xinping Zhu, Wei Qin, Sharad Malik	Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	Shobana Padmanabhan, Ron K. Cytron, Roger D. Chamberlain, John W. Lockwood	Automatic application-specific microarchitecture reconfiguration.	IPDPS	2006	DBLP DOI BibTeX RDF
2	Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe	Statistical sampling of microarchitecture simulation.	IPDPS	2006	DBLP DOI BibTeX RDF
2	Xin Fu, James Poe, Tao Li, José A. B. Fortes	Characterizing Microarchitecture Soft Error Vulnerability Phase Behavior.	MASCOTS	2006	DBLP DOI BibTeX RDF
2	YongKang Zhu, David H. Albonesi	Localized microarchitecture-level voltage management.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Kenneth Hoste, Lieven Eeckhout	Comparing Benchmarks Using Key Microarchitecture-Independent Characteristics.	IISWC	2006	DBLP DOI BibTeX RDF
2	Jason Cong, Yiping Fan, Wei Jiang	Platform-based resource binding using a distributed register-file microarchitecture.	ICCAD	2006	DBLP DOI BibTeX RDF	distributed register file, behavior synthesis, resource binding
2	Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou	Yield-Aware Cache Architectures.	MICRO	2006	DBLP DOI BibTeX RDF
2	Noel Eisley, Li-Shiuan Peh, Li Shang	In-Network Cache Coherence.	MICRO	2006	DBLP DOI BibTeX RDF
2	Samantika Subramaniam, Gabriel H. Loh	Fire-and-Forget: Load/Store Scheduling with No Store Queue at All.	MICRO	2006	DBLP DOI BibTeX RDF
2	Tingting Sha, Milo M. K. Martin, Amir Roth	NoSQ: Store-Load Communication without a Store Queue.	MICRO	2006	DBLP DOI BibTeX RDF
2	Sangyeun Cho, Lei Jin	Managing Distributed, Shared L2 Caches through OS-Level Page Allocation.	MICRO	2006	DBLP DOI BibTeX RDF
2	Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger	Distributed Microarchitectural Protocols in the TRIPS Prototype Processor.	MICRO	2006	DBLP DOI BibTeX RDF
2	Benjamin C. Lee, David M. Brooks	Accurate and efficient regression modeling for microarchitectural performance and power prediction.	ASPLOS	2006	DBLP DOI BibTeX RDF	simulation, statistics, regression, inference, microarchitecture
2	Angshuman Parashar, Anand Sivasubramaniam, Sudhanva Gurumurthi	SlicK: slice-based locality exploitation for efficient redundant multithreading.	ASPLOS	2006	DBLP DOI BibTeX RDF	backward slice extraction, redundant threading, microarchitecture, transient faults
2	Robert P. Colwell	The Pentium Chronicles: Introduction.	IEEE Computer	2006	DBLP DOI BibTeX RDF	Professional conduct, P6 microarchitecture, Project management, Microprocessors
2	Michael J. Schulte, John Glossner, Sanjay Jinturkar, Mayan Moudgill, Suman Mamidi, Stamatis Vassiliadis	A Low-Power Multithreaded Processor for Software Defined Radio.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	low power, wireless communication, computer architecture, multithreading, microarchitecture, Software Defined Radio, processor design
2	Shobana Padmanabhan, Phillip H. Jones, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger D. Chamberlain, Ron Cytron, Jason E. Fritts, John W. Lockwood	Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures.	International Journal of Parallel Programming	2005	DBLP DOI BibTeX RDF	cycle-accurate hardware profiling, performance, architecture, Reconfigurable
2	Diana Marculescu, Emil Talpes	Energy Awareness and Uncertainty in Microarchitecture-Level Design.	IEEE Micro	2005	DBLP DOI BibTeX RDF	gate length, on-chip temperature variations, variability metric, Energy awareness
2	Weiping Liao, Lei He, Kevin M. Lepak	Temperature and supply Voltage aware performance and power modeling at microarchitecture level.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
2	Weiping Liao, Joseph M. Basile, Lei He	Microarchitecture-level leakage reduction with data retention.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
2	Emil Talpes, Diana Marculescu	Execution cache-based microarchitecture for power-efficient superscalar processors.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
2	Weiwu Hu, Fuxin Zhang, Zusong Li	Microarchitecture of the Godson-2 Processor.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	superscalar pipeline, dynamic scheduling non-blocking cache, load speculation, branch prediction, out-of-order execution, register renaming