Search results for "microprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
5	Junichi Hirase, Shinichi Yoshimura	Faster processing for microprocessor functional ATPG.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	microprocessor functional ATPG, fault coverage improvement, short test pattern, processing speed increase, logic testing, integrated circuit testing, automatic test pattern generation, identification, test pattern generation, functional testing, microprocessor chips, instruction sets, instruction sets, microprocessor tests
5	Carlos Montemayor, Marie Sullivan, Jen-Tien Yen, Pete Wilson, Richard Evers, K. R. Kishore	The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	PowerPC 603e microprocessor, low-power superscalar microprocessor, portable products, on-chip instruction, cache associativity, bus modes, 120 SPECint92, 105 SPECfp92, die size, software controllable power-down modes, power saving capability, 16 Kbyte, performance evaluation, performance, computer architecture, system design, power consumption, data cache, cache storage, microprocessor chips, frequency, system buses, portable computers, portable computers, transistors, 100 MHz
4	William Lloyd Bircher, Lizy K. John	Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events.	ISPASS	2007	DBLP DOI BibTeX RDF	power sensing hardware, complete system power estimation, microprocessor performance event, microprocessor performance counter, online measurement, complete system power consumption, microprocessor power, on-chip performance event counter, system power consumption estimation, power model
4	Hyun-Gyu Kim, Hyeong-Cheol Oh	A DSP-Enhanced 32-Bit Embedded Microprocessor.	EUC	2005	DBLP DOI BibTeX RDF	DSP-enhanced microprocessor, hardware address generator, register extension, embedded microprocessor, SIMD
4	Murat Aydos, T. Yanik, Çetin Kaya Koç	An High-Speed ECC-based Wireless Authentication Protocol on an ARM Microprocessor.	ACSAC	2000	DBLP DOI BibTeX RDF	high-speed ECC-based wireless authentication, ARM microprocessor, elliptic curve digital signature algorithm, ARM7TDMI processor, core processor, 80 MHz, 160 bit, mobile computing, elliptic curve cryptography, public key cryptography, software libraries, software library, authorisation, microprocessor chips, message authentication, portable computers, ECDSA, 32 bit, wireless applications
4	Shannon V. Morton, Sam S. Appleton, Michael J. Liebelt	ECSTAC: a fast asynchronous microprocessor.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous microprocessor, ECSTAC, two-phase communication, processor pipeline, register tagging, branch techniques, block simulation, caches, logic design, asynchronous circuits, microprocessor chips
4	Thomas D. Burd, Robert W. Brodersen	Energy efficient CMOS microprocessor design.	HICSS	1995	DBLP DOI BibTeX RDF	energy efficient CMOS microprocessor design, portable electronics, battery weight, battery size, heat dissipation, computation modes, power analysis methodology, energy efficiency quantification, computer architecture, computer architectures, throughput, parallel machines, energy consumption, energy conservation, microprocessor chips, design principles, power dissipation, CMOS digital integrated circuits, integrated circuit modelling, cooling, figures of merit, desktop computers
3	Rupesh S. Shelar, Marek Patyra	Impact of local interconnects on timing and power in a high performance microprocessor.	ISPD	2010	DBLP DOI BibTeX RDF	CAD, delay, interconnects, power, microprocessor
3	Charles F. Webb	IBM z10: The Next-Generation Mainframe Microprocessor.	IEEE Micro	2008	DBLP DOI BibTeX RDF	high-frequency design, decimal floating-point, reliability, pipeline, microprocessor, branch prediction, accelerators, symmetric multiprocessor (SMP), mainframe, Hot Chips 19
3	Da Wang, Yu Hu, Huawei Li, Xiaowei Li	Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	microprocessor design-for-testability, built-in self-test, test generation, at-speed testing
3	Desta Tadesse, R. Iris Bahar, Joel Grodstein	Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation.	VTS	2008	DBLP DOI BibTeX RDF	Microprocessor Diagnosis, Pass/Fail Region, Maximum Likelihood Estimation, Silicon Debug
3	Fu-Ching Yang, Ing-Jer Huang	An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software Tools.	ASP-DAC	2007	DBLP DOI BibTeX RDF	16 bit, ARM7 software tools, THUMB instruction set microprocessor, short-precision computing
3	Wei Li, Daniel Blakely, Scott Van Sooy, Keven Dunn, David Kidd, Robert Rogenmoser, Dian Zhou	LVS verification across multiple power domains for a quad-core microprocessor.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	LVS, multi-core microprocessor, physical verification
3	Shlomi Dolev, Yinnon A. Haviv	Self-Stabilizing Microprocessor: Analyzing and Overcoming Soft Errors.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Self-stabilization, microprocessor, soft errors, single event upset
3	Koichi Sato, Brian L. Evans, J. K. Aggarwal	Designing an Embedded Video Processing Camera Using a 16-bit Microprocessor for a Surveillance System.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	temporal spatio-velocity transform, embedded system, interaction, tracking, video, recognition, microprocessor, surveillance, DRAM, velocity, Ptolemy
3	Eric S. Fetzer	Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	dual core, Itanium microprocessor, Montecito, adaptive circuits, cache safe technology, active clock deskew, process variation, power measurement
3	Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis	Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates.	SBCCI	2006	DBLP DOI BibTeX RDF	fault-tolerant microprocessor, soft errors, single event upsets, single event transients
3	Noriyuki Ito, Akira Kanuma, Daisuke Maruyama, Hitoshi Yamanaka, Tsuyoshi Mochizuki, Osamu Sugawara, Chihiro Endoh, Masahiro Yanagida, Takeshi Kono, Yutaka Isoda, Kazunobu Adachi, Takahisa Hiraide, Shigeru Nagasawa, Yaroku Sugiyama, Eizo Ninoi	Delay defect screening for a 2.16GHz SPARC64 microprocessor.	ASP-DAC	2006	DBLP DOI BibTeX RDF	delay defect, microprocessor, screening, at-speed
3	Noriyuki Ito, Hideaki Katagiri, Ryoichi Yamashita, Hiroshi Ikeda, Hiroyuki Sugiyama, Hiroaki Komatsu, Yoshiyasu Tanamura, Akihiro Yoshitake, Kazuhiro Nonomura, Kinya Ishizaka, Hiroaki Adachi, Yutaka Mori, Yutaka Isoda, Yaroku Sugiyama	Diagonal routing in high performance microprocessor design.	ASP-DAC	2006	DBLP DOI BibTeX RDF	diagonal routing, manhattan routing, microprocessor
3	Jaime H. Moreno	Chip-level integration: the new frontier for microprocessor architecture.	SPAA	2006	DBLP DOI BibTeX RDF	chip-level integration, microprocessor architecture
3	Ioannis Panagopoulos, Christos Pavlatos, George K. Papakonstantinou	An Embedded Microprocessor for Intelligent Control.	Journal of Intelligent and Robotic Systems	2005	DBLP DOI BibTeX RDF	embedded systems, logic programming, microprocessor, intelligent control, RISC, declarative programs
3	Yue Luo, Lizy Kurian John, Lieven Eeckhout	SMA: A Self-Monitored Adaptive Cache Warm-Up Scheme for Microprocessor Simulation.	International Journal of Parallel Programming	2005	DBLP DOI BibTeX RDF	Microprocessor simulation, cache warm-up, simulation time reduction, sampling
3	Seokkee Kim, Soo-Ik Chae	Complexity reduction in an nRERL microprocessor.	ISLPED	2005	DBLP DOI BibTeX RDF	buffer skipping, clocked power generator (CPG), nMOS reversible energy recovery logic (nRERL), reversibility breaking, microprocessor, complexity reduction
3	Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante	Automatic generation of test sets for SBST of microprocessor IP cores.	SBCCI	2005	DBLP DOI BibTeX RDF	FPGA, hardware accelerator, automatic test generation, pipelined architectures, microprocessor test, test programs
3	Seokkee Kim, Soo-Ik Chae	Implementation of a simple 8-bit microprocessor with reversible energy recovery logic.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	clocked power generator (CPG), nMOS reversible energy recovery logic (nRERL), phase scheduling, reversibility breaking, microprocessor
3	Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores.	MTV	2005	DBLP DOI BibTeX RDF
3	Luca Benini, Francesco Menichelli, Mauro Olivieri	A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Microprocessor/microcomputer applications, low-power design, code compression
3	Fadi Busaba, Timothy J. Slegel, Steven R. Carlough, Christopher A. Krygowski, John G. Rell	The design of the fixed point unit for the z990 microprocessor.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	superscalar FXU, microprocessor
3	Mark Aagaard, Byron Cook, Nancy A. Day, Robert B. Jones	A framework for superscalar microprocessor correctness statements.	STTT	2003	DBLP DOI BibTeX RDF	Microprocessor correctness, Commuting diagrams, Formal verification, Pipelines
3	Nguyen Quang Trung, Artur Kokoszka, Krystyna Siekierska, Adam Pawlak, Dariusz Obrebski, Norbert Lugowski	Organization of a Microprocessor Design Process Using Internet-Based Interoperable Workflows. (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF	Virtual Component, Interoperability, Workflow, VHDL, IP, Microprocessor, Microcontroller, Collaborative Engineering
3	Mohammad H. Tehranipour, Mehrdad Nourani	Signal Integrity Loss in SoC's Interconnects: A Diagnosis Approach Using Embedded Microprocessor.	ITC	2002	DBLP DOI BibTeX RDF	Embedded Microprocessor, Integrity Loss, System-on-Chip, Diagnosis, Test Pattern Generation, Signal Integrity, Interconnect Testing, Noise Detection
3	Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau, Timothy Kam, Michael Kishinevsky, Shai Rotem	Coordinated transformations for high-level synthesis of high performance microprocessor blocks.	DAC	2002	DBLP DOI BibTeX RDF	high-level synthesis, microprocessor design
3	Yuichiro Takamizawa, Kouhei Nadehara, Max Boegli, Masao Ikekawa, Ichiro Kuroda	MPEG-2 AAC 5.1-Channel Decoder Software for a Low-Power Embedded RISC Microprocessor.	VLSI Signal Processing	2001	DBLP DOI BibTeX RDF	microprocessor, decoder, MPEG, AAC
3	Stanislav Polonsky, Moyra K. McManus, Daniel R. Knebel, Steve Steen, Pia Sanda	Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	imaging circuit analysis, IBM G6 microprocessor, non-invasive backside timing, Picosecond Imaging Circuit Analysis, waveform extraction, integrated circuit testing, timing analysis, race condition, circuit switching, integrated memory circuits, hazards and race conditions, L1 cache
3	Stephen D. Posluszny, N. Aoki, David Boerstler, P. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, N. Kojima, Ohsang Kwon, K. Lee, D. Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia	"Timing closure by design, " a high frequency microprocessor design methodology.	DAC	2000	DBLP DOI BibTeX RDF	chip integration, dynamic circuits0, CAD, methodology, microprocessor, timing analysis, PLA, timing closure
3	Nandu Tendolkar, Robert F. Molyneaux, Carol Pyron, Rajesh Raina	At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor.	VTS	2000	DBLP DOI BibTeX RDF	delay testing, at-speed testing, microprocessor testing
3	Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng	On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set.	VTS	2000	DBLP DOI BibTeX RDF	Microprocessor self-testing, Path delay fault classification, Functionally testable paths, Functional tests, Delay fault testing
3	Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante	A genetic algorithm-based system for generating test programs for microprocessor IP cores.	ICTAI	2000	DBLP DOI BibTeX RDF	industrial property, genetic algorithm based system, test program generation, microprocessor IP cores, digital systems design trend, design-and-reuse paradigm, intellectual property cores, encrypted gate-level netlist, testability problems, automatic approach, processor cores, fault coverage figures, random approach, genetic algorithms, genetic algorithms, microprocessor chips, automatic test software, test program, electronic engineering computing
3	Erik A. McShane, Krishna Shenai, Leon Alkalai, E. Kolawa, V. Boyadzhyan, B. Blaes, Wai-Chi Fang	Monolithic Microprocessor and RF Transceiver in 0.25-micron FDSOI CMOS.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	Mixed-signal VLSI, VLSI circuits process for mixed-signal VLSI in a die size measuring 2.2 mm x 2.2 mm, low-power, microprocessor, RF
3	Tom Thomas, Brian Anthony	Area, Performance, and Yield Implications of Redundancy in On-Chip Caches.	ICCD	1999	DBLP DOI BibTeX RDF	cache, redundancy, microprocessor, yield, SRAM, yield enhancement, microprocessor design, embedded SRAM
3	Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda	EXFI: a low-cost fault injection system for embedded microprocessor-based boards.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	microprocessor systems, software-implemented fault injection, trace exception mode, fault injection, fault coverage
3	Kåre T. Christensen, Peter Jensen, Peter Korger, Jens Sparsø	The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor Core. (PDF / PS)	ASYNC	1998	DBLP DOI BibTeX RDF	Asynchronous circuits and systems, low-power, microprocessor design
3	Marc Renaudin, Pascal Vivet, Frédéric Robin	ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor.	ASYNC	1998	DBLP DOI BibTeX RDF	asynchronous microprocessor, quasi-delay-insensitive circuits, standard-cell asynchronous design
3	Toshihiro Hattori, Yusuke Nitta, Mitsuho Seki, Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, Ryuichi Satomura	Design Methodology of a 200MHz Superscalar Microprocessor: SH-4.	DAC	1998	DBLP DOI BibTeX RDF	verification, timing, design methodology, microprocessor
3	John Matthews, Byron Cook, John Launchbury	Microprocessor Specification in Hawk. (PDF / PS)	ICCL	1998	DBLP DOI BibTeX RDF	Microprocessor Verification, Domain-Specific Language, Functional Language, Hardware Verification
3	Daniel Audet, Steve Masson, Yvon Savaria	Reducing Fault Sensitivity of Microprocessor-Based Systems by Modifying Workload Structure. (PDF / PS)	DFT	1998	DBLP DOI BibTeX RDF	bit flip, fault-tolerance, memory, microprocessor, fault injection, software fault-tolerance, transient faults
3	S. Srivastava, S. C. Bose, B. P. Mathur, Arti Noor, Raj Singh, A. S. Mandal, K. Prabhakaran, A. Karmakar, Chandra Shekhar, Sudhir Kumar, Amit K. Agarwal	Evolution of Architectural Concepts and Design Methods of Microprocessors.	VLSI Design	1998	DBLP DOI BibTeX RDF	Microprocessor Evolution, Synthesis, VHDL, Microprocessor Design
3	Bogdan Kasztenny, Eugeniusz Rosolowski	A digital protective relay as a real-time microprocessor system.	ECBS	1997	DBLP DOI BibTeX RDF	power system protection, digital protective relay, real-time microprocessor system, protection system, hardware, power system, software structures
3	D. L. Grundy, M. Bozic, John V. Hatfield	Development of an Analogue Microprocessor.	VLSI Design	1997	DBLP DOI BibTeX RDF	Analogue array, Analogue microprocessor, Analogue signal processing, Programmable Logarithmic, Instruction set
3	Sam S. Appleton, Shannon V. Morton, Michael J. Liebelt	Two-Phase Asynchronous Pipeline Control.	ASYNC	1997	DBLP DOI BibTeX RDF	two-phase asynchronous pipeline control, bounded-delay model, prototype microprocessor, microprocessor chips
3	Po-Ching Hsu, Sying-Jyan Wang	Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	multiple-board system, bus emulator, wiring interconnect, testing, fault detection, diagnosis, microprocessor, printed circuit board, printed circuit testing, hierarchical testing
3	Suresh Rajgopal	Challenges in Low Power Microprocessor Design.	VLSI Design	1996	DBLP DOI BibTeX RDF	power benchmarks, latch power, idle power, active power, clock enabling, max power, thermal power, transient power, low-power, clock gating, microprocessor design, di/dt
3	Christian Piguet, T. Schneider, Jean-Marc Masgonty, Claude Arm, Serge Durand, M. Stegers	Low-Power Embedded Microprocessor Design.	EUROMICRO	1996	DBLP DOI BibTeX RDF	low-power embedded microprocessor design, low-power RISC-like architectures, gated clock techniques, power savings, microprocessor chips, CMOS technology, hierarchical memories, clock cycles
3	James O. Bondi, Ashwini K. Nanda, Simonjit Dutta	Integrating a Misprediction Recovery Cache (MRC) into a Superscalar Pipeline.	MICRO	1996	DBLP BibTeX RDF	branch target buffer technology, deep pipelines, misprediction recovery cache integration, performance loss, residual misprediction penalty, superscalar pipeline, microprocessor chips, microprocessor designs, CISC, multiple instructions
3	Michael Nicolaidis	Efficient UBIST implementation for microprocessor sequencing parts.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	strongly code disjoint checkers, signature analyser, UBIST, microprocessor sequencing part, BIST, LFSR, self-checking circuits, totally self-checking circuits
3	Francis Chin, Francis Wu	A microprocessor-based optical character recognition check reader. (PDF / PS)	ICDAR	1995	DBLP DOI BibTeX RDF	microprocessor-based optical character recognition check reader, Magnetic Ink Character Recognition, check reader, lens system, colour image, hardware limitations, optical character recognition, floating point arithmetics, recognition algorithm, software solution
3	S. M. Yuen, K. P. Lam	A Knowledge-based Approach for Worst-case Timing Analysis of Microprocessor Systems. (PDF / PS)	COMPSAC	1995	DBLP DOI BibTeX RDF	Microprocessor Systems Diagnosis, Time Range Reasoning, Knowledge-based Systems
3	Charles P. Roth, Frank E. Levine, Edward H. Welbon	Performance monitoring on the PowerPC 604 microprocessor. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	PowerPC 604 microprocessor, multichip processors, Groupe Bull, performance evaluation, integrated circuit testing, workstations, performance monitoring, microprocessor chips, PCs, Microsoft, IBM, computer testing, Apple, Motorola
3	Steven Wallace, Nirav Dagli, Nader Bagherzadeh	Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	centralized instruction window, four instructions per cycle, compact layout, full-custom design, computer architecture, microprocessor chips, superscalar architecture, superscalar microprocessor, out-of-order issue, 100 MHz
3	H. Hao, K. Bhabuthmal	Clock controller design in SuperSPARC II microprocessor. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	SuperSPARC II, internal clock pulses, internal clock, free running mode, IEEE 1149.1 interface, microprocessor, clocks, microprocessor chips, clock controller
3	Alexander Dalal, Lavi Lev, Sundari Mitra	Design of an efficient power distribution network for the UltraSPARC-I microprocessor. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	computer power supplies, UltraSPARC-I, simulation method, exact layout locations, excessive voltage drop, floorplanning constraints, power interconnections, reduced time-to-market, circuit analysis computing, circuit layout CAD, microprocessor chips, electromigration, CAD tools, power distribution network
3	Thomas Lynch, Ashraf Ahmed, Michael J. Schulte, Thomas K. Callaway, Robert Tisdale	The K5 transcendental functions.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	K5 transcendental functions, AMD x86 compatible superscalar microprocessor, multi-level development cycle, design schedule, table-driven reductions, multiprecision arithmetic operations, encoding, polynomials, floating point arithmetic, microprocessor chips, approximation theory, polynomial approximations
3	Louis Monier, Ramsey W. Haddad, Jeremy Dion	Recursive layout generation.	ARVLSI	1995	DBLP DOI BibTeX RDF	BiCMOS digital integrated circuits, recursive layout generation, layout directives, netlist description, hand-drawn layout, synthesized layout, overall layout, dense VLSI, VLSI, logic CAD, circuit layout CAD, microprocessor chips, microprocessor chips, VLSI chips, seamless integration
3	Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell	Automated verification of temporal properties specified as state machines in VHDL.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	automated verification methodology, correctness specifications, Viper microprocessor, Mealy FSM, compatible states, formal specification, formal verification, high level synthesis, finite state machines, VHDL, sequential circuits, state machines, hardware description languages, microprocessor chips, synchronous sequential circuit, temporal properties, liveness properties
3	Michael S. Allen, W. Kurt Lewchuk, J. D. Coddington	A high performance bus and cache controller for PowerPC multiprocessing systems. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	high performance bus, cache controller, PowerPC 620 microprocessor, system bus interface, ECC protected, server-class systems, physical address bus, data bus, address transfer rates, address snoop response, direct cache-to-cache data transfers, 2 GByte/s, 133 MHz, 128 MB, performance evaluation, pipelining, multiprocessing systems, multiprocessing systems, pipeline processing, cache storage, microprocessor chips, coprocessors, cache coherency protocol, data transfer, PowerPC, system buses, co-processor
3	O. A. Petlin, Stephen B. Furber	Scan testing of micropipelines.	VTS	1995	DBLP DOI BibTeX RDF	asynchronous VLSI circuit design, AMULET1 microprocessor, scan test technique, data processing blocks, combinational processing logic, state holding elements, test generation techniques, VLSI, logic testing, delays, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault location, integrated circuit design, microprocessor chips, delay faults, boundary scan testing, computer testing, test patterns, single stuck-at faults, micropipelines
3	Veljko M. Milutinovic, David A. Fura, Walter A. Helbig	Pipeline Design Tradeoffs in a 32-bit Gallium Arsenide Microprocessor.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	instruction pipeline design, single-chip GaAs microprocessor, application-related parameters, pipelined memory pipeline, III-V semiconductors, performance evaluation, microprocessor chips, instruction sets, 32 bit, GaAs, gallium arsenide
3	Veljko M. Milutinovic, Mark Bettinger, Walter A. Helbig	Multiplier/Shifter Design Tradeoffs in a 32-bit Microprocessor.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	full barrel shifter, large register file, GaAs microprocessor, logic design, microprocessors, microprocessor chips, design tradeoffs, 32 bits, single chip, bit-serial multiplier
3	Robert P. Roesser	Two-Dimensional Microprocessor Pipelines for Image Processing.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	two-dimensional pipeline, Digital image processor, microprocessor array, microprocessor pipeline, space-domain processing, state-space processing, parallel processors, microcomputers
2	Michail Maniatakos, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris	Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	instruction-level error, microprocessor controller, Fault simulation, concurrent error detection
2	Naghmeh Karimi, Michail Maniatakos, Abhijit Jas, Chandra Tirumurti, Yiorgos Makris	Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	scheduler, microprocessor, invariance, Concurrent error detection
2	Klaus-Dietrich Kramer, Thomas Stolze, Alexander Oppelt	Microprocessor Benchmarks - A Detailed Look at Techniques, Problems and Solutions.	ICSEng	2011	DBLP DOI BibTeX RDF	Performance Assessment and Rating, Runtime Measurement, Benchmarks, Microprocessor, Microcontroller
2	Robert de B. Johnston, Ouiza Dahmoune	Overview of Applying Reachability Analysis to Verifying a Physical Microprocessor.	MTV	2011	DBLP DOI BibTeX RDF
2	Lingkan Gong, Jingfen Lu	Verification-Purpose Operating System for Microprocessor System-Level Functions.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	microprocessor verification, system-level function, Verification-Purpose Operating System, VPOS, FPGA, design and test
2	Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De	Resilient microprocessor design for high performance & energy efficiency.	ISLPED	2010	DBLP DOI BibTeX RDF	resilient design
2	Pinkesh J. Shah, Yoni Aizik, Muhammad K. Mhameed, Gila Kamhi	Challenges and methodologies for efficient power budgeting across the die.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	simulation, performance, energy-efficient, management, power, microprocessor, budget
2	Greg James, Barry Silverman, Brian Silverman	Visualizing a classic CPU in action: the 6502.	SIGGRAPH Talks	2010	DBLP DOI BibTeX RDF	MOS 6502, simulation, visualization, microprocessor, integrated circuit, computer history
2	Iman Faraji, Moslem Didehban, Hamid R. Zarandi	Analysis of Transient Faults on a MIPS-Based Dual-Core Processor.	ARES	2010	DBLP DOI BibTeX RDF	Dual-core microprocessor, Microprocessor without Interlocked Pipeline Stages (MIPS), simulation-based fault injection, vulnerability analysis, fault propagation
2	Teresa L. McLaurin, Stylianos Diamantidis, Irakis Diamantidis	The ARM Cortex-A8 Microprocessor IEEE Std 1500 Wrapper.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
2	Amol Vasudeva, Arvind Kumar Sharma, Ashish Kumar	Saksham: Customizable x86 Based Multi-Core Microprocessor Simulator.	CICSyN	2009	DBLP DOI BibTeX RDF	Microprocessor Simulator, x86 Architecture Simulator, Register/Instruction Set Simulator, Object oriented, Assembler
2	Gang Jin, Lei Wang 0011, Zhiying Wang	The Design of Asynchronous Microprocessor Based on Optimized NCL_X Design-Flow.	NAS	2009	DBLP DOI BibTeX RDF
2	Frederik Vandeputte, Lieven Eeckhout	Finding Stress Patterns in Microprocessor Workloads.	HiPEAC	2009	DBLP DOI BibTeX RDF
2	Carl J. Anderson	Beyond innovation: dealing with the risks and complexity of processor design in 22nm.	DAC	2009	DBLP DOI BibTeX RDF	microprocessor design, VLSI technology
2	Jonathan Owen, Maurice Steinman	Northbridge Architecture of AMD's Griffin Microprocessor Family.	IEEE Micro	2008	DBLP DOI BibTeX RDF	data communications devices, low-power design, power management, processors, I/O and data communications, Hot Chips 19
2	Kevin Reick, Pia N. Sanda, Scott B. Swaney, Jeffrey W. Kellington, Michael J. Mack, Michael S. Floyd, Daniel Henderson	Fault-Tolerant Design of the IBM Power6 Microprocessor.	IEEE Micro	2008	DBLP DOI BibTeX RDF	fault tolerance, reliability, fault isolation, RAS, instruction retry, Hot Chips 19
2	Davy Genbrugge, Lieven Eeckhout	Memory Data Flow Modeling in Statistical Simulation for the Efficient Exploration of Microprocessor Design Spaces.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Simulation, Modeling techniques, Performance Analysis and Design Aids
2	Fu-Ching Yang, Wen-Kai Huang, Jing-Kun Zhong, Ing-Jer Huang	Automatic Verification of External Interrupt Behaviors for Microprocessor Design.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Deepak Mathaikutty, Sreekumar V. Kodakara, Ajit Dingankar, Sandeep K. Shukla, David J. Lilja	MMV: A Metamodeling Based Microprocessor Validation Environment.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis	Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	coprocessor data-path, template units, kernels, performance improvements, design flow, energy reductions, architectural synthesis
2	Kip Killpack, Suriyaprakash Natarajan, Arun Krishnamachary, Pouria Bastani	Case Study on Speed Failure Causes in a Microprocessor.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF
2	Shijian Zhang, Weiwu Hu	Fetching Primary and Redundant Instructions in Turn for a Fault-Tolerant Embedded Microprocessor.	PRDC	2008	DBLP DOI BibTeX RDF
2	Andreas Ehliar, Per Karlström, Dake Liu	A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA.	FPL	2008	DBLP DOI BibTeX RDF
2	Marek Chrobak, Christoph Dürr, Mathilde Hurand, Julien Robert	Algorithms for Temperature-Aware Task Scheduling in Microprocessor Systems.	AAIM	2008	DBLP DOI BibTeX RDF
2	Da Wang, Rui Li, Yu Hu, Huawei Li, Xiaowei Li	A Case Study on At-Speed Testing for a Gigahertz Microprocessor.	DELTA	2008	DBLP DOI BibTeX RDF	test power consumption, test coverage, at-speed testing, test time, test data volume
2	Venkatesh Arunachalam, Wayne Burleson	Low-power clock distribution in a multilayer core 3d microprocessor.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	3D ic's, 3D processor architectures, clock grids
2	Hisashige Ando, Ryuji Kan, Yoshiharu Tosaka, Keiji Takahisa, Kichiji Hatanaka	Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor.	DSN	2008	DBLP DOI BibTeX RDF
2	Babu Turumella, Mukesh Sharma	Assertion-based verification of a 32 thread SPARCTM CMT microprocessor.	DAC	2008	DBLP DOI BibTeX RDF	simulation, verification, coverage, assertions, multi-threading
2	Chun-Liang Hsu, Sheng-Yuan Yang, Wei-Bin Wu	Implementing Speech-Recognition Microprocessor into Intelligent Control-System of Home-Appliance.	APSCC	2008	DBLP DOI BibTeX RDF
2	Cecilia Metra, Daniele Rossi, Martin Omaña, Abhijit Jas, Rajesh Galivanche	Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic.	European Test Symposium	2008	DBLP DOI BibTeX RDF	microprocessor, error detecting codes, on-line testing, control logic
2	Liang-Bi Chen, Yung-Chih Liu, Chen-Hung Chen, Chung-Fu Kao, Ing-Jer Huang	Parameterized embedded in-circuit emulator and its retargetable debugging software for microprocessor/microcontroller/DSP processor.	ASP-DAC	2008	DBLP DOI BibTeX RDF