Search results for "microprocessor power"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	William Lloyd Bircher, Lizy K. John	Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events.	ISPASS	2007	DBLP DOI BibTeX RDF	power sensing hardware, complete system power estimation, microprocessor performance event, microprocessor performance counter, online measurement, complete system power consumption, microprocessor power, on-chip performance event counter, system power consumption estimation, power model
1	Mandar Padmawar, Sanghamitra Roy, Koushik Chakraborty	Microprocessor Power Supply Noise Aware Floorplanning Using a Circuit-Architectural Framework.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Youngtaek Kim, Lizy Kurian John	Automated di/dt stressmark generation for microprocessor power delivery networks.	ISLPED	2011	DBLP BibTeX RDF
1	Peter van Stralen, Andy D. Pimentel	A High-level Microprocessor Power Modeling Technique Based on Event Signatures.	Signal Processing Systems	2010	DBLP DOI BibTeX RDF
1	Mondira (Mandy) Deb Pant	Microprocessor power delivery challenges in the Nano-Era.	ISLPED	2010	DBLP DOI BibTeX RDF	power delivery, power, microprocessors
1	Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Shih-Lien Lu	Improving cache lifetime reliability at ultra-low voltages.	MICRO	2009	DBLP DOI BibTeX RDF
1	Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit R. Sheikh, Shrirang M. Yardi	CAMP: A technique to estimate per-structure power at run-time using a few simple parameters.	HPCA	2009	DBLP DOI BibTeX RDF
1	Peter van Stralen, Andy D. Pimentel	Signature-based Microprocessor Power Modeling for Rapid System-level Design Space Exploration.	ESTImedia	2007	DBLP DOI BibTeX RDF
1	Meeta Sharma Gupta, Jarod L. Oatley, Russ Joseph, Gu-Yeon Wei, David M. Brooks	Understanding voltage variations in chip multiprocessors using a distributed power-delivery network.	DATE	2007	DBLP DOI BibTeX RDF
1	Rong Ji, Xianjun Zeng, Liang Chen, Junfeng Zhang	The Implementation and Design of a Low-Power Clock Distribution Microarchitecture.	IEEE NAS	2007	DBLP DOI BibTeX RDF
1	Hendrik F. Hamann, Alan J. Weger, James A. Lacey, Zhigang Hu, Pradip Bose, Erwin Cohen, Jamil A. Wakil	Temperature-limited microprocessors: Measurements and design implications.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Rong Ji, Xianjun Zeng, Liang Chen, Junfeng Zhang	The Implementation and Evaluation of a Low-Power Clock Distribution Network Based on EPIC.	NPC	2007	DBLP DOI BibTeX RDF
1	Nagm Mohamed, Nazeih Botros, Wei Zhang	The Impact of Cache Organization in Optimizing Microprocessor Power Consumption.	CDES	2006	DBLP BibTeX RDF
1	Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque	Evaluation of the field-programmable cache: performance and energy consumption.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	adaptive processors, reconfigurable cache memory, static and dynamic energy consumption, performance evaluation, run-time adaptation
1	Shiwen Hu, Madhavi Gopal Valluri, Lizy Kurian John	Effective management of multiple configurable units using dynamic optimization.	TACO	2006	DBLP DOI BibTeX RDF	Adaptive computing environment (ACE), dynamic optimization, power dissipation, hotspots
1	Tanay Karnik, Peter Hazucha, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner	High-frequency DC-DC conversion : fact or fiction.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva Narendra, Tanay Karnik, Vivek De	Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation.	ISLPED	2004	DBLP DOI BibTeX RDF	integrated magnetics, on-die switching converter, power delivery, DC-DC converter, 3-D integration
1	Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy	Deterministic Clock Gating for Microprocessor Power Reduction.	HPCA	2003	DBLP DOI BibTeX RDF
1	Karthik Natarajan, Heather Hanson, Stephen W. Keckler, Charles R. Moore, Doug Burger	Microprocessor pipeline energy analysis.	ISLPED	2003	DBLP DOI BibTeX RDF	alpha 21264, over-provisioning, power, energy, speculation
1	Alper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster	Tradeoffs in power-efficient issue queue design.	ISLPED	2002	DBLP DOI BibTeX RDF	non-compacting, adaptation, low-power, microarchitecture, compacting, banking, issue queue
1	Toshinori Sato, Itsujiro Arita	Reducing Energy Consumption via Low-Cost Value Prediction.	PATMOS	2002	DBLP DOI BibTeX RDF
1	Cheng-Ta Hsieh, L. Chen, Massoud Pedram	Microprocessor power analysis by labeled simulation.	DATE	2001	DBLP DOI BibTeX RDF
1	David Brooks, Vivek Tiwari, Margaret Martonosi	Wattch: a framework for architectural-level power analysis and optimizations.	ISCA	2000	DBLP DOI BibTeX RDF
1	David H. Albonesi	Selective Cache Ways: On-Demand Cache Resource Allocation. (PDF / PS)	MICRO	1999	DBLP DOI BibTeX RDF
1	Cheng-Ta Hsieh, Massoud Pedram	Microprocessor power estimation using profile-driven program synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
1	Brad W. Suessmith, George Paap III	PowerPC 603 Microprocessor Power Management.	Commun. ACM	1994	DBLP DOI BibTeX RDF