Search results for "microprocessors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Yedidya Hilewitz, Ruby B. Lee	Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	Bit scatter, Bit gather, Parallel deposit, Unpack, Algorithm acceleration, Bioinformatics, Compression, Pattern matching, Steganography, Microprocessors, Permutations, Pack, Instruction set architecture, Cryptology, ISA, Parallel extract, Bit manipulations
3	Uwe Brinkschulte, Mathias Pacher	A Control Theory Approach to Improve the Real-Time Capability of Multi-Threaded Microprocessors.	ISORC	2008	DBLP DOI BibTeX RDF	Control theory in high-end microprocessors, real-time microprocessors, IPC rate
3	Yiu-Hing Chan, Prabhakar Kudva, Lisa B. Lacey, Gregory A. Northrop, Thomas E. Rosser	Physical synthesis methodology for high performance microprocessors.	DAC	2003	DBLP DOI BibTeX RDF	synthesis, microprocessors, high-performance
3	Anthony C. J. Fox, Neal A. Harman	Algebraic Models of Correctness for Microprocessors.	Formal Asp. Comput.	2000	DBLP DOI BibTeX RDF	Formal Verification, Microprocessors, Algebraic Models
3	Seongbae Park, SangMin Shim, Soo-Mook Moon	Evaluation of Scheduling Techniques on a SPARC-based VLIW Testbed.	MICRO	1997	DBLP BibTeX RDF	SPARC-based VLIW testbed, VLIW microprocessors, Very Long Instruction Word microprocessors, all-path speculation, gcc-generated optimized SPARC code, high-performance VLIW code, nongreedy enhanced pipeline scheduling, nonspeculative operations, profile-based all-path speculation, restricted speculative loads, scheduling compiler, speculative operations, trace-based speculation, performance, compiler, computer architecture, parallel machines, software pipelining, loop unrolling, renaming, memory disambiguation, copies, scheduling techniques
3	John Bunda, Donald S. Fussell, William C. Athas	Energy-efficient instruction set architecture for CMOS microprocessors.	HICSS	1995	DBLP DOI BibTeX RDF	energy-efficient instruction set architecture, CMOS microprocessors, portable battery-based applications, performance-driven designs, processor architecture tradeoffs, program encoding size, instruction set richness, energy cost, speculative instruction fetching, execution resources, instruction-level parallel machines, multiple-path instruction fetching, high execution bandwidth, power management, microprocessor chips, instruction sets, power dissipation, CMOS digital integrated circuits, reduced instruction set computing, cooling, design constraint, instruction delivery, code density
2	Adam Waksman, Simha Sethumadhavan	Tamper Evident Microprocessors.	IEEE Symposium on Security and Privacy	2010	DBLP DOI BibTeX RDF	microprocessors, hardware security, backdoors
2	Daniele Rossi, Martin Omaña, Gianluca Berghella, Cecilia Metra, Abhijit Jas, Chandra Tirumurti, Rajesh Galivanche	Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	microprocessor, on-line testing, control logic
2	Skyler Schneider, Daniel Y. Deng, Daniel Lo, Greg Malysa, G. Edward Suh	Implementing dynamic information flow tracking on microprocessors with integrated FPGA fabric (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	dynamic inspection, reconfigurable microprocessors, fpga
2	Mondira (Mandy) Deb Pant	Microprocessor power delivery challenges in the Nano-Era.	ISLPED	2010	DBLP DOI BibTeX RDF	power delivery, power, microprocessors
2	George Xenoulis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units.	IEEE Trans. Dependable Sec. Comput.	2009	DBLP DOI BibTeX RDF
2	Antonio González	Key Microarchitectural Innovations for Future Microprocessors.	ARCS	2009	DBLP DOI BibTeX RDF
2	Rupesh S. Shelar	An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors.	ISPD	2009	DBLP DOI BibTeX RDF	routing, power, clock distribution
2	Nikolaos Kavvadias, Spiridon Nikolaidis	Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Optimization, Microprocessors, Hardware description languages, Real-time and embedded systems, Pipeline processors, Control design
2	Ilya Wagner, Valeria Bertacco, Todd M. Austin	Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev, Stamatis Vassiliadis	Test Set Development for Cache Memory in Modern Microprocessors.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Lin Zhang, Aaron Carpenter, Berkehan Ciftcioglu, Alok Garg, Michael C. Huang, Hui Wu	Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Giovanni Squillero	Ea-based test and verification of microprocessors.	GECCO (Companion)	2008	DBLP DOI BibTeX RDF	post-sysnthesis verification, pre-sysnthesis verification, test, evolutionary algorithm, microprocessors
2	Michael Katelman, José Meseguer, Santiago Escobar	Directed-Logical Testing for Functional Verification of Microprocessors.	MEMOCODE	2008	DBLP DOI BibTeX RDF
2	Paolo Bernardi, Kyriakos Christou, Michelangelo Grosso, Maria K. Michael, Ernesto Sánchez, Matteo Sonza Reorda	Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors.	EvoWorkshops	2008	DBLP DOI BibTeX RDF	microprocessor, BDD, MOEA, path-delay testing
2	David S. Hardin	Invited Tutorial: Considerations in the Design and Verification of Microprocessors for Safety-Critical and Security-Critical Applications.	FMCAD	2008	DBLP DOI BibTeX RDF
2	Kyriakos Christou, Maria K. Michael, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda	A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions.	VTS	2008	DBLP DOI BibTeX RDF	SBST, path-delay faults, microprocessor test
2	Florent de Dinechin, Jérémie Detrey, Octavian Cret, Radu Tudoran	When FPGAs are better at floating-point than microprocessors.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, floating-point, arithmetic
2	DiaaEldin Khalil, Yehea I. Ismail	A global interconnect link design for many-core microprocessors.	IFMT	2008	DBLP DOI BibTeX RDF	interconnect, link, bus, repeater insertion
2	Cecilia Metra, Martin Omaña, T. M. Mak, Asifur Rahman, Simon Tam	Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors.	DFT	2008	DBLP DOI BibTeX RDF
2	Rui Gong, Kui Dai, Zhiying Wang	A Framework to Evaluate the Trade-off among AVF Performance and Area of Soft Error Tolerant Microprocessors.	DFT	2008	DBLP DOI BibTeX RDF
2	Kamran Zarrineh	Design for Test Challenges of High Performance/Low Power Microprocessors.	DFT	2008	DBLP DOI BibTeX RDF
2	Chandramouli V. Kashyap, Pouria Bastani, Kip Killpack, Chirayu S. Amin	Silicon feedback to improve frequency of high-performance microprocessors: an overview.	ICCAD	2008	DBLP DOI BibTeX RDF	speedpath, learning, timing analysis
2	Deniz Balkan, Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose	Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	General, Microprocessors, Pipeline processors, Performance attributes
2	David Brooks, Robert P. Dick, Russ Joseph, Li Shang	Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors.	IEEE Micro	2007	DBLP DOI BibTeX RDF	process variation, power models, reliability models, modeling of computer architecture, thermal analysis
2	Youngjin Cho, Naehyuck Chang	Energy-Aware Clock-Frequency Assignment in Microprocessors and Memory Devices for Dynamic Voltage Scaling.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Dimitris Gizopoulos, Robert C. Aitken, S. Kundu	Guest Editorial: Special Section on "Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems".	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Loganathan Lingappan, Niraj K. Jha	Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Todd J. Foster, Dennis L. Lastor, Padmaraj Singh	First Silicon Functional Validation and Debug of Multicore Microprocessors.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Ziyad Hanna	Abstract Modeling and Formal Verification of Microprocessors.	CSR	2007	DBLP DOI BibTeX RDF
2	Leslie Barnes	Performance Modeling and Analysis for AMD's High Performance Microprocessors.	ISPASS	2007	DBLP DOI BibTeX RDF
2	Jason D. Lee, Praveen Bhojwani, Rabi N. Mahapatra	A Safety Analysis Framework for COTS Microprocessors in Safety-Critical Applications.	HASE	2007	DBLP DOI BibTeX RDF
2	Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari	Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors.	ISPD	2007	DBLP DOI BibTeX RDF	multi-VTH, optimization, timing, low-power design, microprocessor, EDA, leakage power, sizing
2	Srinivas Vadlamani, Stephen Jenks	Architectural Considerations for Efficient Software Execution on Parallel Microprocessors.	IPDPS	2007	DBLP DOI BibTeX RDF
2	Wen-mei W. Hwu, Shane Ryoo, Sain-Zee Ueng, John H. Kelm, Isaac Gelado, Sam S. Stone, Robert E. Kidd, Sara S. Baghsorkhi, Aqeel Mahesri, Stephanie C. Tsao, Nacho Navarro, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel	Implicitly Parallel Programming Models for Thousand-Core Microprocessors.	DAC	2007	DBLP DOI BibTeX RDF
2	Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam	Novel Approach to Clock Fault Testing for High Performance Microprocessors.	VTS	2007	DBLP DOI BibTeX RDF
2	Nitin Yogi, Vishwani D. Agrawal	Spectral RTL Test Generation for Microprocessors.	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Hendrik F. Hamann, Alan J. Weger, James A. Lacey, Zhigang Hu, Pradip Bose, Erwin Cohen, Jamil A. Wakil	Temperature-limited microprocessors: Measurements and design implications.	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Dietmar Fey, Marcus Komann, Frank Schurz, Andreas Loos	An Organic Computing architecture for visual microprocessors based on Marching Pixels.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel	Examining ACE analysis reliability estimates using fault-injection.	ISCA	2007	DBLP DOI BibTeX RDF	fault tolerance, microprocessors, soft errors, measurement techniques
2	Neal A. Harman	Algebraic Models of Simultaneous Multithreaded and Multi-core Processors.	CALCO	2007	DBLP DOI BibTeX RDF	many-sorted algebra, verification, microprocessors, correctness, threaded
2	Yehuda Sadeh Weinraub, Shlomo Weiss	Power-aware out-of-order issue logic in high-performance microprocessors.	Microprocessors and Microsystems	2006	DBLP DOI BibTeX RDF
2	Nicholas J. Wang, Sanjay J. Patel	ReStore: Symptom-Based Soft Error Detection in Microprocessors.	IEEE Trans. Dependable Sec. Comput.	2006	DBLP DOI BibTeX RDF	Simulation, fault tolerance, fault injection, redundant design
2	Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso	Data-Driven Multithreading Using Conventional Microprocessors.	IEEE Trans. Parallel Distrib. Syst.	2006	DBLP DOI BibTeX RDF	nonblocking threads, multiprocessors, high performance computing, multithreading, network of workstations, Dataflow, cache prefetching
2	Weiwu Hu, Rui Hou, Jun-Hua Xiao, Long-Bin Zhang	High Performance General-Purpose Microprocessors: Past and Future.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	high performance general-purpose microprocessor, Godson processor, chip multiprocessors, instruction level parallelism, thread level parallelism, data level parallelism
2	Shuai Wang, Jie S. Hu, Sotirios G. Ziavras	On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors.	ICSAMOS	2006	DBLP DOI BibTeX RDF
2	Miroslav N. Velev	Formal Verification of Pipelined Microprocessors with Delayed Branches.	ISQED	2006	DBLP DOI BibTeX RDF
2	Oguz Ergin	Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors.	PATMOS	2006	DBLP DOI BibTeX RDF
2	Jianfeng An, Xiaoya Fan, Shengbing Zhang, Danghui Wang, Yi Wang	VMSIM: Virtual Machine Based a Full System Simulation Platform for Microprocessors' Functional Verification.	ITNG	2006	DBLP DOI BibTeX RDF
2	Pong-Fei Lu, Nianzheng Cao, Leon J. Sigal, Pieter Woltgens, Raphael Robertazzi, David F. Heidel	A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors.	ISLPED	2006	DBLP DOI BibTeX RDF	pulse latch, low-power, latch
2	André V. Fidalgo, Manuel G. Gericota, Gustavo R. Alves, José M. Ferreira	Using NEXUS compliant debuggers for real time fault injection on microprocessors.	SBCCI	2006	DBLP DOI BibTeX RDF	on chip debug, real time systems, fault injection
2	Vladimir Stojanovic, R. Iris Bahar, Jennifer Dworak, Richard Weiss	A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors.	DAC	2006	DBLP DOI BibTeX RDF	instruction queue, reliability, error correcting codes
2	Wei Wu, Lingling Jin, Jun Yang 0002, Pu Liu, Sheldon X.-D. Tan	A systematic method for functional unit power estimation in microprocessors.	DAC	2006	DBLP DOI BibTeX RDF	microprocessor, power estimation, performance counter
2	Jason A. Blome, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke	Cost-efficient soft error protection for embedded microprocessors.	CASES	2006	DBLP DOI BibTeX RDF	reliability, embedded processors, soft errors
2	Zoran A. Salcic, Flavius Gruian, Partha S. Roop, Alif Wahid	A Scheduler Support Unit for Reactive Microprocessors.	RTCSA	2006	DBLP DOI BibTeX RDF
2	Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos	Fast bit permutation unit for media enhanced microprocessors.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Hassan Al-Sukhni, David Lindberg, James Holt, Michele Reese	Workload Slicing for Characterizing New Features in High Performance Microprocessors.	MTV	2006	DBLP DOI BibTeX RDF
2	Jörg Platte, Raúl Durán Díaz, Edwin Naroska	A New Encryption and Hashing Scheme for the Security Architecture for Microprocessors.	Communications and Multimedia Security	2006	DBLP DOI BibTeX RDF
2	Sumeet Kumar, Aneesh Aggarwal	Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors.	HPCA	2006	DBLP DOI BibTeX RDF
2	Nathan T. Slingerland, Alan Jay Smith	Multimedia extensions for general purpose microprocessors: a survey.	Microprocessors and Microsystems	2005	DBLP DOI BibTeX RDF
2	Bramha Allu, Wei Zhang 0002	Exploiting the replication cache to improve performance for multiple-issue microprocessors.	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF
2	Giacinto Paolo Saggese, Nicholas J. Wang, Zbigniew Kalbarczyk, Sanjay J. Patel, Ravishankar K. Iyer	An Experimental Study of Soft Errors in Microprocessors.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Soft error sensitivity, Assessment and Protection Techniques, Fault Injection, Soft errors, Microprocessor Architecture
2	Yiran Chen, Kaushik Roy, Cheng-Kok Koh	Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
2	Qing K. Zhu, David Ayers	Power Grid Planning for Microprocessors and SOCS.	ISQED	2005	DBLP DOI BibTeX RDF
2	Mikhail N. Dorojevets	Opportunities, Challenges, and Projections for Superconductor RSFQ Microprocessors.	SC	2005	DBLP DOI BibTeX RDF
2	Sreejit Chakravarty	Improving Logic Test Quality of Microprocessors.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
2	Cristian Constantinescu	Neutron SER Characterization of Microprocessors.	DSN	2005	DBLP DOI BibTeX RDF
2	Nicholas J. Wang, Sanjay J. Patel	ReStore: Symptom Based Soft Error Detection in Microprocessors.	DSN	2005	DBLP DOI BibTeX RDF
2	Norman P. Jouppi	The Future Evolution of High-Performance Microprocessors.	MICRO	2005	DBLP DOI BibTeX RDF
2	Hans Eberle, Arvinderpal Wander, Nils Gura, Sheueling Chang Shantz, Vipul Gupta	Architectural Extensions for Elliptic Curve Cryptography over GF(2m) on 8-bit Microprocessors.	ASAP	2005	DBLP DOI BibTeX RDF
2	Yi-Shing Chang, Sreejit Chakravarty, Hiep Hoang, Nick Thorpe, Khen Wee	Transition Tests for High Performance Microprocessors.	VTS	2005	DBLP DOI BibTeX RDF
2	K. Uday Bhaskar, M. Prasanth, G. Chandramouli, V. Kamakoti	A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	Haihua Shen, Lin Ma, Heng Zhang	CRPG: a configurable random test-program generator for microprocessors.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Bin Xue, D. M. H. Walker	Is IDDQ Test of Microprocessors Feasible?	MTV	2005	DBLP DOI BibTeX RDF
2	Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova	Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors.	MTV	2005	DBLP DOI BibTeX RDF
2	Michele Portolan, Régis Leveugle	On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors.	IOLTS	2005	DBLP DOI BibTeX RDF
2	Andre L. R. Pouponnot	Strategic Use of SEE Mitigation Techniques for the Development of the ESA Microprocessors: Past, Present and Future.	IOLTS	2005	DBLP DOI BibTeX RDF
2	Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail	A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors.	ICCD	2005	DBLP DOI BibTeX RDF
2	Kyeong-Jae Lee, Kevin Skadron, Wei Huang	Analytical Model for Sensor Placement on Microprocessors.	ICCD	2005	DBLP DOI BibTeX RDF
2	W. L. Bircher, M. Valluri, J. Law, L. K. John	Runtime identification of microprocessor energy saving opportunities.	ISLPED	2005	DBLP DOI BibTeX RDF	speculative microprocessors, modeling, energy efficiency, power
2	Patricio Bulic, Veselko Gustin	An efficient way to filter out data dependences with a sufficiently large distance between memory references.	SIGPLAN Notices	2005	DBLP DOI BibTeX RDF	SIMD microprocessors, vectorizing compilers, data dependence analysis
2	Fred A. Bower, Sule Ozev, Daniel J. Sorin	Autonomic Microprocessor Execution via Self-Repairing Arrays.	IEEE Trans. Dependable Sec. Comput.	2005	DBLP DOI BibTeX RDF	Logic design reliability and testing, microprocessors and microcomputers
2	Michael Bedford Taylor, Walter Lee, Saman P. Amarasinghe, Anant Agarwal	Scalar Operand Networks.	IEEE Trans. Parallel Distrib. Syst.	2005	DBLP DOI BibTeX RDF	microprocessors, distributed architectures, Interconnection architectures
2	Fulvio Corno, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero	Code Generation for Functional Validation of Pipelined Microprocessors.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	pipelined micro processors, evolutionary algorithms, functional validation, automatic test program generation
2	Norman P. Jouppi	The Future Evolution of High-Performance Microprocessors.	HiPC	2004	DBLP DOI BibTeX RDF
2	Lieven Eeckhout	Efficient architectural design of high performance microprocessors.	ISPASS	2004	DBLP DOI BibTeX RDF
2	Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva Narendra, Tanay Karnik, Vivek De	Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation.	ISLPED	2004	DBLP DOI BibTeX RDF	integrated magnetics, on-die switching converter, power delivery, DC-DC converter, 3-D integration
2	Nobuyuki Ohba, Kohji Takano	An SoC design methodology using FPGAs and embedded microprocessors.	DAC	2004	DBLP DOI BibTeX RDF	mixed-level verification, SoC, ASIC, FPGA prototyping
2	Miroslav N. Velev	Using positive equality to prove liveness for pipelined microprocessors.	ASP-DAC	2004	DBLP DOI BibTeX RDF
2	Miroslav N. Velev	Efficient translation of boolean formulas to CNF in formal verification of microprocessors.	ASP-DAC	2004	DBLP DOI BibTeX RDF
2	Sumeet Kumar, Prateek Pujara, Aneesh Aggarwal	Bit-Sliced Datapath for Energy-Efficient High Performance Microprocessors.	PACS	2004	DBLP DOI BibTeX RDF
2	Sergio López-Buedo, Eduardo I. Boemo	Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report.	FPGA	2004	DBLP DOI BibTeX RDF	JBits, FPGA, embedded processors, run-time reconfiguration, ring-oscillator, temperature measurement
2	Miroslav N. Velev	Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of Microprocessors.	DATE	2004	DBLP DOI BibTeX RDF
2	Christian Tenllado, Carlos García, Manuel Prieto, Luis Piñuel, Francisco Tirado	Exploiting Multilevel Parallelism Within Modern Microprocessors: DWT as a Case Study.	VECPAR	2004	DBLP DOI BibTeX RDF
2	Lorena Anghel, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Raoul Velazco	Coupling Different Methodologies to Validate Obsolete Microprocessors.	DFT	2004	DBLP DOI BibTeX RDF