Search results for "minimisation of switching nets"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Prathima Agrawal, B. Narendran, Narayanan Shivakumar	Multi-way partitioning of VLSI circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	multi-way partitioning, hierarchical design processes, nets cut metric, VLSI, delays, economics, logic CAD, VLSI layout, integrated circuit layout, VLSI circuits, logic partitioning, minimisation of switching nets, average delay, integrated circuit manufacture, cost metric
1	Nripendra N. Biswas, C. Srikanth, James Jacob	Cubical CAMP for minimization of Boolean functions.	VLSI Design	1996	DBLP DOI BibTeX RDF	cubical CAMP algorithm, single Boolean function, QCAMP, UNATE TEST, cyclic function, prime cubes, Achilles heel function, Boolean functions, minimization, minimisation of switching nets, BISECT, unate function
1	Sasan Iman, Massoud Pedram	Two-level logic minimization for low power.	ICCAD	1995	DBLP DOI BibTeX RDF	Power Prime Implicants, low power two-level logic minimization, minimum covering problem, minimum power solution, static CMOS circuits, logic design, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, circuit optimisation, minimisation of switching nets
1	Robert M. Fuhrer, Bill Lin, Steven M. Nowick	Algorithms for the optimal state assignment of asynchronous state machines.	ARVLSI	1995	DBLP DOI BibTeX RDF	optimal state assignment, asynchronous state machines, state codes, race-free state assignment, hazard-free state assignment, input encoding problem, sum-of-products implementations, finite state machines, asynchronous circuits, state assignment, minimisation of switching nets, hazards and race conditions, asynchronous sequential logic
1	Ted Stanion, Carl Sechen	Quasi-algebraic decompositions of switching functions.	ARVLSI	1995	DBLP DOI BibTeX RDF	quasi-algebraic decompositions, algebraic product, binary Boolean operation, canonical manner, SSL testable, logic testing, testability, switching functions, switching functions, state assignment, minimisation of switching nets, benchmark circuits, circuit size
1	Noam Nisan, Avi Wigderson	Lower Bounds for Arithmetic Circuits via Partial Serivatives (Preliminary Version).	FOCS	1995	DBLP DOI BibTeX RDF	restricted classes, computational complexity, lower bounds, digital arithmetic, polynomials, logic circuits, arithmetic circuits, multivariate polynomials, complexity measure, minimisation of switching nets, partial derivatives
1	Tomasz Kozlowski, Erik L. Dagless, Jonathan Saul	An enhanced algorithm for the minimization of exclusive-OR sum-of-products for incompletely specified functions. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	minimization algorithm, exclusive-OR sum-of-products, rule-based heuristics, initial circuit description, MINT, multiple-product-term transformations, multiple-valued input two-valued multiple-output functions, knowledge based systems, logic design, heuristic programming, minimisation of switching nets, incompletely specified functions
1	Aiguo Lu, Erik L. Dagless, Jonathan M. Saul	DART: delay and routability driven technology mapping for LUT based FPGAs. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	DART, delay driven technology mapping, LUT based FPGAs, two-phased approach, routability directed delay-optimal mapping, stochastic routability analysis, delay-optimal mapping, field programmable gate arrays, delays, logic design, programmable logic arrays, table lookup, minimisation of switching nets
1	Luis F. G. Sarmenta, Gill A. Pratt, Stephen A. Ward	Rational clocking [digital systems design]. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	rational clocking, independently-clocked digital subsystems, finite probability, phase relationship, delays, delays, logic design, logic design, synchronisation, clocks, minimisation of switching nets, digital systems design, synchronization failure
1	Shashidhar Thakur, D. F. Wong	Simultaneous area and delay minimum K-LUT mapping for K-exact networks. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	area/delay minimum K-LUT mapping, K-exact networks, technology mapping problem, lookup table FPGAs, area minimization problem, K-bounded networks, delay minimization problem, flow-map algorithm, field programmable gate arrays, computational complexity, complexity, NP-complete, logic design, polynomial time algorithm, programmable logic arrays, table lookup, minimisation of switching nets
1	Hirendu Vaishnav, Massoud Pedram	Logic extraction based on normalized netlengths. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	logic extraction, normalized netlengths, chip area, routing, logic design, logic synthesis, cost function, minimisation of switching nets
1	Chuan-Yu Wang, Kaushik Roy	Control unit synthesis targeting low-power processors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	control unit synthesis, low-power processors, low-power decoding scheme, microprogrammed architecture, nanoprogrammed architecture, 8086 instruction set, instruction opcodes, computer architecture, logic design, encoding, decoding, microprocessor chips, graph embedding, instruction sets, microprogramming, CMOS circuits, logic minimization, system reliability, switching activity, minimisation of switching nets, pseudo-Boolean programming
1	Takahiro Hozumi, Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	Multiple-Valued Logic Design Using Multiple-Valued EXOR. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	multiple-valued EXOR, sum operation, multiple valued sum of products expression, binary EXOR of MINs expressions, three valued EXOR of MINs expression, three valued two variable functions, multiple valued EXOR of MINs expressions, MAX of MINs, TSUM of MINs expressions, logic design, neural nets, multivalued logic, logic minimization, minimisation of switching nets, neural computing, multiple valued logic design, multiple-valued logic design
1	Jacob Augustine, Wen Feng, James Jacob	Logic minimization based approach for compressing image data.	VLSI Design	1995	DBLP DOI BibTeX RDF	binary image compression, Boolean switching function, cubical form, ESPRESSO, cube-based two-level logic minimizer, prefix property, image data compression, decompression time, logic coding, data compression, Boolean functions, image coding, lossless compression, logic minimization, minimisation of switching nets, compression ratio
1	Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli	A new switching-level approach to multiple-output functions synthesis.	VLSI Design	1995	DBLP DOI BibTeX RDF	switching-level, multiple-output functions synthesis, transistor level, randomly generated functions, logic CAD, timing constraints, circuit layout CAD, CMOS logic circuits, multivalued logic circuits, integrated circuit layout, minimisation of switching nets, area minimization, figures of merit
1	Chunduri Rama Mohan, Partha Pratim Chakrabarti	Combined optimization of area and testability during state assignment of PLA-based FSM's.	VLSI Design	1995	DBLP DOI BibTeX RDF	combined optimization, testability optimisation, PLA-based FSM, EARTH algorithm, single cross-point faults, redundancy checker, fault diagnosis, logic testing, redundancy, finite state machines, integrated circuit testing, design for testability, fault model, logic CAD, programmable logic arrays, circuit layout CAD, circuit optimisation, integrated circuit layout, state assignment, state assignment, minimisation of switching nets, single stuck-at faults, area minimization
1	Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng	Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.	VLSI Design	1995	DBLP DOI BibTeX RDF	stuck-at fault testability, robust path delay fault testability, multilevel logic, hazard-free logic, synthesis for testability method, multi-level circuit, minimization algorithms, logic testing, delays, redundancy, design for testability, logic design, combinational circuits, asynchronous circuits, asynchronous circuits, multivalued logic circuits, minimisation of switching nets, area overhead, hazards and race conditions
1	Hsing-Lung Chen, Nian-Feng Tzeng	Efficient Resource Placement in Hypercubes Using Multiple-Adjacency Codes.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	multiple-adjacency codes, access contention, parallel algorithms, resource allocation, hypercubes, encoding, hypercube networks, system performance, performance degradation, binary sequences, minimisation of switching nets, Hamming codes, resource placement, linear block codes
1	Hussein M. Alnuweiri	Optimal VLSI Networks for Multidimensional Transforms.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	optimal VLSI networks, multidimensional transforms, AT/sup 2/-optimal networks, mapping large K-shuffle networks, index-rotation operations, regular layouts, VLSI, fast Fourier transforms, discrete Fourier transform, circuit analysis computing, minimisation of switching nets
1	H. Braun, F. C. Stephan	On Optimizing Diameter and Average Distance of Directed Interconnected Networks.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	Maekawa problem, directed interconnected networks, logarithmic time complexity, computational complexity, multiprocessor interconnection networks, directed graphs, routing algorithms, diameter, buffer size, minimisation of switching nets, average distance
1	Dilip D. Kandlur, Kang G. Shin	Traffic Routing for Multicomputer Networks with Virtual Cut-Through Capability.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	virtual cut-through capability, route selection problem, link cost function, C-wrapped hexagonal mesh, performance, computational complexity, hypercube, computer networks, NP-hard, hypercube networks, telecommunication network routing, interprocess communication, minimisation of switching nets, multicomputer networks, minimization problem, traffic routing, network load
1	Suman Purwar	An Efficient Method of Computing Generalized Reed-Muller Expansions from Binary Decision Diagram.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	generalized Reed-Muller expansions, minterm values, Boolean function, Boolean functions, variables, binary decision diagram, minimisation of switching nets
1	Edward A. Bender, Jon T. Butler	On the Size of PLA's Required to Realize Binary and Multiple-Valued Functions.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	product terms, nonzero output values, PLA size, realizable functions, lower bounds, logic design, upper bounds, variance, switching functions, logic arrays, minimisation of switching nets, multiple-valued functions
1	Ghislaine Thuau, Gabriele Saucier	Optimized Layout of MOS Cells.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	optimised MOS cell layout, optimized topological arrangements, minimized Boolean function, well-structured network, transistor merging procedure, nonseries-parallel network, logic design, circuit layout CAD, minimisation of switching nets, logical optimization, field effect integrated circuits