Search results for "multi-core architecture"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Quan Chen, Zhiyi Huang, Minyi Guo, Jingyu Zhou	CAB: Cache Aware Bi-tier Task-Stealing in Multi-socket Multi-core Architecture.	ICPP	2011	DBLP DOI BibTeX RDF	Multi-socket Multi-core architecture, Cache aware, Task-stealing, Cilk
2	Jih-Ching Chiu, Yu-Liang Chou, Ding-Siang Su	A hyperscalar multi-core architecture.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	cmps, dynamic multi-core chips, reconfigurable multi-core architectures, chip multiprocessors
2	Lu Yang, Zhanqi Cui, Xuandong Li	A Case Study for Fault Tolerance Oriented Programming in Multi-core Architecture.	HPCC	2009	DBLP DOI BibTeX RDF
2	Qingbo Wang, Viktor K. Prasanna	Multi-Core Architecture on FPGA for Large Dictionary String Matching.	FCCM	2009	DBLP DOI BibTeX RDF	FPGA, String Matching, Multi-core Architecture
2	Martha Cárdenas, Juan Tapia, Roberto Sepúlveda, Oscar Montiel, Patricia Melin	Scalability Potential of Multi-core Architecture in a Neuro-Fuzzy System.	Soft Computing for Hybrid Intelligent Systems	2008	DBLP DOI BibTeX RDF
2	Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Ruben Gonzalez, Daniel A. Jiménez, Mateo Valero	A Flexible Heterogeneous Multi-Core Architecture.	PACT	2007	DBLP DOI BibTeX RDF
2	Lei Chai, Qi Gao, Dhabaleswar K. Panda	Understanding the Impact of Multi-Core Architecture in Cluster Computing: A Case Study with Intel Dual-Core System.	CCGRID	2007	DBLP DOI BibTeX RDF
2	Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao	Optimizing the Fast Fourier Transform on a Multi-core Architecture.	IPDPS	2007	DBLP DOI BibTeX RDF
2	Guangming Tan, Ninghui Sun, Guang R. Gao	A parallel dynamic programming algorithm on a multi-core architecture.	SPAA	2007	DBLP DOI BibTeX RDF	scalabilitiy, dynamic programming, multi-core, memory hierarchy, data dependence
2	Sören Moch, Mladen Berekovic, Hans-Joachim Stolberg, Lars Friebe, Mark Bernd Kulaczewski, Andreas Dehnhardt, Peter Pirsch	HIBRID-SOC: a multi-core architecture for image and video applications.	SIGARCH Computer Architecture News	2004	DBLP DOI BibTeX RDF
1	Mihai Pricopi, Tulika Mitra	Bahurupi: A polymorphic heterogeneous multi-core architecture.	TACO	2012	DBLP DOI BibTeX RDF
1	Jacob Murray, John Klingner, Partha P. Pande, Behrooz Shirazi	Sustainable multi-core architecture with on-chip wireless links.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Ahmed Yasir Dogan, Jeremy Constantin, Martino Ruggiero, Andreas Burg, David Atienza	Multi-core architecture design for ultra-low-power wearable health monitoring systems.	DATE	2012	DBLP BibTeX RDF
1	Pascal Vivet, Edith Beigné, Hugo Lebreton, Nacer-Eddine Zergainoh	On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Yuxin Wang, He Guo, Liye Yuan	A routing algorithm for multicast on hypercube multi-core architecture.	J. Embedded Computing	2011	DBLP DOI BibTeX RDF
1	Tomoyuki Nagatsuka, Yoshito Sakaguchi, Takayuki Matsumura, Kenji Kise	CoreSymphony: an efficient reconfigurable multi-core architecture.	SIGARCH Computer Architecture News	2011	DBLP DOI BibTeX RDF
1	Guang-Ming Tan, Ping Liu, Dong-Bo Bu, Yanbing Liu	Revisiting Multiple Pattern Matching Algorithms for Multi-Core Architecture.	J. Comput. Sci. Technol.	2011	DBLP DOI BibTeX RDF
1	Amit Kale, Parag Mittal, Shekhar Manek, Neha Gundecha, Madhuri Londhe	Distributing Subsystems Across Different Kernels Running Simultaneously in a Multi-Core Architecture.	CSE	2011	DBLP DOI BibTeX RDF
1	Yong-Min Kim, Myeongsu Kang, Jong-Myon Kim	High-Performance Video Based Fire Detection Algorithms Using a Multi-core Architecture.	ICIC	2011	DBLP DOI BibTeX RDF
1	M. Rajasekhara Babu, P. Venkata Krishna, M. Khalid	Optimization Techniques and Performance Evaluation of a Multithreaded Multi-core Architecture Using OpenMP.	ACC	2011	DBLP DOI BibTeX RDF
1	Michael K. Chan, Lan Yang	Comparative analysis of OpenMP and MPI on multi-core architecture.	SpringSim (ANSS)	2011	DBLP BibTeX RDF
1	Wen-Yen Tsai, Nen-Fu Huang, Hsien-Wei Hung	A Lock-Controlled Session Table Partitioning Scheme with Dynamic Resource Balancing for Multi-Core Architecture.	ICC	2011	DBLP DOI BibTeX RDF
1	Yan Cui, Yingxin Wang, Yu Chen, Yuanchun Shi	Experience on Comparison of Operating Systems Scalability on the Multi-core Architecture.	CLUSTER	2011	DBLP DOI BibTeX RDF	performance, scalability, benchmarks, operating systems, multi-core
1	Licheng Chen, Yongbing Huang, Yungang Bao, Onur Mutlu, Guangming Tan, Mingyu Chen	Poster: revisiting virtual channel memory for performance and fairness on multi-core architecture.	ICS	2011	DBLP DOI BibTeX RDF
1	Fazal Hameed, Mohammad Abdullah Al Faruque, Jörg Henkel	Dynamic thermal management in 3D multi-core architecture through run-time adaptation.	DATE	2011	DBLP DOI BibTeX RDF
1	Navid Khoshavi, Hamid R. Zarandi, Mohammad Maghsoudloo	Control-flow error recovery using commodity multi-core architecture features.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Shouqing Hao, Qi Liu, Longbing Zhang, Jian Wang	Processes Scheduling on Heterogeneous Multi-core Architecture with Hardware Support.	NAS	2011	DBLP DOI BibTeX RDF
1	Chao Li, Wangyuan Zhang, Chang-Burm Cho, Tao Li	SolarCore: Solar energy driven multi-core architecture power management.	HPCA	2011	DBLP DOI BibTeX RDF
1	Reiley Jeyapaul, Fei Hong, Abhishek Rhisheekesan, Aviral Shrivastava, Kyoungwoo Lee	UnSync: A Soft Error Resilient Redundant Multicore Architecture.	ICPP	2011	DBLP DOI BibTeX RDF	core-level redundancy, redundant architecture, hardware detection, low power, soft error, error resilient, multi-core architecture
1	Ching-Chi Lin, Pangfeng Liu, Jan-Jan Wu	A Novel Approach for Finding Optimization Opportunities in Multicore Architectures.	ISPA	2011	DBLP DOI BibTeX RDF	parallel program behavior analysis, optimization opportunities for parallel programs, sampling based technique, multi-core architecture
1	Haitao Wei, Junqing Yu, Jiang Li	The design and evaluation of hierarchical multi-level parallelisms for H.264 encoder on multi-core architecture.	Comput. Sci. Inf. Syst.	2010	DBLP DOI BibTeX RDF
1	Yongheng Chen, Wanli Zuo, Fengling He, Kerui Chen	Optimization Strategy of Parallel Query Processing Based on Multi-core Architecture.	JCIT	2010	DBLP BibTeX RDF
1	Joo-Young Kim, Sejong Oh, Seungjin Lee, Minsu Kim, Jinwook Oh, Hoi-Jun Yoo	An attention controlled multi-core architecture for energy efficient object recognition.	Sig. Proc.: Image Comm.	2010	DBLP DOI BibTeX RDF
1	George Kornaros	A soft multi-core architecture for edge detection and data analysis of microarray images.	Journal of Systems Architecture - Embedded Systems Design	2010	DBLP DOI BibTeX RDF
1	Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrjä, Fragkiskos Ieromnimon, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, Philippe Martin	Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Pascal Vivet, Edith Beigné, Hugo Lebreton, Nacer-Eddine Zergainoh	On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS.	PATMOS	2010	DBLP DOI BibTeX RDF
1	Art Black, Mohammad Muztaba Fuad	Survey and Classification of Software Technologies for Multi-core Architecture.	CAINE	2010	DBLP BibTeX RDF
1	Jih-Ching Chiu, Yu-Liang Chou, Po-Kai Chen	Hyperscalar: A Novel Dynamically Reconfigurable Multi-core Architecture.	ICPP	2010	DBLP DOI BibTeX RDF
1	Yan Sun, Haiqin Liu, Victor C. Valgenti, Min Sik Kim	Hybrid Regular Expression Matching for Deep Packet Inspection on Multi-Core Architecture.	ICCCN	2010	DBLP DOI BibTeX RDF
1	Zhang Jun, Mei Kui-Zhi, Zhao Ji-Zhong	CSDA: An Adaptive Data Storage Strategy for Predictive Branch Path on Multi-Core Architecture.	CIT	2010	DBLP DOI BibTeX RDF	Chip Multi-core, Adaptation, Memory System, Confidence Estimation, Cache Pollution
1	Jun Zhang, Kui-zhi Mei, Ji-zhong Zhao	An Adaptive and Selective Instruction Active Push Mechanism for Multi-core Architecture.	NAS	2010	DBLP DOI BibTeX RDF	Chip Multi-core, Instruction Pre-fetch, Active Push, Adaptation, Memory System, Confidence Estimation
1	Kefei Cheng, Kewen Pan, Jun Feng, Yong Bai	Multi-core Architecture Cache Performance Analysis and Optimization Based on Distributed Method.	ADMA	2010	DBLP DOI BibTeX RDF
1	Guofu Feng, Chi Zhang, Dongmei Huang, Xiaoshe Dong	Porting Molecular Dynamics simulation to heterogeneous multi-core architecture.	BIC-TA	2010	DBLP DOI BibTeX RDF
1	Ruirui C. Huang, Daniel Y. Deng, G. Edward Suh	Orthrus: efficient software integrity protection on multi-cores.	ASPLOS	2010	DBLP DOI BibTeX RDF	replication-aware architecture, software diversity and redundancy, software security, multi-core architecture, memory protection
1	Liang Han, Wei Liu, James Tuck	Speculative parallelization of partial reduction variables.	CGO	2010	DBLP DOI BibTeX RDF	reduction variables, parallelization, thread-level speculation, multi-core architecture
1	Zhimin Chen, Richard Neil Pittman, Alessandro Forin	Combining multicore and reconfigurable instruction set extensions.	FPGA	2010	DBLP DOI BibTeX RDF	extensible microprocessors, reconfigurable instruction set extensions, embedded, multi-core
1	JongSoo Park, William J. Dally	Buffer-space efficient and deadlock-free scheduling of stream applications on multi-core architectures.	SPAA	2010	DBLP DOI BibTeX RDF	compiler and tools for concurrent programming, green computing and power-efficient architectures, multi-core architectures, stream programming
1	Sorin Faibish, Peter Bixby, John Forecast, Philippe Armangau, Sitaram Pawar	A new approach to file system cache writeback of application data.	SYSTOR	2010	DBLP DOI BibTeX RDF	cache writeback, dirty pages, rate flushing, watermark flushing, feedback loop, buffer cache
1	Sung-Wen Wang, Shu-Sian Yang, Hong-Ming Chen, Chia-Lin Yang, Ja-Ling Wu	A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Parallel algorithm, Video coding, SIMD, H.264/AVC, Deblocking filter
1	Jingling Yuan, Tao Jiang, Jingjing He, Luo Zhong	Grey Neural Network Based Predictive Model for Multi-core Architecture 2D Spatial Characteristics.	ISNN	2009	DBLP DOI BibTeX RDF
1	Yuxin Wang, Liye Yuan, He Guo, Xinzhong Hui, Yuansheng Yang	An Effective Approach for Multicast on Multi-core Architecture.	ScalCom-EmbeddedCom	2009	DBLP DOI BibTeX RDF
1	Yi Pang, Jiangtao Wen, Lifeng Sun, WeiDong Hu, Shiqiang Yang	Frame-level heuristic scheduling Multi-view Video Coding on symmetric multi-core architecture.	ICIP	2009	DBLP DOI BibTeX RDF
1	Mengxiao Liu, Weixing Ji, Zuo Wang, Jiaxin Li, Xing Pu	High Performance Memory Management for a Multi-core Architecture.	CIT	2009	DBLP DOI BibTeX RDF
1	Guoping Long, Dongrui Fan, Junchao Zhang	Characterizing and Understanding the Bandwidth Behavior of Workloads on Multi-core Processors.	Euro-Par	2009	DBLP DOI BibTeX RDF	phase model, memory bandwidth, multi-core architecture
1	Chang-Burm Cho, Wangyuan Zhang, Tao Li	Thermal Design Space Exploration of 3D Die Stacked Multi-core Processors Using Geospatial-Based Predictive Models.	SPEC Benchmark Workshop	2009	DBLP DOI BibTeX RDF	Thermal/power characterization, 3D die stacking, analytical modeling, multi-core architecture
1	Nicholas Lowell	Model-based software design tools for the cell processor.	ACM Southeast Regional Conference	2009	DBLP DOI BibTeX RDF	run-time kernel, system dataflow modeling, code generation, automatic target recognition, cell processor
1	Masato Edahiro	Parallelizing fundamental algorithms such as sorting on multi-core processors for EDA acceleration.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Junchang Wang, Haipeng Cheng, Bei Hua, Xinan Tang	Practice of parallelizing network applications on multi-core architectures.	ICS	2009	DBLP DOI BibTeX RDF	application-level protocol processing, deep content inspection, lock-free data structures, multi-core parallelization, pipelining implementation, tcp/ip protocol processing
1	Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King	PPT: joint performance/power/thermal management of DRAM memory for multi-core systems.	ISLPED	2009	DBLP DOI BibTeX RDF	page allocation, scheduling, power, temperature, DRAM memory
1	Elizabeth Whitaker Lynch, George F. Riley	Hardware Supported Time Synchronization in Multi-core Architectures.	PADS	2009	DBLP DOI BibTeX RDF	multi-core synchronization
1	Haroon-Ur-Rashid Khan, Shi Feng, Ji Weixing	Triplet Based Multi-core Interconnection Network and its Computational Efficiency.	ACIS-ICIS	2009	DBLP DOI BibTeX RDF
1	Nikolaos Alachiotis, Euripides Sotiriades, Apostolos Dollas, Alexandros Stamatakis	Exploring FPGAs for accelerating the phylogenetic likelihood function.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Enric Musoll	Trading off higher execution latency for increased reliability in tile-based massive multi-core architectures.	ISQED	2009	DBLP DOI BibTeX RDF
1	Mengxiao Liu, Weixing Ji, Xing Pu, Jiaxin Li	A Parallel Memory System Model for Multi-core Processor.	NAS	2009	DBLP DOI BibTeX RDF
1	Joar Sohl, Jian Wang, Dake Liu	Large Matrix Multiplication on a Novel Heterogeneous Parallel DSP Architecture.	APPT	2009	DBLP DOI BibTeX RDF	ePUMA, parallel DSP, vector memory, SIMD, permutation, matrix multiplication
1	Hui Liu, Zili Shao, Meng Wang, Junzhao Du, Chun Jason Xue, Zhiping Jia	Combining Coarse-Grained Software Pipelining with DVS for Scheduling Real-Time Periodic Dependent Tasks on Multi-Core Embedded Systems.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Periodic dependent tasks, Scheduling, Multimedia, Real-time, Dynamic voltage scaling (DVS), Multi-core, Software pipelining, Retiming
1	Md. Rafiqul Islam, Jaipal Singh, Ashley Chonka, Wanlei Zhou	Multi-classifier Classification of Spam Email on a Ubiquitous Multi-core Architecture.	NPC Workshops	2008	DBLP DOI BibTeX RDF	Text Classifier, Multi-core, Spam Filters, Multiple Classifiers
1	Like Yan, Qingsong Shi, Tianzhou Chen, Guobing Chen	An On-chip Communication Mechanism Design in the Embedded Heterogeneous Multi-core Architecture.	ICNSC	2008	DBLP DOI BibTeX RDF
1	Alexandre Duchateau, Albert Sidelnik, María Jesús Garzarán, David A. Padua	P-Ray: A Software Suite for Multi-core Architecture Characterization.	LCPC	2008	DBLP DOI BibTeX RDF
1	Enric Musoll	A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors.	ISQED	2008	DBLP DOI BibTeX RDF	low power, hot spots, power gating, Multi-core architecture
1	Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen, Hong Wang 0003, John Paul Shen	Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices.	IEEE Trans. Parallel Distrib. Syst.	2008	DBLP DOI BibTeX RDF	Speculative thread level parallelism, pre-computation slices, thread partitioning, multi-core architecture
1	Haipeng Cheng, Zheng Chen, Bei Hua, Xinan Tang	Scalable packet classification using interpreting: a cross-platform multi-core solution.	PPOPP	2008	DBLP DOI BibTeX RDF	architecture, multithreading, network processor, packet classification, thread-level parallelism, embedded system design
1	Jianjun Guo, Ming-che Lai, Zhengyuan Pang, Libo Huang, Fangyuan Chen, Kui Dai, Zhiying Wang	Hierarchical memory system design for a heterogeneous multi-core processor.	SAC	2008	DBLP DOI BibTeX RDF	memory, heterogeneous, multi-core
1	Alain Pegatoquet, Filip Thoen, Denis Paterson	Virtual Reality for 2.5 G Wireless Communication Modem Software Development.	COMPSAC	2008	DBLP DOI BibTeX RDF	EGPRS, simulation, MPSoC, GSM, GPRS, Virtual platform
1	Magnus Själander, Andrei Terechko, Marc Duranton	A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures.	DSD	2008	DBLP DOI BibTeX RDF
1	Eren Kursun, Chen-Yong Cher	Variation-aware thermal characterization and management of multi-core architectures.	ICCD	2008	DBLP DOI BibTeX RDF
1	Jianfeng Yang, Yinbo Xie, Qing Geng, Jolly Wang, Nick Bao	Using cP^2BL in Teaching Multi-Core Related Contents.	ICYCS	2008	DBLP DOI BibTeX RDF
1	Jiang HanPing, Yan Jun	Research and Design for IPSec Architecture on Kernel.	WKDD	2008	DBLP DOI BibTeX RDF	architecture, multi-core, kernel, IPSec
1	Thuy Duong Vu, Li Zhang, Chris R. Jesshope	The Verification of the On-Chip COMA Cache Coherence Protocol.	AMAST	2008	DBLP DOI BibTeX RDF	on-chip COMA cache coherence protocol, location consistency, verification, Abstract State Machine
1	Hans Vandierendonck, Sean Rul, Michiel Questier, Koen De Bosschere	Experiences with Parallelizing a Bio-informatics Program on the Cell BE.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Xiao-Feng Li, Ligang Wang, Chen Yang	A Fully Parallel LISP2 Compactor with Preservation of the Sliding Properties.	LCPC	2008	DBLP DOI BibTeX RDF	compactor, parallelization, Garbage collector
1	Haris Saybasili, Peter Kellman, J. Andrew Derbyshire, Elliot R. McVeigh, Michael A. Guttman	Parallelized Hybrid TGRAPPA Reconstruction for Real-Time Interactive MRI.	MICCAI	2008	DBLP DOI BibTeX RDF
1	Jun Yan, Wei Zhang 0002	Hybrid multi-core architecture for boosting single-threaded performance.	SIGARCH Computer Architecture News	2007	DBLP DOI BibTeX RDF
1	Omar S. Elkeelany, Ghulam Chaudhry	A multi-core architecture for bi-network protocol conversion.	ISCA PDCS	2007	DBLP BibTeX RDF
1	Tianzhou Chen, Guobing Chen, Hongjun Dai, Qingsong Shi	A function-based on-chip communication design in the heterogeneous multi-core architecture.	MUE	2007	DBLP DOI BibTeX RDF
1	Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Michael F. P. O'Boyle, Dionisios N. Pnevmatikatos, Alex Ramírez, Pascal Sainrat, André Seznec, Per Stenström, Olivier Temam	High-Performance Embedded Architecture and Compilation Roadmap.	T. HiPEAC	2007	DBLP DOI BibTeX RDF	HiPEAC, single core architecture, programming models and tools, simulation and system modelling, real-time systems, compilation, interconnection networks, benchmarking, reconfigurable computing, run-time systems, multi-core architecture, roadmap
1	Andrew B. Kahng	Design challenges at 65nm and beyond.	DATE	2007	DBLP DOI BibTeX RDF
1	Emiliano Dolif, Michele Lombardi, Martino Ruggiero, Michela Milano, Luca Benini	Communication-aware stochastic allocation and scheduling framework for conditional task graphs in multi-processor systems-on-chip.	EMSOFT	2007	DBLP DOI BibTeX RDF	multimedia dataflow streaming, scheduling, allocation
1	Marco Mantovani, Simone Leardini, Martino Ruggiero, Andrea Acquaviva, Luca Benini	A lightweight parallel java execution environment for embedded multiprocessor systems-on-chip.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	Java, MPSoC
1	Jim Kahle	Cell architecture: key physical design features and methodology.	ISPD	2007	DBLP DOI BibTeX RDF
1	Edmund S. L. Lam, Martin Sulzmann	A concurrent constraint handling rules implementation in Haskell with software transactional memory.	DAMP	2007	DBLP DOI BibTeX RDF	parallel implementation of concurrent language
1	Jeffery A. Brown, Rakesh Kumar, Dean M. Tullsen	Proximity-aware directory-based coherence for multi-core processor architectures.	SPAA	2007	DBLP DOI BibTeX RDF	chip multiprocessors, coherence
1	Ben Cope, Peter Y. K. Cheung, Wayne Luk	Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective.	ASAP	2007	DBLP DOI BibTeX RDF
1	Jinquan Dai, Long Li, Bo Huang 0002	Pipelined Execution of Critical Sections Using Software-Controlled Caching in Network Processors.	CGO	2007	DBLP DOI BibTeX RDF
1	Weifeng Zhang, Dean M. Tullsen, Brad Calder	Accelerating and Adapting Precomputation Threads for Effcient Prefetching.	HPCA	2007	DBLP DOI BibTeX RDF
1	Alban Douillet, Guang R. Gao	Software-Pipelining on Multi-Core Architectures.	PACT	2007	DBLP DOI BibTeX RDF
1	Dean M. Tullsen	HCW Keynote Address Holistic Design of Multi-Core Architectures.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Arun Kumar, Ganapathy Senthilkumar, Murali Krishna, Naresh Jayam, Pallav K. Baruah, Raghunath Sharma, Ashok Srinivasan, Shakti Kapoor	A Buffered-Mode MPI Implementation for the Cell BETM Processor.	International Conference on Computational Science	2007	DBLP DOI BibTeX RDF	heterogeneous multi-core processors, MPI, Cell processor
1	Junqing Yu, Haitao Wei	Video Processing and Retrieval on Cell Processor Architecture.	ICEC	2007	DBLP DOI BibTeX RDF
1	Haitao Wei, Junqing Yu	Loading OpenMP to Cell: An Effective Compiler Framework for Heterogeneous Multi-core Chip.	IWOMP	2007	DBLP DOI BibTeX RDF