Search results for "multiplier"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
6	Nuno Bandeira, Ken Vaccaro, James A. Howard	A Two's Complement Array Multiplier Using True Values of the Operands.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	Pezaris multiplier, Baugh-Wooley multiplier, celluar-subtractor multiplier, Array multiplier, parallel multiplier, binary multiplication
5	Johann Großschädl	The Chinese Remainder Theorem and its Application in a High-Speed RSA Crypto Chip.	ACSAC	2000	DBLP DOI BibTeX RDF	RSA/spl gamma/ crypto-chip, RSA encryption scheme, hardware performance, long-integer modular arithmetic, private key operations, multiplier architecture, high-speed hardware accelerator, reconfigurable multiplier datapath, word-serial multiplier, modular reduction method, multiplier core, decryption rate, 200 MHz, 560 kbit/s, 2 Mbit/s, parallelism, pipelining, public key cryptography, reconfigurable architectures, clocks, Chinese Remainder Theorem, microprocessor chips, multiplying circuits, modular multiplications, modular exponentiations, pipeline arithmetic, clock frequency
5	W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi	A 16-bit x 16-bit 1.2 /spl mu/ CMOS multiplier with low latency vector merging.	VLSI Design	1995	DBLP DOI BibTeX RDF	CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron
5	S. M. Aziz	A C-testable modified Booth's array multiplier.	VLSI Design	1995	DBLP DOI BibTeX RDF	C-testable multiplier, modified Booth algorithm, gate-level design, parallel processing, logic testing, integrated circuit testing, digital arithmetic, stuck-at faults, CMOS logic circuits, multiplying circuits, logic arrays, array multiplier, parallel multiplier
5	Peter Kornerup	A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	systolic linear-array multiplier, right-shift algorithms, multiplier cell, digit-product terms, least significant digit first, active elements, module-multiplier, Montgomery module-reduction, RSA encryption, modular division, cryptography, logic design, systolic arrays, systolic array, digital arithmetic, multiplying circuits, latches, modular inverses, Hensel codes, digit-serial multiplier
4	Ron S. Waters, Earl E. Swartzlander Jr.	A Reduced Complexity Wallace Multiplier Reduction.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	High-speed multiplier, Wallace multiplier, Dadda multiplier
4	Dimitris Bekiaris, Kiamal Z. Pekmestzi, Christos A. Papachristou	A high-speed radix-4 multiplexer-based array multiplier.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	modified booth, multiplexer-based, radix-4 multiplier, array multiplier
4	Stefan Lemsitzer, Johannes Wolkerstorfer, Norbert Felber, Matthias Braendli	Multi-gigabit GCM-AES Architecture Optimized for FPGAs.	CHES	2007	DBLP DOI BibTeX RDF	Galois/Counter Mode (GCM), hybrid multiplier, Field Programmable Gate Array (FPGA), Very Large Scale Integration (VLSI), Advanced Encryption Standard (AES), high throughput, digit-serial multiplier, bit-parallel multiplier
4	Sandeep S. Kumar, Thomas J. Wollinger, Christof Paar	Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	least significant digit multiplier, elliptic/hyperelliptic curve cryptography, public key cryptography, digit serial multiplier, Bit serial multiplier
4	Zhijun Huang, Milos D. Ercegovac	High-Performance Low-Power Left-to-Right Array Multiplier Design.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Left-to-right array multiplier, tree multiplier, layout regularity, low-power design, high-performance design
4	Jinn-Shyan Wang, Chien-Nan Kuo, Tsung-Han Yang	Low-power fixed-width array multipliers.	ISLPED	2004	DBLP DOI BibTeX RDF	fixed-width multiplier, left-to-right multiplier, reduced-width multiplier, low power
4	Alexandre F. Tenca, Georgi Todorov, Çetin Kaya Koç	High-Radix Design of a Scalable Modular Multiplier.	CHES	2001	DBLP DOI BibTeX RDF	modular multiplier, montgomery multiplier, high-radix, scalable architecture
4	Jaswinder Pal Singh, A. Kumar, Sanjeev Kumar	A multiplier generator for Xilinx FPGAs.	VLSI Design	1996	DBLP DOI BibTeX RDF	multiplier generator, Xilinx FPGAs, LUT based FPGA, sequential designs, combinational designs, pipelined designs, IDEAS synthesis system, XC3000 family, XC4000 family, dedicated carry logic, XACT tool, XBLOX tool, field programmable gate arrays, high level synthesis, sequential circuits, combinational circuits, digital arithmetic, logic CAD, pipeline processing, integrated circuit design, circuit CAD, table lookup, multiplying circuits, module generator, carry logic, multiplier designs
4	Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang	Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	pipelined multipliers, nonpipelined multipliers, Baugh-Wooley multiplier, binary tree multiplier, Wallace tree multiplier, STDs, sub circuits, energy values, cubic dependence, word length, quadratic dependence, digital CMOS circuits, CMOS adder, low power arithmetic units, power consumption, power consumption, switching activity, state transition diagrams
4	Mallika De, Bhabani P. Sinha	Testing of a parallel ternary multiplier using I/sup 2/L logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	integrated injection logic, parallel ternary multiplier, I/sup 2/L logic, multivalued I/sup 2/L circuits, input balanced ternary full adder, precarry generator, multivalued current inputs, multivalued current outputs, generated test sets, skew fault, fault diagnosis, logic testing, design for testability, logic design, digital arithmetic, fault location, stuck-at fault, generalized model, adders, adder, multiplying circuits, multivalued logic circuits, test sets, parallel multiplier
3	Che Wun Chiou, Jim-Min Lin, Chiou-Yng Lee, Chi-Ting Ma	Novel Mastrovito Multiplier over GF(2m) Using Trinomial.	ICGEC	2011	DBLP DOI BibTeX RDF	Mastrovito multiplier, cryptography, elliptic curve cryptosystem, public-key cryptosystems, finite field multiplier
3	Shreesha Srinath, Katherine Compton	Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks.	FPGA	2010	DBLP DOI BibTeX RDF	asymmetric multipliers, composable multipliers, multiplier design
3	Chua-Chin Wang, Gang-Neng Sung	Low-Power Multiplier Design Using a Bypassing Technique.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Low power multiplier, Timing control, Partial product, Bypassing
3	Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi	Sign Bit Reduction Encoding For Low Power Applications.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Low power multiplier, Signed multiplier, Sign extension, FIR filter, Power reduction, Energy reduction, Bus encoding
3	Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi	A New Finite-Field Multiplier Using Redundant Representation.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	cyclotomic field, multiplier, Finite field arithmetic, Redundant representation, optimal normal basis
3	Tae Ho Kim, Sang Chul Kim, Chang Hoon Kim, Chun Pyo Hong	Scalable Montgomery Multiplier for Finite Fields GF(p) and GF(2^m).	DELTA	2008	DBLP DOI BibTeX RDF	Multi-Precision CSA, Scalable Multiplier, VLSI, Montgomery Multiplication
3	Arash Reyhani-Masoleh	A New Bit-Serial Architecture for Field Multiplication Using Polynomial Bases.	CHES	2008	DBLP DOI BibTeX RDF	Finite or Galois field, Mastrovito multiplier, polynomial basis, bit-serial multiplier
3	M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas	New and Improved Architectures for Montgomery Modular Multiplication.	MONET	2007	DBLP DOI BibTeX RDF	reconfigurable multiplier, scalable multiplier, RSA, ECC, carry save adders, Montgomery modular multiplication
3	Sun-Mi Park, Ku-Young Chang, Dowon Hong	Efficient Bit-Parallel Multiplier for Irreducible Pentanomials Using a Shifted Polynomial Basis.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	shifted polynomial basis, irreducible pentanomial, finite field arithmetic, Bit-parallel multiplier
3	K. M. Tsui, S. C. Chan	Error Analysis and Efficient Realization of the Multiplier-Less FFT-Like Transformation (ML-FFT) and Related Sinusoidal Transformations.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	Radix-p Fast Fourier Transform (FFT), Multiplier-less approximation, Sum-of-Powers-of-two (SOPOT), Real-valued, Discrete W Transform (DWT), Implementation, Discrete Cosine Transform (DCT), Discrete Fourier Transform (DFT), Error analysis
3	Chiou-Yng Lee, Jenn-Shyong Horng, I-Chang Jou	Low-Complexity Bit-Parallel Multiplier over GF(2m) Using Dual Basis Representation.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	Galois field GF(2m), inner product, dual basis, bit-parallel systolic multiplier
3	Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin	Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2m).	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	cryptography, fault-tolerant computing, fault detection, multiplier, finite fields arithmetic
3	Ku-Young Chang, Dowon Hong, Hyun-Sook Cho	Low Complexity Bit-Parallel Multiplier for GF(2^m) Defined by All-One Polynomials Using Redundant Representation.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Karatsuba method, AOP, finite field arithmetic, redundant representation, Bit-parallel multiplier
3	Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin	Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2m).	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	cryptography, fault-tolerant computing, fault detection, finite fields, multiplier, single stuck-at fault
3	M. Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José C. Monteiro	Design of a radix-2m hybrid array multiplier using carry save adder format.	SBCCI	2005	DBLP DOI BibTeX RDF	hybrid multiplier, low power, carry save adder
3	Chang Han Kim, Yongtae Kim, Nam Su Chang, IlWhan Park	Modified Serial Multipliers for Type-IV Gaussian Normal Bases.	INDOCRYPT	2005	DBLP DOI BibTeX RDF	serial multiplier, Finite fields, ECC, Massey-Omura multiplier, Gaussian Normal Basis
3	Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman	Complex +/-1 Multiplier Based on Signed-Binary Transformations.	VLSI Signal Processing	2004	DBLP DOI BibTeX RDF	PN code scrambler, complex ±1 multiplier, signed-binary number representation, VLSI, CDMA, redundant arithmetic
3	Sangjin Hong, Shu-Shin Chin, Suhwan Kim, Wei Hwang	Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization.	VLSI Signal Processing	2004	DBLP DOI BibTeX RDF	low-power multiplier, coefficient optimization, power weight factor, power modeling
3	Yijun Liu, Stephen B. Furber	The design of a low power asynchronous multiplier.	ISLPED	2004	DBLP DOI BibTeX RDF	Booth's algorithm, low power, benchmark, multiplier, asynchronous logic
3	Ahmet Akkas, Michael J. Schulte	A Quadruple Precision and Dual Double Precision Floating-Point Multiplier.	DSD	2003	DBLP DOI BibTeX RDF	Quadruple precision, computer arithmetic, normalization, floating-point, multiplier, rounding, double precision
3	Jia Di, Jiann S. Yuan	Power-aware pipelined multiplier design based on 2-dimensional pipeline gating.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	2-D pipeline gating, power-awareness, array multiplier
3	Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-seog Choi	54x54-bit radix-4 multiplier based on modified booth algorithm.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	compressor, adder, multiplier, booth encoder, wallace tree
3	Yeshwant Kolla, Yong-Bin Kim, John Carter	A novel 32-bit scalable multiplier architecture.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	CMOS VLSI, architecture, multiplier
3	Jong-Hak Hwang, Kyung-Jae Moon, Seung-Yong Park, Heung-Soo Kim	A New Construction of the Irreducible Polynomial for parallel multiplier over GF(2m). (PDF / PS)	ISMVL	2003	DBLP DOI BibTeX RDF	Systolic Multiplier, IPG, Trinomial, Finite Field
3	Xu Zhou, Zhimin Tang	A New Architecture of a Fast Floating-Point Multiplier.	APPT	2003	DBLP DOI BibTeX RDF	Floating-point Multiplier, Processor
3	Markus Hütter, Johann Großschädl, Guy-Armand Kamendje	A Versatile and Scalable Digit-Serial/Parallel Multiplier Architecture for Finite Fields GF(2m).	ITCC	2003	DBLP DOI BibTeX RDF	binary extension fields, digit-serial/parallel multiplier, Elliptic curve cryptography, critical path
3	Alexandre F. Tenca, Çetin Kaya Koç	A Scalable Architecture for Modular Multiplication Based on Montgomery's Algorithm.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	modular multiplier, scalable multiplier, Cryptography, Montgomery multiplication, modular multiplication
3	Arash Reyhani-Masoleh, M. Anwarul Hasan	A New Construction of Massey-Omura Parallel Multiplier over GF(2m).	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	optimal normal bases, Finite field, Massey-Omura multiplier, all-one polynomial
3	Huapeng Wu, M. Anwarul Hasan, Ian F. Blake, Shuhong Gao	Finite Field Multiplier Using Redundant Representation.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	cyclotomic ring, redundant set, multiplier, Finite field arithmetic, normal basis, squaring
3	S. M. Aziz, C. N. Basheer, Joarder Kamruzzaman	A Synthesisable VHDL Model for an Easily Testable Generalised Multiplier.	DELTA	2002	DBLP DOI BibTeX RDF	Modified Booth, Generic, Synthesis, VHDL, Multiplier, C-Testable
3	Simon C. Li, Jimmy C. Cha	±0.5V ±1.5V VHF CMOS LV/LP four-quadrant analog multiplier in modified bridged-triode scheme.	ISLPED	2002	DBLP DOI BibTeX RDF	modified bridged-triode scheme (MBTS), analog multiplier
3	Hak-soo Yu, Jacob A. Abraham	An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation.	VLSI Design	2002	DBLP DOI BibTeX RDF	3-bit-scan, power-delay-area tradeoffs, synchronous sequential, multiplier, partial product
3	Berk Sunar, Çetin Kaya Koç	An Efficient Optimal Normal Basis Type II Multiplier.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Galois field, space complexity, optimal normal basis, Massey-Omura multiplier
3	Johann Großschädl	A Bit-Serial Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m).	CHES	2001	DBLP DOI BibTeX RDF	iterative modulo multiplication, polynomial basis representation, bit-serial multiplier architecture, smart card crypto-coprocessor, Elliptic curve cryptography, finite field arithmetic
3	Wen-Chang Yeh, Chein-Wei Jen	High-Speed Booth Encoded Parallel Multiplier Design.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Final adder, multiple-level conditional-sum adder and parallel multiplier, Booth encoding
3	Rong Lin	A Reconfigurable Low-Power High-Performance Matrix Multiplier Design.	ISQED	2000	DBLP DOI BibTeX RDF	low-power CMOS circuits, parallel counter-multiplier circuits, reconfigurable architecture, Matrix multiplication
3	Kyeounsoo Kim, Peter A. Beerel, Youpyo Hong	An asynchronous matrix-vector multiplier for discrete cosine transform.	ISLPED	2000	DBLP DOI BibTeX RDF	asynchronous matrix-vector multiplier, discrete cosine transform
3	Carl James Debono, Franco Maloberti, Joseph Micallef	A low-voltage CMOS multiplier for RF applications (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF	CMOS, low-voltage, RF, analog multiplier
3	Takafumi Aoki, Ken-ichi Hoshi, Tatsuo Higuchi	Redundant Complex Arithmetic and Its Application to Complex Multiplier Design. (PDF / PS)	ISMVL	1999	DBLP DOI BibTeX RDF	Complex Number System, VLSI, Computer Arithmetic, Multiplier, Arithmetic Circuits
3	Gerardo Orlando, Christof Paar	A Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms.	FCCM	1999	DBLP DOI BibTeX RDF	Galois Fields multiplier, field programmable gate array application, cryptography, elliptic curve cryptography
3	Bong-Il Park, In-Cheol Park, Chong-Min Kyung	A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders.	ICCD	1999	DBLP DOI BibTeX RDF	Booth algorithm, Carry-Save Adder and Wallace Tree, Multiplier
3	Chanyutt Arjhan, Raghvendra G. Deshmukh	A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	parallel divider, parallel-array divider, pf-model, summand-generator, summand-counter, multiple faults functional testing, design for testability, boundary scan, array multiplier, Parallel multiplier
3	Charles A. Klein, Li-Chung Chu	Comparison of Extended Jacobian and Lagrange Multiplier Based Methods for Resolving Kinematic Redundancy.	Journal of Intelligent and Robotic Systems	1997	DBLP DOI BibTeX RDF	extended Jacobian method, Lagrange multiplier method, kinematically redundant manipulators, optimization, robotics, numerical efficiency
3	Eric M. Schwarz, Robert M. Averill III, Leon J. Sigal	A Radix-8 CMOS S/390 Multiplier.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	Booth algorithm, computer arithmetic, multiplication, multiplier, floating-point unit
3	David W. Matula, Asger Munk Nielsen	Pipelined Packet-Forwarding Floating Point: I. Foundations and a Rounder.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	pipelined packet forwarding floating point, packet forwarding floating point format, rounder design, packet forwarding format, standard binary IEEE 754 floating point format, multiplication algorithms, ALU pipeline paradigm, data hazards, pipelined floating point operations, execution phases, multiplier packet forwarding pipelines, execution phase, logic levels, multiplier pipelines, forwarding pipelines, IEEE 754 binary floating point compatibility, pipeline arithmetic, data dependent operations
3	Ranjeet Ranade, Sanjay Bhandari, A. N. Chandorkar	VLSI Implementation of Artificial Neural Network Based Digital Multiplier and Adder.	VLSI Design	1996	DBLP DOI BibTeX RDF	Digital Multiplier and Adder, VLSI Implementation of Neural Networks, Artificial Neural Networks (ANN)
3	D. V. Poornaiah, P. V. Ananda Mohan	A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications.	VLSI Design	1996	DBLP DOI BibTeX RDF	concurrent dual multiplier-dual adder architecture, video coding applications, high-throughput image coding, carry-save 4:2 compressors, computational complexity, VLSI, VLSI, data compression, video coding, adders, computation time, multiplying circuits, digital signal processing chips
3	George A. Hadgis, P. R. Mukund	A novel CMOS monolithic analog multiplier with wide input dynamic range.	VLSI Design	1995	DBLP DOI BibTeX RDF	analogue multipliers, circuit feedback, CMOS monolithic analog multiplier, input dynamic range, voltage-controlled variable linear resistor, feedback network, PSpice simulation results, circuit analysis computing, linearity, SPICE, operational amplifiers, operational amplifier, CMOS analogue integrated circuits
3	D. V. Poornaiah, P. V. Ananda Mohan	Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture.	VLSI Design	1995	DBLP DOI BibTeX RDF	concurrent multiplier-accumulator architecture, second order modified Booth algorithm, sign extension bits minimization algorithm, sign-bit updating algorithm, multi-bit recoded parallel multipliers, computation time reduction, CMOS standard cell technology, 35 ns, 50 pF, parallel algorithms, VLSI, VLSI, parallel architectures, digital arithmetic, multiplication, CMOS logic circuits, multiplying circuits, accumulation, 1 micron
3	Suthikshn Kumar, Kevin E. Forward, M. Palaniswami	A fast-multiplier generator for FPGAs.	VLSI Design	1995	DBLP DOI BibTeX RDF	fast-multiplier generator, variable word length multipliers, Booth encoded optimized Wallace tree architecture, field programmable gate arrays, FPGAs, parallel architectures, artificial neural networks, multiplying circuits, FPGA architecture, neural chips
3	Charles U. Martel, Vojin G. Oklobdzija, R. Ravi, Paul F. Stelling	Design Strategies for Optimal Multiplier Circuits.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	Algorithms, Circuit design, Partial product reduction, Multiplier design
3	Belle W. Y. Wei, He Du, Honglu Chen	A complex-number multiplier using radix-4 digits.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	complex-number multiplier, radix-4 digits, arithmetic datapath, complex-number digital signal processor, binary signed digits, fast multiplication, compact layout, three-multiplication scheme, radix-4 operands, delays, delay, encoding, digital arithmetic, multiplying circuits, binary additions, coding scheme
3	S. Cui, Neil Burgess, Michael J. Liebelt, Kamran Eshraghian	A GaAs IEEE Floating Point Standard Single Precision Multiplier.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	floating point multiplier, rounding algorithm, modified carry save array, GaAs technology
3	H. Yamada, T. Hotta, T. Nishiyama, F. Murabayashi, T. Yamauchi, H. Sawamoto	A 13.3ns double-precision floating-point ALU and multiplier. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	double-precision floating-point ALU, floating-point multiplier, carry select addition, prerounding techniques, noise tolerant precharge circuit, two-cycle latency, 13.3 ns, 0.3 micron, 2.5 V, 150 MHz, normalization, floating point arithmetic, CMOS integrated circuits, multiplying circuits, CMOS technology, arithmetic logic unit
3	Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi	High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	multiple-valued current-mode circuits, high-speed multiplier, carry-propagation-free addition trees, multiple-valued current-mode, carry-propagation-free addition, area efficient design, VLSI, VLSI, tree structure, multiplying circuits, redundant number representations, number representations, multiplier design
3	Giuseppe Alia, Enrico Martinelli	A VLSI Modulo m Multiplier.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	modulo m multiplier, residue multiplier, computational complexity, VLSI, VLSI, digital arithmetic, modular multiplications
3	In-Shek Hsu, Trieu-Kien Truong, Leslie J. Deutsch, Irving S. Reed	A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	dual-basis multiplier, Massey-Omura normal basis multiplier, Scott-Tavares-Peppard standard basis multiplier, NMOS technology, VLSI, VLSI architecture, multiplying circuits, finite field multipliers, field effect integrated circuits
3	Charles C. Wang, Trieu-Kien Truong, Howard M. Shao, Leslie J. Deutsch, Jim K. Omura, Irving S. Reed	VLSI Architectures for Computing Multiplications and Inverses in GF(2m).	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	Finite field inverse, normal basis multiplier, pipeline, systolic array, inverse, normal basis, finite field multiplication, Massey-Omura multiplier, finite field multiplier
3	R. Gnanasekaran	On a Bit-Serial Input and Bit-Serial Output Multiplier.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	two's complement number representation, Add-shift multiplier, bit-sequential multiplier, on-line multiplication, carry-save addition
2	Wonhak Hong, Rajashekhar Modugu, Minsu Choi	Efficient Online Self-Checking Modulo 2^n+1 Multiplier Design.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	Modulo 2^n+1 multiplier, arithmetic circuit design, compressor, online self-checking, international data encryption algorithm (IDEA), residue arithmetic
2	Chiou-Yng Lee, Pramod Kumar Meher	Speeding up Subquadratic Finite Field Multiplier over GF(2m) Generated by Trinomials Using Toeplitz Matrix-Vector with Inner Product Formula.	ICGEC	2011	DBLP DOI BibTeX RDF	Subquadratic multiplier, Toeplitz matrix-vector product, inner product
2	Alaaeldin Amin, M. Waleed Shinwari	High-Radix Multiplier-Dividers: Theory, Design, and Hardware.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	quotient digit selection, multiplier-divider, Computer arithmetic, division, SRT
2	Qingzheng Li, Guixuan Liang, Amine Bermak	A High-speed 32-bit Signed/Unsigned Pipelined Multiplier.	DELTA	2010	DBLP DOI BibTeX RDF	signed/unsigned multiplier, fast adder, Booth Encoding, Wallace Tree
2	Y. Hamid, Martin Langhammer	Multiplier architectures for FPGA double precision functions (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, floating point
2	Yixiong Guo, Jun Ding, Na Li, Jun Yang	A Research and Design of Decimal Floating Multiplier Based on FPGA.	WKDD	2010	DBLP DOI BibTeX RDF	Decimal floating multiplier, DPD codec, BCD new codec, Signed-Digit radix-5, Decimal 32:2 CSA
2	V. Jeyakumar, S. Srisatkunarajah	Lagrange multiplier necessary conditions for global optimality for non-convex minimization over a quadratic constraint via S-lemma.	Optimization Letters	2009	DBLP DOI BibTeX RDF	Smooth non-convex minimization, Difference of quadratic and convex functions, Single quadratic constraint, Global optimality, Lagrange multipliers, Fractional programs
2	Dimitri Tan, Carl Lemonds, Michael J. Schulte	Low-Power Multiple-Precision Iterative Floating-Point Multiplier with SIMD Support.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
2	Ismo Hänninen, Jarmo Takala	Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata.	SAMOS	2009	DBLP DOI BibTeX RDF	nanotechnology, multiplication, arithmetic, QCA
2	Jianping Quan, Guoqiang Bai	A DPA-Resistant Digit-Parallel Modular Multiplier over GF (2m).	ITNG	2009	DBLP DOI BibTeX RDF	Modular multiplier, DPA-resistant, 1-bit masking, ECC, Architecture level
2	Luciano A. de Lacerda, Edson P. Santana, Cleber Vinícius A. de Almeida, Ana Isabela A. Cunha	Distortion analysis of analog multiplier circuits using two-dimensional integral nonlinear function.	SBCCI	2009	DBLP DOI BibTeX RDF	CMOS multipliers, distortion, analog multipliers
2	Yves Edel, Alexander Pott	On Designs and Multiplier Groups Constructed from Almost Perfect Nonlinear Functions.	IMA Int. Conf.	2009	DBLP DOI BibTeX RDF
2	Charles Tsen, Sonia Gonzalez-Navarro, Michael J. Schulte, Brian J. Hickmann, Katherine Compton	A Combined Decimal and Binary Floating-Point Multiplier.	ASAP	2009	DBLP DOI BibTeX RDF
2	Mark S. K. Lau, Keck Voon Ling, Yun-Chung Chu	Energy-aware probabilistic multiplier: design and analysis.	CASES	2009	DBLP DOI BibTeX RDF	optimization, multiplier, voltage scaling, probabilistic computation
2	Malte Baesler, Thomas Teufel	FPGA Implementation of a Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier.	ReConFig	2009	DBLP DOI BibTeX RDF	decimal multiplier, IEEE 754-2008, accurate scalar product, FPGA, floating point
2	Johann Großschädl, Erkay Savas, Kazim Yumbul	Realizing Arbitrary-Precision Modular Multiplication with a Fixed-Precision Multiplier Datapath.	ReConFig	2009	DBLP DOI BibTeX RDF	Bit-serial multiplier architecture, Scalability, Montgomery modular multiplication
2	Michalis Vavouras, Kyprianos Papadimitriou, Ioannis Papaefstathiou	Implementation of a genetic algorithm on a virtex-ii pro FPGA.	FPGA	2009	DBLP DOI BibTeX RDF	multiplier blocks, genetic algorithm, fpga, fitness functions
2	Gang Zhou, Harald Michalik, László Hinsenkamp	Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs.	ARC	2009	DBLP DOI BibTeX RDF	AES-GCM, pipelined Karatsuba multiplier, FPGAs, finite field arithmetic
2	Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals, Eiji Okamoto, Francisco Rodríguez-Henríquez	Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers.	CHES	2009	DBLP DOI BibTeX RDF	Karatsuba-Ofman multiplier, FPGA, elliptic curve, hardware accelerator, Tate pairing, finite field arithmetic, ? T pairing
2	Mustafa Gök, Metin Mete Özbilen	Evaluation of Sticky-Bit Generation Methods for Floating-Point Multipliers.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Floating-point multiplier, Sticky-bit, Rounding
2	Giovanni Giallombardo, Daniel Ralph	Multiplier convergence in trust-region methods with application to convergence of decomposition methods for MPECs.	Math. Program.	2008	DBLP DOI BibTeX RDF	Mathematics Subject Classification (2000) 90C30, 90C33
2	Oliver A. Pfänder, Hans-Jörg Pfleiderer	EMMA - A suggestion for an embedded multi-precision multiplier array for FPGAs.	FPL	2008	DBLP DOI BibTeX RDF
2	Horácio C. Neto, Mário P. Véstias	Decimal multiplier on FPGA using embedded binary multipliers.	FPL	2008	DBLP DOI BibTeX RDF
2	Saroja V. Siddamal, R. M. Banakar, B. C. Jinaga	Design of High-Speed Floating Point Multiplier.	DELTA	2008	DBLP DOI BibTeX RDF	FP operations, Fast Carry look ahead adder (MCLA), CSD algorithm, Booth algorithm
2	Abner Correa Barros, Victor Wanderley Costa de Medeiros, Viviane Lucy Santos de Souza, Paulo Sérgio Brandão do Nascimento, Ângelo Mazer, João Paulo Fernandes Barbosa, Bruno P. Neves, Ismael Santos, Manoel Eusebio de Lima	Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA.	SBCCI	2008	DBLP DOI BibTeX RDF	FPGA, scientific computing, floating-point, HPC
2	Soman Purushothaman	A simple 4 quadrant NMOS analog multiplier with input range equal to +/-VDD and very low THD.	EIT	2008	DBLP DOI BibTeX RDF