Search results for "multipliers"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Shreesha Srinath, Katherine Compton	Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks.	FPGA	2010	DBLP DOI BibTeX RDF	asymmetric multipliers, composable multipliers, multiplier design
4	Francisco Rodríguez-Henríquez, Çetin Kaya Koç	Parallel Multipliers Based on Special Irreducible Pentanomials.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	pentanomials, multipliers for GF(2^m), Finite fields arithmetic, parallel multipliers
4	Kiamal Z. Pekmastzi	Multiplexer-Based Array Multipliers.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	multiplication algorithm, two's complement multiplication, pipeline multipliers, Array multipliers
4	Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang	Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	pipelined multipliers, nonpipelined multipliers, Baugh-Wooley multiplier, binary tree multiplier, Wallace tree multiplier, STDs, sub circuits, energy values, cubic dependence, word length, quadratic dependence, digital CMOS circuits, CMOS adder, low power arithmetic units, power consumption, power consumption, switching activity, state transition diagrams
4	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	An effective BIST scheme for carry-save and carry-propagate array multipliers.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST scheme, carry-propagate array multipliers, carry-save array multipliers, complex VLSI devices, maximum length LFSR, count-based scheme, multiplier cells, VLSI, logic testing, controllability, built-in self test, integrated circuit testing, automatic testing, observability, fault coverage, test pattern generator, multiplying circuits, carry logic
3	Luciano A. de Lacerda, Edson P. Santana, Cleber Vinícius A. de Almeida, Ana Isabela A. Cunha	Distortion analysis of analog multiplier circuits using two-dimensional integral nonlinear function.	SBCCI	2009	DBLP DOI BibTeX RDF	CMOS multipliers, distortion, analog multipliers
3	Patrizia Daniele	Lagrange multipliers and infinite-dimensional equilibrium problems.	J. Global Optimization	2008	DBLP DOI BibTeX RDF	Separation theory, Quasi relative interior, Lagrange multipliers, Equilibrium problems
3	Robert T. Grisamore, Earl E. Swartzlander Jr.	Negative Save Sign Extension for Multi-term Adders and Multipliers.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	adder trees, multi-term adders, two’s complement arithmetic, sign extension, multipliers
3	Pasquale Malacaria, Han Chen	Lagrange multipliers and maximum information leakage in different observational models.	PLAS	2008	DBLP DOI BibTeX RDF	security, information theory, lagrange multipliers
3	Hafizur Rahaman, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan	Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}).	VTS	2007	DBLP DOI BibTeX RDF	cryptography, polynomials, Multipliers, Galois field, error control code, Transition fault, C-testable
3	Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos	Efficient Diminished-1 Modulo 2^n+1 Multipliers.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Modulo 2^n+1 multipliers, Fermat number transform, computer arithmetic, VLSI design, residue number system
3	Gang Quan, James P. Davis, Siddhaveerasharan Devarkal, Duncan A. Buell	High-level synthesis for large bit-width multipliers on FPGAs: a case study.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	FPGA devices, large-scale integer multipliers, high level synthesis, reconfigurable computing, design exploration
3	Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos	Modified Booth Modulo 2n-1 Multipliers.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Mersenne arithmetic, one's complement arithmetic, Booth multipliers, VLSI design, Residue Number System
3	Lisa A. Korf	Stochastic programming duality: 8 multipliers for unbounded constraints with an application to mathematical finance.	Math. Program.	2004	DBLP DOI BibTeX RDF	arbitrage, fundamental theorem of asset pricing, duality, stochastic programming, Lagrange multipliers
3	T. Sansaloni, Javier Valls, Keshab K. Parhi	Digit-Serial Complex-Number Multipliers on FPGAs.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	complex-number multipliers, digit-serial arithmetic, FPGA, Booth recoding
3	Roman A. Polyak	Log-Sigmoid Multipliers Method in Constrained Optimization.	Annals OR	2001	DBLP DOI BibTeX RDF	log-sigmoid, multipliers method, smoothing technique, duality
3	Milos D. Ercegovac, Tomás Lang, Jean-Michel Muller, Arnaud Tisserand	Reciprocation, Square Root, Inverse Square Root, and Some Elementary Functions Using Small Multipliers.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	inverse square root, single-/double-precision operations, small multipliers, exponential, square root, Reciprocal, logarithm, Taylor series
3	Kiamal Z. Pekmestzi, Paraskevas Kalivas	Constant Number Serial Pipeline Multipliers.	VLSI Signal Processing	2000	DBLP DOI BibTeX RDF	constant number multiplication, serial multipliers, systolic circuits, canonic signed digit representation
3	Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos	Low Power BIST for Wallace Tree-Based Fast Multipliers.	ISQED	2000	DBLP DOI BibTeX RDF	Testing, Low Power, BIST, Multipliers, Wallace Trees
3	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	An Effective Built-In Self-Test Scheme for Parallel Multipliers.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	tree multipliers, Built-in self-test, array multipliers, cell fault model
3	Issam Alzaher-Noufal, Michael Nicolaidis	A CAD Framework for Generating Self-Checking 1 Multipliers Based on Residue Codes.	DATE	1999	DBLP DOI BibTeX RDF	Fault Secure Circuits, Residue Arithmetic Codes, Multipliers, Self-Checking Circuits
3	Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou	Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. (PDF / PS)	DFT	1999	DBLP DOI BibTeX RDF	Modified Booth Multipliers, Low Power, Built In Self Test, VLSI Testing
3	Sebastian T. J. Fenn, Michael Gössel, Mohammed Benaissa, David Taylor	On-Line Error Detection for Bit-Serial Multipliers in GF(2m).	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	finite fields, multipliers, parity checking, on-line error detection
3	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Effective Built-In Self-Test for Booth Multipliers.	IEEE Design & Test of Computers	1998	DBLP DOI BibTeX RDF	Booth multipliers, Built-In Self Test, design for testability, data paths
3	Michael Nicolaidis, Ricardo de Oliveira Duarte	Design of Fault-Secure Parity-Prediction Booth Multipliers.	DATE	1998	DBLP DOI BibTeX RDF	Booth multipliers, Self-checking circuits
3	Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis, Constantin Halatsis	C-Testable modified-Booth multipliers.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	Booth multipliers, design for testability, C-testability, iterative logic arrays, carry lookahead adders, cell fault model
3	Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin	Design tradeoffs in high speed multipliers and FIR filters.	VLSI Design	1996	DBLP DOI BibTeX RDF	high speed multipliers, high speed FIR filters, modified Booth recoding, pipeline granularity, transistor count, activity factor reduction, guarded evaluation, gate-level pipelining, half-bit level pipelining, bit-level pipelining, delay, clocking, digital filters, FIR filters, multiplying circuits, power dissipation, design tradeoffs, pipeline arithmetic, operation speed
3	Luca Breveglieri, Luigi Dadda, Vincenzo Piuri	Column Compression Pipelined Multipliers.	ASAP	1995	DBLP DOI BibTeX RDF	pipelining, computer arithmetic, multipliers
3	Hakim Bederr, Michael Nicolaidis, Alain Guyot	Analytic approach for error masking elimination in on-line multipliers.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	error masking elimination, online multipliers, high precision numbers, scan design approach, internal state observability, DFT approach, sequential circuits, digital arithmetic, fault coverage, multiplying circuits, area overhead
2	Valeria Garofalo, Nicola Petra, Ettore Napoli	Analytical Calculation of the Maximum Error for a Family of Truncated Multipliers Providing Minimum Mean Square Error.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	truncated multipliers, maximum error, digital arithmetic, error analysis, Multiplication, error compensation
2	Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija	Energy efficient implementation of parallel CMOS multipliers with improved compressors.	ISLPED	2010	DBLP DOI BibTeX RDF	arithmetic and logic structures, VLSI, low-power design, high- speed arithmetic, booth encoding
2	Masayuki Yoshino, Katsuyuki Okeya, Camille Vuillaume	Bipartite modular multiplication with twice the bit-length of multipliers.	Int. J. Inf. Sec.	2009	DBLP DOI BibTeX RDF	Bipartite modular multiplication, Double-size technique, RSA, Smartcard, Montgomery multiplication, Modular multiplication
2	Mustafa Gök, Metin Mete Özbilen	Evaluation of Sticky-Bit Generation Methods for Floating-Point Multipliers.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Floating-point multiplier, Sticky-bit, Rounding
2	Alexey F. Izmailov, Mikhail V. Solodov	On attraction of Newton-type iterates to multipliers violating second-order sufficiency conditions.	Math. Program.	2009	DBLP DOI BibTeX RDF	Mathematics Subject Classification (2000) 90C30
2	Marc Teboulle	Lagrangian Multipliers Methods for Convex Programming.	Encyclopedia of Optimization	2009	DBLP DOI BibTeX RDF	Proximal algorithms, Convex optimization, Augmented Lagrangians, Primal-dual methods, Lagrangian multipliers
2	Igor V. Evstigneev, Sjur Didrik Flåm	Stochastic Programming: Nonanticipativity and Lagrange Multipliers.	Encyclopedia of Optimization	2009	DBLP DOI BibTeX RDF	Nonanticipativity, Fritz John conditions, Yosida-Hewitt decomposition, Stochastic programming, Lagrange multipliers
2	Pachara V. Rao, Cyril Prasanna Raj P, S. Ravi	VLSI Design and Analysis of Multipliers for Low Power.	IIH-MSP	2009	DBLP DOI BibTeX RDF	Low Power, Delay, CMOS, Multipliers, Area, ASIC Implementation
2	Sjur Didrik Flåm, Hubertus Th. Jongen, Oliver Stein	Slopes of shadow prices and Lagrange multipliers.	Optimization Letters	2008	DBLP DOI BibTeX RDF	Optimal value function, Shadow price, Karush-Kuhn-Tucker system, Sensitivity, Matrix inversion
2	Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir	C-testable bit parallel multipliers over GF(2m).	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	testing, cryptography, built-in self-test, digital signal processing, polynomials, VLSI design, stuck-at fault, TPG, fault, multiplier, Galois field, error control code, C-testable
2	Jean-Luc Beuchat, Jean-Michel Muller	Automatic Generation of Modular Multipliers for FPGA Applications.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
2	Lucia Parussini	Fictitious Domain Approach Via Lagrange Multipliers with Least Squares Spectral Element Method.	J. Sci. Comput.	2008	DBLP DOI BibTeX RDF	Fictitious Domain, Least Squares Spectral Element Method, Lagrange multipliers
2	H.-C. Liang, P.-H. Huang, Y.-F. Tang	Testing Transition Delay Faults in Modified Booth Multipliers.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner	Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Jian-Feng Hu, Ping-Qi Pan	An efficient approach to updating simplex multipliers in the simplex algorithm.	Math. Program.	2008	DBLP DOI BibTeX RDF	Mathematics Subject Classification (2000) 65K05, 90C05
2	Horácio C. Neto, Mário P. Véstias	Decimal multiplier on FPGA using embedded binary multipliers.	FPL	2008	DBLP DOI BibTeX RDF
2	Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Lars Lundheim, Asghar Havashki	Power Optimization of Parallel Multipliers in Systems with Variable Word-Length.	PATMOS	2008	DBLP DOI BibTeX RDF
2	Chiou-Yng Lee, Pramod Kumar Meher	Efficient Bit-Parallel Multipliers in Composite Fields.	APSCC	2008	DBLP DOI BibTeX RDF
2	Udo Krautz, Markus Wedler, Wolfgang Kunz, Kai Weber, Christian Jacobi 0002, Matthias Pflanz	Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Jimson Mathew, Costas Argyrides, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan	Single Error Correcting Finite Field Multipliers Over GF(2m).	VLSI Design	2008	DBLP DOI BibTeX RDF	Galois Field Multiplier, VLSI, Cryptography, Error Correcting Codes
2	Ravi Kumar Satzoda, Ramya Muralidharan, Chip-Hong Chang	Programmable LSB-first and MSB-first modular multipliers for ECC in GF(2m).	ISCAS	2008	DBLP DOI BibTeX RDF
2	Kenny Johansson, Oscar Gustafsson, Lars Wanhammar	Switching activity estimation for shift-and-add based constant multipliers.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Sri Raga Sudha Garimella, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal	Design of highly linear multipliers using floating gate transistors and/or source degeneration resistor.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Man Yan Kong, J. M. Pierre Langlois, Dhamin Al-Khalili	Efficient FPGA implementation of complex multipliers using the logarithmic number system.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan	Fault tolerant bit parallel finite field multipliers using LDPC codes.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh	Systematic design of high-radix Montgomery multipliers for RSA processors.	ICCD	2008	DBLP DOI BibTeX RDF
2	Brian J. Hickmann, Michael J. Schulte, Mark A. Erle	Improved combined binary/decimal fixed-point multipliers.	ICCD	2008	DBLP DOI BibTeX RDF
2	Oliver A. Pfänder, Reinhard Nopper, Hans-Jörg Pfleiderer, Shun Zhou, Amine Bermak	Configurable Blocks for Multi-precision Multiplication.	DELTA	2008	DBLP DOI BibTeX RDF	reconfigurable multipliers, embedded blocks, multi-precision, FPGA, multiplication
2	Lelia Festila, Lorant Andras Szolga, Mihaela Cirlugea, Robert Groza	Analog Multiplying/Weighting VLSI Cells for SVM Classifiers.	KES	2008	DBLP DOI BibTeX RDF	weighting circuits, th domain, square-root domain, current controlled amplifiers, analog multipliers
2	Haining Fan, M. Anwar Hasan	A New Approach to Subquadratic Space Complexity Parallel Multipliers for Extended Binary Fields.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	subquadratic space complexity multiplier, shifted polynomial basis, Finite field, coordinate transformation, Toeplitz matrix
2	Katsushi Ohmori, Norikazu Saito	Flux-free Finite Element Method with Lagrange Multipliers for Two-fluid Flows.	J. Sci. Comput.	2007	DBLP DOI BibTeX RDF	Two-fluid flows, flux-free constraint, mass preserving, finite element method, Lagrange multipliers
2	Jamshid Shokrollahi, Elisa Gorla, Christoph Puttmann	Efficient FPGA-based multipliers for F_3^97 and F_3^(6*97).	FPL	2007	DBLP DOI BibTeX RDF
2	Michal Bidlo	Evolutionary Development of Generic Multipliers: Initial Results.	AHS	2007	DBLP DOI BibTeX RDF
2	Henrik Eriksson	Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers.	PATMOS	2007	DBLP DOI BibTeX RDF
2	Jiun-Ping Wang, Shiann-Rong Kuang	Area-Efficient Signed Fixed-Width Multipliers with Low-Error Compensation Circuit.	SiPS	2007	DBLP DOI BibTeX RDF
2	Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu	Low Power Multipliers Using Enhenced Row Bypassing Schemes.	SiPS	2007	DBLP DOI BibTeX RDF
2	Nathaniel Ross Pinckney, David Money Harris	Parallelized radix-4 scalable montgomery multipliers.	SBCCI	2007	DBLP DOI BibTeX RDF	cryptography, RSA, Montgomery Multiplication
2	Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Oscar Gustafsson	Transition-activity aware design of reduction-stages for parallel multipliers.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	power consumption, parallel multiplier, partial product reduction, transition activity
2	Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan	Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m).	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena	Switching Activity Models for Power Estimation in FPGA Multipliers.	ARC	2007	DBLP DOI BibTeX RDF
2	Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi	A New Family of High.Performance Parallel Decimal Multipliers.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
2	Michal Bidlo	Evolutionary Design of Generic Combinational Multipliers Using Development.	ICES	2007	DBLP DOI BibTeX RDF
2	Ioannis C. Demetriou	Algorithm 863: L2WPMA, a Fortran 77 package for weighted least-squares piecewise monotonic data approximation.	ACM Trans. Math. Softw.	2007	DBLP DOI BibTeX RDF	data smoothing, peak finding, piecewise monotonic, pound/dollar exchange rate, turning point, image processing, dynamic programming, Approximation, signal processing, histogram, spline, fitting, Lagrange multipliers, isotonic regression, divided difference
2	Ajay K. Verma, Paolo Ienne	Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands.	ASP-DAC	2007	DBLP DOI BibTeX RDF	multiplier-like circuits, XOR-dominated circuits, datapath design, netlist optimization, carry-save form, column compressors, XOR operations, logic synthesizers, algebraic factoring, computer arithmetic, logic synthesis, digital design, parallel multipliers
2	Raymond J. Madachy	Distributed Global Development Parametric Cost Modeling.	ICSP	2007	DBLP DOI BibTeX RDF	parametric cost modeling, Detailed COCOMO, phasesensitive effort multipliers, labor distribution, subcontracting, cost estimation, global software development, distributed teams, COCOMO, Distributed development, software lifecycles
2	Sandeep S. Kumar, Thomas J. Wollinger, Christof Paar	Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	least significant digit multiplier, elliptic/hyperelliptic curve cryptography, public key cryptography, digit serial multiplier, Bit serial multiplier
2	Mustafa Gök, Michael J. Schulte, Mark G. Arnold	Integer Multipliers with Overflow Detection.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	high-speed arithmetic algorithms, overflow detection, Computer arithmetic, multiplication, combinational logic
2	José Luis Imaña, Juan Manuel Sánchez, Francisco Tirado	Bit-Parallel Finite Field Multipliers for Irreducible Trinomials.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Finite (or Galois) fields, canonical basis, triangular basis, complexity, permutation, multiplication, cycles, matrix decomposition, transpositions, irreducible trinomials
2	José Luis Imaña, Román Hermida, Francisco Tirado	Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert	Toward architecture-based test-vector generation for timing verification of fast parallel multipliers.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	José Luis Imaña, Juan Manuel Sánchez	Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields GF(2m) Generated by AOPs.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	Galois field GF(2m), canonical basis, reconfigurable hardware, normal basis, bit-parallel multiplier
2	Samir Hamaci, Jean-Louis Boimond, Sébastien Lahaye	Modeling and Control of Hybrid Timed Event Graphs with Multipliers Using (Min, +) Algebra.	Discrete Event Dynamic Systems	2006	DBLP DOI BibTeX RDF	Hybrid timed event graph, (min, +) algebra, Just-in-time control
2	Yoo-Jin Baek, Mi-Jung Noh	DPA-Resistant Finite Field Multipliers and Secure AES Design.	ISPEC	2006	DBLP DOI BibTeX RDF
2	Martin Novotný, Jan Schmidt	General Digit Width Normal Basis Multipliers with Circular and Linear Structure.	FPL	2006	DBLP DOI BibTeX RDF
2	Yen-Chin Liao, Hsie-Chia Chang, Chih-Wei Liu	Carry Estimation for Two's Complement Fixed-Width Multipliers.	SiPS	2006	DBLP DOI BibTeX RDF
2	Mohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi	ByZFAD: a low switching activity architecture for shift-and-add multipliers.	SBCCI	2006	DBLP DOI BibTeX RDF	adder bypass, byZFAD, hot-block ring counter, shiftand-add multiplier, low-power, switching activity
2	Nima Honarmand, Ali Afzali-Kusha	Low Power Combinational Multipliers using Data-driven Signal Gating.	APCCAS	2006	DBLP DOI BibTeX RDF
2	Hayssam El-Razouk, Zine Abid	Area and Power Efficient Array and Tree Multipliers.	CCECE	2006	DBLP DOI BibTeX RDF
2	George Economakos, K. Anagnostopoulos	Bit level architectural exploration technique for the design of low power multipliers.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Magnus Karlsson, Mark Vesterbacka	Digit-serial/parallel multipliers with improved throughput and latency.	ISCAS	2006	DBLP DOI BibTeX RDF
2	P. Bougas, A. Tsirikos, K. Anagnostopoulos, Isidoros Sideris, Kiamal Z. Pekmestzi	Segmentation based design of serial parallel multipliers.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Jinyao Zhang, Miodrag Vujkovic, David Wadkins, Carl Sechen	Post-layout energy-delay analysis of parallel multipliers.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Zih-Heng Chen, Ming-Haw Jing, Jian-Hong Chen, Yaotsu Chang	New viewpoint of bit-serial/parallel normal basis multipliers using irreducible all-one polynomial.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Gordana Jovanovic-Dolecek, M. A. Perez-Xochicale	One Method for Design of Wide-band FIR Filters Without Multipliers.	CONIELECOMP	2006	DBLP DOI BibTeX RDF
2	Chiou-Yng Lee, Jenn-Shyong Horng, I-Chang Jou, Erl-Huei Lu	Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2m).	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	irreducible AOP, finite field, montgomery multiplication, irreducible trinomial, Bit-parallel systolic multiplier
2	Arash Reyhani-Masoleh, M. Anwar Hasan	Low Complexity Word-Level Sequential Normal Basis Multipliers.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Finite field, optimal normal basis, Massey-Omura multiplier
2	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Built-in sequential fault self-testing of array multipliers.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
2	Soonhak Kwon, Taekyoung Kwon, Young-Ho Park	New Architecture for Multiplication in GF(2m) and Comparisons with Normal and Polynomial Basis Multipliers for Elliptic Curve Cryptography.	ICISC	2005	DBLP DOI BibTeX RDF	linear multiplier, NIST recommended binary fields, elliptic curve cryptography
2	Ravi Kumar Satzoda, Chip-Hong Chang	VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
2	Masahiro Iwahashi, Dang Khoa Dang, Masahiro Ohnishi, Somchart Chokchaitam	A new structure of integer DCT least sensitive to finite word length expression of multipliers.	ICIP	2005	DBLP DOI BibTeX RDF
2	Kyle Kelley, David Harris	Very High Radix Scalable Montgomery Multipliers.	IWSOC	2005	DBLP DOI BibTeX RDF