Search results for "multiprocessor architecture"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Christian Schäck, Wolfgang Heenes, Rolf Hoffmann	A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA.	SAMOS	2009	DBLP DOI BibTeX RDF	Global Cellular Automata, FPGA, multiprocessor architecture, omega network
3	Martijn J. Rutten, Jos T. J. van Eijndhoven, Evert-Jan D. Pol, Egbert G. T. Jaspers, Pieter van der Wolf, Om Prakash Gangwal, Adwin H. Timmer	Eclipse: Heterogeneous Multiprocessor Architecture for Flexible Media Processing. (PDF / PS)	IPDPS	2002	DBLP DOI BibTeX RDF	high-performance media processing, heterogeneous multiprocessor architecture, Scalability, synchronization
2	Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Takafumi Yuasa, Toru Fujihira, Kenichi Iwata, Motoki Kimura, Fumitaka Izuhara, Seiji Mochizuki, Masaki Nobori	Development of full-HD multi-standard video CODEC IP based on heterogeneous multiprocessor architecture.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Jörg-Christian Niemann, Christoph Puttmann, Mario Porrmann, Ulrich Rückert	GigaNetIC - A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications.	ARCS	2006	DBLP DOI BibTeX RDF
2	Li Yang, Lu Peng	SecCMP: a secure chip-multiprocessor architecture.	ASID	2006	DBLP DOI BibTeX RDF	security, fault-tolerance, encryption, chip-multiprocessor
2	Raphael Fonte Boa, Dulcinéia Oliveira da Penha, Alexandre Marques Amaral, Márcio Oliveira Soares de Souza, Carlos Augusto Paiva da Silva Martins, Petr Yakovlevitch Ekel	RCMP: A Reconfigurable Chip-Multiprocessor Architecture.	ISPA Workshops	2006	DBLP DOI BibTeX RDF
2	Wolfgang Heenes, Rolf Hoffmann, Johannes Jendrsczok	A multiprocessor architecture for the massively parallel model GCA.	IPDPS	2006	DBLP DOI BibTeX RDF
2	Jing Chen, Jian-Horng Liu	Developing Embedded Kernel for System-On-a-Chip Platform of Heterogeneous Multiprocessor Architecture.	RTCSA	2006	DBLP DOI BibTeX RDF
2	Nikolay Kavaldjiev, Gerard J. M. Smit, Pierre G. Jansen	Throughput of Streaming Applications Running on a Multiprocessor Architecture.	DSD	2005	DBLP DOI BibTeX RDF
2	Alessio Bechini, Pierfrancesco Foglia, Cosimo Antonio Prete	Fine-grain design space exploration for a cartographic SoC multiprocessor.	SIGARCH Computer Architecture News	2003	DBLP DOI BibTeX RDF	SoC Multiprocessors, performance evaluation, embedded systems, trace-driven simulation, multiprocessor architecture
2	Chouki Aktouf	A Complete Strategy for Testing an On-Chip Multiprocessor Architecture.	IEEE Design & Test of Computers	2002	DBLP DOI BibTeX RDF
2	Syed Saif Abrar	High Performance Multiprocessor Architecture Design Methodology for Application-Specific Embedded Systems.	HiPC	2002	DBLP DOI BibTeX RDF
2	Diana Hecht, Constantine Katsinis	Protocols for Fault-Tolerant Distributed-Shared-Memory on the SOME-Bus Multiprocessor Architecture. (PDF / PS)	IPDPS	2002	DBLP DOI BibTeX RDF
2	Hubert Garavel, César Viho, Massimo Zendri	System design of a CC-NUMA multiprocessor architecture using formal specification, model-checking, co-simulation, and test generation.	STTT	2001	DBLP DOI BibTeX RDF	Verification, Formal specification, Testing, Formal methods, Validation, Code generation, Computer architecture, Test generation, Rapid prototyping, Process algebra, Conformance testing, Cache coherency, System level design, Co-design, lotos, Hardware design, Co-simulation, numa, cc-numa
2	J. Robert Heath, Andrew Tan	Modeling, Design, Virtual and Physical Prototyping, Testing, and Verification of a Multifunctional Processor Queue for a Single-Chip Multiprocessor Architecture.	IEEE International Workshop on Rapid System Prototyping	2001	DBLP DOI BibTeX RDF	Real-time reconfigurable architecture, analytic functional modeling, real-time testing and functional/performance verification, design, FPGA prototyping
2	Sophie Bonneau, Abdelkader Hameurlain	Database Program Mapping onto a Shared-Nothing Multiprocessor Architecture: Minimizing Communication Costs.	Euro-Par	1997	DBLP DOI BibTeX RDF
2	John Heinlein, Kourosh Gharachorloo, Robert P. Bosch Jr., Mendel Rosenblum, Anoop Gupta	Coherent Block Data Transfer in the FLASH Multiprocessor. (PDF / PS)	IPPS	1997	DBLP DOI BibTeX RDF	FLASH multiprocessor, block data transfer, multiple communication protocols, embedded protocol processor, protocol, shared memory, prefetching, cache storage, FLASH, cache coherence protocol, multiprocessor architecture, MAGIC
2	Rong-Yuh Hwang	An Efficient Technique of Instruction Scheduling on a Superscalar-Based Mulprocessor. (PDF / PS)	IPPS	1997	DBLP DOI BibTeX RDF	FLASH multiprocessor, block data transfer, multiple communication protocols, embedded protocol processor, protocol, shared memory, prefetching, cache storage, FLASH, cache coherence protocol, multiprocessor architecture, MAGIC
2	Stefan Ronngren, Behrooz Shirazi	Static multiprocessor scheduling of periodic real-time tasks with precedence constraints and communication costs.	HICSS	1995	DBLP DOI BibTeX RDF	static multiprocessor scheduling, periodic real-time tasks, large task sets, exclusion relation, heuristic scheduling algorithms, clustering, real-time systems, resource allocation, NP-complete, multiprocessing systems, communication complexity, mutual exclusion, processor scheduling, timing constraints, task allocation, communication costs, precedence constraints, multiprocessor architecture, precedence relations, scheduling methods
2	Raja Neogi, Meghanad D. Wagh	Parallel processing algorithms and architecture for multimedia on-demand servers. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	parallel processing algorithms, parallel processing architecture, multimedia on-demand servers, videotape rental stores, specialized high performance programmable multiprocessor architecture, continuous playback, mediastreams, dynamic phase shifts, media distribution, maximum concurrency extraction, dynamically changing demand, parallel algorithms, networking, parallel architectures, multimedia communication, multimedia computing, distributed environment, interactive video
2	Jos Huisken, A. Delaruelle, B. Egberts, P. Eeckhout, Jef L. van Meerbergen	Synthesis of synchronous communication hardware in a multiprocessor architecture.	VLSI Signal Processing	1993	DBLP DOI BibTeX RDF
2	Alok N. Choudhary, Janak H. Patel, Narendra Ahuja	NETRA: A Hierarchical and Partitionable Architecture for Computer Vision Systems.	IEEE Trans. Parallel Distrib. Syst.	1993	DBLP DOI BibTeX RDF	NETRA, partitionable architecture, tree-type control hierarchy, broadcast capability, block-level control, memorymanagement, scheduling, performance, computer vision, computer vision, load balancing, topology, SIMD, data flow, MIMD, multiprocessor architecture, CVS, hierarchical architecture, parallelarchitectures, Systolic, flexible architecture
2	Hong Jiang, Kenneth C. Smith	PPMB: A Partial-Multiple-Bus Multiprocessor Architecture with Improved Cost-Effectiveness.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	PPMB, partial-multiple-bus multiprocessor architecture, processor-oriented partial-multiple-bus, memory-oriented partial-multiple-bus, system bandwidth, simulation, performance evaluation, design, performance analysis, interconnection networks, computer architecture, multiprocessor interconnection networks, cost-effectiveness, arbitration
2	Hee Yong Youn	An Efficient Multiprocessor Architecture for Image Processing in VLSI.	ICCI	1991	DBLP DOI BibTeX RDF
2	Jean-Luc Gaudiot, Andrew Sohn	Data-Driven Parallel Production Systems.	IEEE Trans. Software Eng.	1990	DBLP DOI BibTeX RDF	parallel production systems, data-flow principles, high programmability, data-driven principles, RETE match algorithm, actor set, program graph design, tagged data-flow computer, deterministic simulation, artificial intelligence production systems, parallel programming, parallel architectures, expert systems, symbolic computations, symbol manipulation, multiprocessor architecture, numerical computations, multiprocessor environment, data-driven architectures
2	Per Brinch Hansen	Multiprocessor Architectures For Concurrent Programs.	ACM Annual Conference	1978	DBLP DOI BibTeX RDF	Hierarchical stores, Language-directed computer design, Monitors, Processes, Concurrent programming, Real-time applications, Multiprocessor architecture
1	Pascal Cotret, Jérémie Crenne, Guy Gogniat, Jean-Philippe Diguet, Lubos Gaspar, Guillaume Duc	Distributed Security for Communications and Memories in a Multiprocessor Architecture.	IPDPS Workshops	2011	DBLP DOI BibTeX RDF
1	Long Zheng, Yanchao Lu, Jingyu Zhou, Minyi Guo, Hai Jin, Song Guo, Yao Shen, Jiehan Zhou, Jukka Riekki	A Scalable Multiprocessor Architecture for Pervasive Computing.	GPC	2011	DBLP DOI BibTeX RDF
1	Fei Guo, Yan Solihin, Li Zhao, Ravishankar Iyer	Quality of service shared cache management in chip multiprocessor architecture.	TACO	2010	DBLP DOI BibTeX RDF
1	Cigdem Inan Aci, Mehmet Fatih Akay	A new congestion control algorithm for improving the performance of a broadcast-based multiprocessor architecture.	J. Parallel Distrib. Comput.	2010	DBLP DOI BibTeX RDF
1	Kunle Olukotun	Chip multiprocessor architecture: A programmability-driven approach.	IPDPS	2010	DBLP DOI BibTeX RDF
1	Antonino Tumeo, Francesco Regazzoni, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto	A reconfigurable multiprocessor architecture for a reliable face recognition implementation.	DATE	2010	DBLP BibTeX RDF
1	Giovanny Sánchez, Jordi Madrenas, Juan Manuel Moreno	Performance Evaluation and Scaling of a Multiprocessor Architecture Emulating Complex SNN Algorithms.	ICES	2010	DBLP DOI BibTeX RDF
1	Simone Pellegrini, Thomas Fahringer, Herbert Jordan, Hans Moritsch	Automatic tuning of MPI runtime parameter settings by using machine learning.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	mpi runtime parameters, machine learning, tuning
1	Jehangir Khan, Smaïl Niar, Mazen A. R. Saghir, Yassin Elhillali, Atika Rivenq-Menhaj	Trade-Off Exploration for Target Tracking Application in a Customized Multiprocessor Architecture.	EURASIP J. Emb. Sys.	2009	DBLP DOI BibTeX RDF
1	Marius Gligor, Nicolas Fournel, Frédéric Pétrot	Adaptive Dynamic Voltage and Frequency Scaling Algorithm for Symmetric Multiprocessor Architecture.	DSD	2009	DBLP DOI BibTeX RDF
1	J. Robert Heath, Sridhar Hegde, Kanchan Bhide	Development and Validation of a Load Balancing and Control Mechanism for a Reconfigurable Single-Chip Heterogenous and Hybrid Multiprocessor Architecture Platform.	ISCA PDCCS	2009	DBLP BibTeX RDF
1	Jason Wu, John W. Williams, Neil W. Bergmann, Peter Sutton	Design Exploration for FPGA-Based Multiprocessor Architecture: JPEG Encoding Case Study.	FCCM	2009	DBLP DOI BibTeX RDF	FPGA, MPSoC, JPEG
1	Sudipto Das, Shyam Antony, Divyakant Agrawal, Amr El Abbadi	CoTS: A Scalable Framework for Parallelizing Frequency Counting over Data Streams.	ICDE	2009	DBLP DOI BibTeX RDF
1	Antonino Tumeo, Simone Borgio, Davide Bosisio, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto	A multiprocessor self-reconfigurable JPEG2000 encoder.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Julio Merino, Lluc Alvarez, Marisa Gil, Nacho Navarro	Cetra: A trace and analysis framework for the evaluation of Cell BE systems.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Slo-Li Chu, Chih-Chieh Hsiao, Pin-Hua Chiu	Design a Hardware Mechanism to Utilize Multiprocessors on a Uni-processor Operating System.	ICA3PP	2009	DBLP DOI BibTeX RDF	Xilinx ML310, FPGA, Linux, Multi-core, Inter-Processor Communication
1	Jonatha Anselmi, Bruno Gaujal	Performance Evaluation of Work Stealing for Streaming Applications.	OPODIS	2009	DBLP DOI BibTeX RDF	Performance Evaluation, Markov Model, Work Stealing
1	Ritesh Rajore, Ganesh Garga, H. S. Jamadagni, S. K. Nandy	Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture.	ASAP	2008	DBLP DOI BibTeX RDF
1	Jun Zhang, Xiao-Ya Fan, Song-He Liu	A Pollution Alleviative L2 Cache Replacement Policy for Chip Multiprocessor Architecture.	NAS	2008	DBLP DOI BibTeX RDF
1	Jude Angelo Ambrose, Sri Parameswaran, Aleksandar Ignjatovic	MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Haris Javaid, Sri Parameswaran	Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	design space exploration, integer linear programming, MPSoCs
1	Alex Vrenios	McGAT: multicomputer granularity assessment tool.	Mardi Gras Conference	2008	DBLP DOI BibTeX RDF
1	Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev	A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	hardware space exploration, embedded system design, Multiprocessor system-on-chip, real time analysis, electrocardiogram algorithms
1	Jehangir Khan, Smaïl Niar, Atika Rivenq, Yassin Elhillali, Jean-Luc Dekeyser	An MPSoC architecture for the Multiple Target Tracking application in driver assistant system.	ASAP	2008	DBLP DOI BibTeX RDF
1	Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto	Lightweight DMA management mechanisms for multiprocessors on FPGA.	ASAP	2008	DBLP DOI BibTeX RDF
1	Madhura Purnaprajna, Christoph Puttmann, Mario Porrmann	Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography.	DATE	2008	DBLP DOI BibTeX RDF
1	Like Yan, Qingsong Shi, Tianzhou Chen, Guobing Chen	An On-chip Communication Mechanism Design in the Embedded Heterogeneous Multi-core Architecture.	ICNSC	2008	DBLP DOI BibTeX RDF
1	Karthik Ganesan, Lizy Kurian John, Valentina Salapura, James C. Sexton	A Performance Counter Based Workload Characterization on Blue Gene/P.	ICPP	2008	DBLP DOI BibTeX RDF
1	Jizhu Lu, Michael Perrone, Kursad Albayraktaroglu, Manoj Franklin	HMMer-Cell: High Performance Protein Profile Searching on the Cell/B.E. Processor.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Julien Bernard, Jean-Louis Roch, Daouda Traoré	Processor-Oblivious Parallel Stream Computations.	PDP	2008	DBLP DOI BibTeX RDF	processor-oblivious parallel stream work-stealing
1	Christof Pitter, Martin Schoeberl	Performance evaluation of a java chip-multiprocessor.	SIES	2008	DBLP DOI BibTeX RDF
1	David L. Andrews, Ron Sass, Erik K. Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp	Achieving Programming Model Abstractions for Reconfigurable Computing.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Julien Castet, Jean-Loup Florens	A Virtual Reality Simulator Based on Haptic Hard Constraints.	EuroHaptics	2008	DBLP DOI BibTeX RDF	Multi Frequency, Mass Interaction, Virtual-Reality, Real Time, Synchronisation, Instrumental, Multi Processor
1	Jörg-Christian Niemann, Christoph Puttmann, Mario Porrmann, Ulrich Rückert	Resource efficiency of the GigaNetIC chip multiprocessor architecture.	Journal of Systems Architecture	2007	DBLP DOI BibTeX RDF
1	Kunle Olukotun, Lance Hammond, James Laudon	iChip Multiprocessor Architecture: Techniques to Improve Throughput and Latency		2007	DOI RDF
1	Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez	A Reconfigurable Chip Multiprocessor Architecture to Accommodate Software Diversity.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Slo-Li Chu	Toward to Utilize the Heterogeneous Multiple Processors of the Chip Multiprocessor Architecture.	EUC	2007	DBLP DOI BibTeX RDF	Swing Scheduling, Octans, Chip Multiprocessor (CMP), Processor-in-Memory
1	Slo-Li Chu	Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture.	LCPC	2007	DBLP DOI BibTeX RDF	Critical Block Scheduling, Octans, Chip Multiprocessor (CMP), Processor-in-Memory
1	Brian D. Carlstrom, Austen McDonald, Michael Carbin, Christos Kozyrakis, Kunle Olukotun	Transactional collection classes.	PPOPP	2007	DBLP DOI BibTeX RDF	collection classes, Java, transactional memory, multiprocessor architecture
1	Dhiraj D. Kalamkar, Mainak Chaudhuri, Mark Heinrich	Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads.	ISPASS	2007	DBLP DOI BibTeX RDF	active memory cluster, directory protocol thread, active memory address remapping, parallel reduction, coherence protocol extension, software protocol, multi-threaded node, dual-core node, active memory architecture, distributed shared memory, multiprocessor architecture, memory controller, matrix transpose
1	Sjoerd Meijer, Bart Kienhuis, Alexandru Turjan, Erwin A. de Kock	Interactive presentation: A process splitting transformation for Kahn process networks.	DATE	2007	DBLP DOI BibTeX RDF
1	Jason Cong, Guoling Han, Wei Jiang	Synthesis of an application-specific soft multiprocessor system.	FPGA	2007	DBLP DOI BibTeX RDF	clustering, multiprocessor, pipeline, labeling, design space
1	Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith	Configurable isolation: building high availability systems with commodity multi-core processors.	ISCA	2007	DBLP DOI BibTeX RDF	chip multiprocessors, high availability, fault isolation
1	Awni Itradat, M. Omair Ahmad, Ali Shatnawi	Architectural Synthesis of DSP Applications with Dynamically Reconfigurable Functional Units.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Muhammet Fikret Ercan	Parallel Image Understanding on a Multi-DSP System.	ICCSA	2007	DBLP DOI BibTeX RDF
1	Sajib Barua, Reda Alhajj	Parallel Wavelet Transform for Spatio-temporal Outlier Detection in Large Meteorological Data.	IDEAL	2007	DBLP DOI BibTeX RDF
1	Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari	HiDRA - A reactive multiprocessor architecture for heterogeneous embedded systems.	Microprocessors and Microsystems	2006	DBLP DOI BibTeX RDF
1	Abdennour El Rhalibi, Madjid Merabti, Yuanyuan Shen	Improving Game Processing in Multithreading and Multiprocessor Architecture.	Edutainment	2006	DBLP DOI BibTeX RDF
1	Brian D. Carlstrom, Austen McDonald, Hassan Chafi, JaeWoong Chung, Chi Cao Minh, Christoforos E. Kozyrakis, Kunle Olukotun	The Atomos transactional programming language.	PLDI	2006	DBLP DOI BibTeX RDF	conditional synchronization, java, transactional memory, multiprocessor architecture
1	Olivier Muller, Amer Baghdadi, Michel Jézéquel	ASIP-based multiprocessor SoC design for simple and double binary turbo decoding.	DATE	2006	DBLP DOI BibTeX RDF
1	Lisa Higham, LillAnne Jackson	Translating between itanium and sparc memory consistency models.	SPAA	2006	DBLP DOI BibTeX RDF	multiprocessors, program transformations, memory consistency models, sparc, itanium
1	Byung-Joo Hong, Koon-Shik Cho, Seung-Hyun Kang, Suk-Yoon Lee, Jun Dong Cho	On the Configurable Multiprocessor SoC Platform with Crossbar Switch.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya	QOS Driven Network-on-Chip Design for Real Time Systems.	CCECE	2006	DBLP DOI BibTeX RDF
1	Erik K. Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp, Ron Sass, David L. Andrews	Enabling a Uniform Programming Model Across the Software/Hardware Boundary.	FCCM	2006	DBLP DOI BibTeX RDF
1	Samarjit Chakraborty, Yanhong Liu, Nikolay Stoimenov, Lothar Thiele, Ernesto Wandeler	Interface-Based Rate Analysis of Embedded Systems.	RTSS	2006	DBLP DOI BibTeX RDF
1	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Application-specific heterogeneous multiprocessor synthesis using extensible processors.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Kyriakos Stavrou, Pedro Trancoso, Paraskevas Evripidou	Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
1	Juan Chen, Huizhan Yi, Xuejun Yang, Liang Qian	Compile-Time Energy Optimization for Parallel Applications in On-Chip Multiprocessors.	International Conference on Computational Science	2006	DBLP DOI BibTeX RDF
1	Suleyman Tosun, Nazanin Mansouri, Mahmut T. Kandemir, Ozcan Ozturk	An ILP Formulation for Task Scheduling on Heterogeneous Chip Multiprocessors.	ISCIS	2006	DBLP DOI BibTeX RDF	Reliability, DVS, energy minimization, duplication, heterogeneous chip multiprocessors
1	Pengyong Ma, Xiao Hu, Shuming Chen, Yang Guo	Pseudo Share Data Cache in Multiprocessor: PSDMP.	ISPA Workshops	2006	DBLP DOI BibTeX RDF
1	Lisa Higham, LillAnne Jackson, Jalal Kawash	Capturing Register and Control Dependence in Memory Consistency Models with Applications to the Itanium Architecture.	DISC	2006	DBLP DOI BibTeX RDF	Multiprocessor memory consistency, register and control dependency, process coordination, Itanium
1	Magnus Ekman, Per Stenström	Enhancing Multiprocessor Architecture Simulation Speed Using Matched-Pair Comparison.	ISPASS	2005	DBLP DOI BibTeX RDF
1	Francisco J. Villa, Manuel E. Acacio, José M. García	Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture.	HPCC	2005	DBLP DOI BibTeX RDF
1	Abdennour El Rhalibi, Steve Costa, David England	Game Engineering for a Multiprocessor Architecture.	DIGRA Conf.	2005	DBLP BibTeX RDF
1	Khaled Z. Ibrahim	Correlation between Detailed and Simplified Simulations in Studying Multiprocessor Architecture.	ICCD	2005	DBLP DOI BibTeX RDF
1	Li Zhao, Yan Luo, Laxmi N. Bhuyan, Ravi R. Iyer	SpliceNP: a TCP splicer using a network processor.	ANCS	2005	DBLP DOI BibTeX RDF	TCP splicing, network processors
1	Mahmut T. Kandemir, Guangyu Chen, Feihui Li, I. Demirkiran	Using data replication to reduce communication energy on chip multiprocessors.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Patrick Schaumont, Bo-Cheng Charles Lai, Wei Qin, Ingrid Verbauwhede	Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design.	DAC	2005	DBLP DOI BibTeX RDF
1	Chuan-Yue Yang, Jian-Jia Chen, Tei-Wei Kuo	An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor.	DATE	2005	DBLP DOI BibTeX RDF
1	Armando Ferro, Igor Delgado, Alejandro Muñoz, Fidel Liberal	An Analytical Model for Performance Evaluation of Network Traffic Analysis Systems.	ICPADS	2005	DBLP DOI BibTeX RDF
1	Shiann-Rong Kuang, Chin-Yang Chen, Ren-Zheng Liao	Partitioning and Pipelined Scheduling of Embedded System Using Integer Linear Programming.	ICPADS	2005	DBLP DOI BibTeX RDF
1	Vassilios A. Chouliaras, Tom R. Jacobs, Ashwin K. Kumaraswamy, José L. Núñez-Yáñez	Configurable Multiprocessors for High-Performance MPEG-4 Video Coding.	ISVLSI	2005	DBLP DOI BibTeX RDF
1	S. Govind, R. Govindarajan	Performance Modeling and Architecture Exploration of Network Processors.	QEST	2005	DBLP DOI BibTeX RDF
1	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors.	VLSI Design	2005	DBLP DOI BibTeX RDF