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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6 occurrences of 6 keywords
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Results
Found 6 publication records. Showing 6 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 3 | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh |
Low power realization of FIR filters using multirate architectures.  |
VLSI Design  |
1996 |
DBLP DOI BibTeX RDF |
low power realization, multirate architectures, computationally efficient implementations, power dissipation reduction, dedicated ASIC implementation, TMS320C2x/C5x programmable DSP, computational complexity, computational complexity, application specific integrated circuits, power analysis, digital filters, FIR filters, FIR filters, digital signal processing chips |
| 1 | M. N. Mahesh, Mahesh Mehendale |
Improving performance of high precision signal processing algorithms on programmable DSPs. |
ISCAS |
1999 |
DBLP DOI BibTeX RDF |
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| 1 | An-Yeu Wu, K. J. Ray Liu |
Algorithm-based low-power transform coding architectures: the multirate approach. |
IEEE Trans. VLSI Syst. |
1998 |
DBLP DOI BibTeX RDF |
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| 1 | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh |
Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
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| 1 | Vikram M. Gadre, R. K. Patney |
Using multirate architectures in realizing quadratic Volterra kernels. |
IEEE Transactions on Signal Processing |
1996 |
DBLP DOI BibTeX RDF |
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| 1 | Vikram M. Gadre, R. K. Patney |
Some novel multirate architectures for filter realization with reduced multiplicative complexity. |
IEEE Transactions on Signal Processing |
1994 |
DBLP DOI BibTeX RDF |
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