Search results for "multithreaded processor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Winfried Grünewald, Theo Ungerer	Towards Extremely Fast Context Switching in a Block-Multithreaded Processor.	EUROMICRO	1996	DBLP DOI BibTeX RDF	extremely fast context switching, block-multithreaded processor, fast context switch, Rhamma, off-chip cache, workstation environment, memory cycle time, latencies, synchronisation, memory accesses, functional unit, synchronization operations
2	Emre Özer, Alastair Reid, Stuart Biles	Low-cost Techniques for Reducing Branch Context Pollution in a Soft Realtime Embedded Multithreaded Processor.	SBAC-PAD	2007	DBLP DOI BibTeX RDF
2	Sascha Uhrig, Jörg Wiese	jamuth: an IP processor core for embedded Java real-time systems.	JTRES	2007	DBLP DOI BibTeX RDF	Java execution environment, embedded system-on-a-chip implementation, virtual machine, real-time embedded system, multithreaded processor, Java processor, embedded operating system
2	Carsten Albrecht, Andreas C. Döring, Frank Penczek, Torben Schneider, Hannes Schulz	Impact of Coprocessors on a Multithreaded Processor Design Using Prioritized Threads.	PDP	2006	DBLP DOI BibTeX RDF
2	Shyamkumar Thoziyoor, Jay B. Brockman, Daniel Rinzler	PIM lite: a multithreaded processor-in-memory prototype.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	multithreading, VLSI design, processing-in-memory
2	Suman Mamidi, Emily R. Blem, Michael J. Schulte, C. John Glossner, Daniel Iancu, Andrei Iancu, Mayan Moudgill, Sanjay Jinturkar	Instruction set extensions for software defined radio on a multithreaded processor.	CASES	2005	DBLP DOI BibTeX RDF	convolutional encoding, multithreading, forward error correction, software defined radio, Reed-Solomon coding, instruction set extensions, digital signal processor, Viterbi decoding, turbo decoding
2	Sascha Uhrig, Theo Ungerer	Fine-grained power management for multithreaded processor cores.	SAC	2004	DBLP DOI BibTeX RDF	performance adaptation, power-aware program execution, power-management, multithreading
2	Ying Chen, Resit Sendag, David J. Lilja	Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor.	IPDPS	2003	DBLP DOI BibTeX RDF	superthreaded architecture, wrong-thread executioin, wrong-path execution, wrong execution cache (WEC), data prefetch, multithreaded processor
2	Juan C. Moure, R. B. García, Dolores Rexachs, Emilio Luque	Improving Single-Thread Fetch Performance on a Multithreaded Processor.	DSD	2001	DBLP DOI BibTeX RDF
2	Dominik Madon, Eduardo Sanchez, Stefan Monnier	A Study of a Simultaneous Multithreaded Processor Implementation.	Euro-Par	1999	DBLP DOI BibTeX RDF
2	Winfried Grünewald, Theo Ungerer	A Multithreaded Processor Designed for Distributed Shared Memory Systems.	APDC	1997	DBLP DOI BibTeX RDF
2	W. Lynn Gallagher, Chuan-lin Wu	Evaluation of a memory hierarchy for the MTS multithreaded processor. (PDF / PS)	ICPADS	1997	DBLP DOI BibTeX RDF	memory hierarchy evaluation, MTS multithreaded processor, hardware resource utilization, instruction throughput, multithreaded superscalar processor, multiple instruction streams, multiple functional unit architecture, parameter-driven simulator, SES/workbench, numerical benchmarks, memory system configurations, main memory latency, cache hit rates, realistic multilevel cache hierarchy, parallel processing, VLIW, superscalar processor, instruction cache
1	Charly Bechara, Aurelien Berhault, Nicolas Ventroux, Stéphane Chevobbe, Yves Lhuillier, Raphaël David, Daniel Etiemble	A small footprint interleaved multithreaded processor for embedded systems.	ICECS	2011	DBLP DOI BibTeX RDF
1	Eric S. Chung, James C. Hoe	High-Level Design and Validation of the BlueSPARC Multithreaded Processor.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Michael Bauer, Mathias Pacher, Uwe Brinkschulte	Chip-Size Evaluation of a Multithreaded Processor Enhanced with a PID Controller.	SEUS	2010	DBLP DOI BibTeX RDF
1	Fredrik Warg, Per Stenström	Dual-thread Speculation: A Simple Approach to Uncover Thread-level Parallelism on a Simultaneous Multithreaded Processor.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	Computer architecture, Chip multiprocessors, Thread-level speculation, Thread-level parallelism, Simultaneous multithreading
1	Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen, Hong Wang 0003, John Paul Shen	Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices.	IEEE Trans. Parallel Distrib. Syst.	2008	DBLP DOI BibTeX RDF	Speculative thread level parallelism, pre-computation slices, thread partitioning, multi-core architecture
1	Jeffery A. Brown, Dean M. Tullsen	The shared-thread multiprocessor.	ICS	2008	DBLP DOI BibTeX RDF	chip multiprocessors, simultaneous multithreading
1	Martin Labrecque, Peter Yiannacouras, J. Gregory Steffan	Scaling Soft Processor Systems.	FCCM	2008	DBLP DOI BibTeX RDF
1	Diana Bautista, Julio Sahuquillo, Houcine Hassan, Salvador Petit, José Duato	A simple power-aware scheduling for multicore systems when running real-time applications.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Zusong Li, Dandan Huan, Weiwu Hu, Zhimin Tang	Chip Multithreaded Consistency Model.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	Godson-2, computer architecture, multithreading, memory consistency model, event ordering
1	Chi Cao Minh, Martin Trautmann, JaeWoong Chung, Austen McDonald, Nathan Grasso Bronson, Jared Casper, Christos Kozyrakis, Kunle Olukotun	An effective hybrid transactional memory system with strong isolation guarantees.	ISCA	2007	DBLP DOI BibTeX RDF	strong isolation, parallel programming, transactional memory, multi-core architectures
1	Ron Gabor, Shlomo Weiss, Avi Mendelson	Fairness enforcement in switch on event multithreading.	TACO	2007	DBLP DOI BibTeX RDF	SOE, Switch on Event multithreading, coarse-grained multithreading, weighted speedup, performance, fairness, throughput, multithreading
1	Michael J. Schulte, John Glossner, Sanjay Jinturkar, Mayan Moudgill, Suman Mamidi, Stamatis Vassiliadis	A Low-Power Multithreaded Processor for Software Defined Radio.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	low power, wireless communication, computer architecture, multithreading, microarchitecture, Software Defined Radio, processor design
1	Sascha Uhrig, S. Maier, Georgi Kuzmanov, Theo Ungerer	Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo	Towards Reconfigurable Cache Memory for a Multithreaded Processor.	PDPTA	2006	DBLP BibTeX RDF
1	Shuo Wang, Lei Wang 0003	Thread-associative memory for multicore and multithreaded computing.	ISLPED	2006	DBLP DOI BibTeX RDF	cache mapping, multithreading, multicore, memory system
1	Bernhard Fechner	A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments.	PARELEC	2006	DBLP DOI BibTeX RDF
1	Shinpei Kato, Kazuya Kitsunai, Hidenori Kobayashi, Nobuyuki Yamasaki	Towards Real-Time Scheduling on Responsive Multithreaded Processor.	PDPTA	2005	DBLP BibTeX RDF
1	Tipp Moseley, Alex Shye, Vijay Janapa Reddi, Matthew Iyer, Dan Fay, David Hodgdon, Joshua L. Kihm, Alex Settle, Dirk Grunwald, Daniel A. Connors	Dynamic run-time architecture techniques for enabling continuous optimization.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	scheduling, profiling, multithreading, performance counters
1	J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, Todd C. Mowry	The STAMPede approach to thread-level speculation.	ACM Trans. Comput. Syst.	2005	DBLP DOI BibTeX RDF	cache coherence, automatic parallelization, Thread-level speculation, chip-multiprocessing
1	Weifeng Zhang, Brad Calder, Dean M. Tullsen	An Event-Driven Multithreaded Dynamic Optimization Framework.	IEEE PACT	2005	DBLP DOI BibTeX RDF
1	Joshua L. Kihm, Daniel A. Connors	Statistical Simulation of Multithreaded Architectures.	MASCOTS	2005	DBLP DOI BibTeX RDF
1	Bo Liang, Hong An, Fang Lu, Rui Guo	Improving Latency Tolerance of Network Processors Through Simultaneous Multithreading.	APPT	2005	DBLP DOI BibTeX RDF
1	Georgios Dimitriou, Constantine D. Polychronopoulos	Hardware Support for Multithreaded Execution of Loops with Limited Parallelism.	Panhellenic Conference on Informatics	2005	DBLP DOI BibTeX RDF
1	C. John Glossner, Sean Dorward, Sanjay Jinturkar, Mayan Moudgill, Erdem Hokenek, Michael J. Schulte, Stamatis Vassiliadis	Sandbridge Software Tools.	SAMOS	2005	DBLP DOI BibTeX RDF
1	Ronald N. Kalla, Balaram Sinharoy, Joel M. Tendler	IBM Power5 Chip: A Dual-Core Multithreaded Processor.	IEEE Micro	2004	DBLP DOI BibTeX RDF
1	Sanjiv Kapil, Harlan McGhan, Jesse Lawrendra	A Chip Multithreaded Processor for Network-Facing Workloads.	IEEE Micro	2004	DBLP DOI BibTeX RDF
1	Michael J. Schulte, C. John Glossner, Suman Mamidi, Mayan Moudgill, Stamatis Vassiliadis	A Low-Power Multithreaded Processor for Baseband Communication Systems.	SAMOS	2004	DBLP DOI BibTeX RDF
1	Tstomu Itou, Nobuyuki Yamasaki	The Instruction Execution Mechanism for Responsive Multithreaded Processor.	Computers and Their Applications	2004	DBLP BibTeX RDF
1	Mary Kiemb, Kiyoung Choi	Application-specific configuration of multithreaded processor architecture for embedded applications.	ISCAS	2004	DBLP BibTeX RDF
1	Xiaotong Zhuang, Santosh Pande	Balancing register allocation across threads for a multithreaded network processor.	PLDI	2004	DBLP DOI BibTeX RDF	register allocation, network processor, multithreaded processor
1	Ali El-Haj-Mahmoud, Eric Rotenberg	Safely exploiting multithreaded processors to tolerate memory latency in real-time systems.	CASES	2004	DBLP DOI BibTeX RDF	real-time systems, multithreading, worst-case execution time, memory latency, schedulability test
1	Jay B. Brockman, Shyamkumar Thoziyoor, Shannon K. Kuntz, Peter M. Kogge	A low cost, multithreaded processing-in-memory system.	WMPI	2004	DBLP DOI BibTeX RDF	PIM, processing-in-memory
1	Uwe Brinkschulte, Jürgen Becker, Theo Ungerer	CARUSO - An Approach Towards a Network of Low Power Autonomic Systems on Chips for Embedded Real-time Application.	IPDPS	2004	DBLP DOI BibTeX RDF
1	Matthias Pfeffer, Theo Ungerer, Stephan Fuhrmann, Jochen Kreuzinger, Uwe Brinkschulte	Real-Time Garbage Collection for a Multithreaded Java Microcontroller.	Real-Time Systems	2004	DBLP DOI BibTeX RDF	Java microprocessor, real-time, garbage collection, multithreading, microcontroller
1	Theo Ungerer, Borut Robic, Jurij Silc	A survey of processors with explicit multithreading.	ACM Comput. Surv.	2003	DBLP DOI BibTeX RDF	interleaved multithreading, simultaneous multithreading, Blocked multithreading
1	Steven Swanson, Luke McDowell, Michael M. Swift, Susan J. Eggers, Henry M. Levy	An evaluation of speculative instruction execution on simultaneous multithreaded processors.	ACM Trans. Comput. Syst.	2003	DBLP DOI BibTeX RDF	multiprocessors, multithreading, Instruction-level parallelism, speculation, thread-level parallelism, simultaneous multithreading
1	Thomas L. Sterling, Hans P. Zima	Gilgamesh: a multithreaded processor-in-memory architecture for petaflops computing.	SC	2002	DBLP DOI BibTeX RDF	Petaflops computing, data parallel processing, parallel architectures, Processor-In-Memory, irregular applications
1	Pedro Marcuello, Antonio González	Thread-Spawning Schemes for Speculative Multithreading.	HPCA	2002	DBLP DOI BibTeX RDF	Thread-spawning policies, Thread-level parallelism, Speculative multithreading
1	Mark N. Yankelevsky, Constantine D. Polychronopoulos	alpha-coral: a multigrain, multithreaded processor architecture.	ICS	2001	DBLP DOI BibTeX RDF	processor archietecture, multithreaded, parallelizing compiler
1	Harold W. Cain, Ravi Rajwar, Morris Marden, Mikko H. Lipasti	An Architectural Evaluation of Java TPC-W.	HPCA	2001	DBLP DOI BibTeX RDF
1	Joan-Manuel Parcerisa, Antonio González	Improving Latency Tolerance of Multithreading through Decoupling.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Access/execute decoupling, instruction-level parallelism, simultaneous multithreading, latency hiding, hardware complexity
1	Ulrich Sigmund, Theo Ungerer	Die Multimediafaehigkeit von mehrfaedig superskalaren Prozessoren am Beispiel der MPEG-2-Decodierung.	Inform., Forsch. Entwickl.	2001	DBLP BibTeX RDF	Mehrfädig superskalar, Superskalarprozessor, Multimediaprozessor, Multimediaeinheit, Videodecodierung, MPEG-2
1	Allan Snavely, Dean M. Tullsen	Symbiotic Jobscheduling for a Simultaneous Multithreading Processor.	ASPLOS	2000	DBLP DOI BibTeX RDF
1	Karthik Sundaramoorthy, Zachary Purser, Eric Rotenberg	Slipstream Processors: Improving both Performance and Fault Tolerance.	ASPLOS	2000	DBLP DOI BibTeX RDF
1	Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Baer, Brian N. Bershad	Characterizing processor architectures for programmable network interfaces.	ICS	2000	DBLP DOI BibTeX RDF
1	Jochen Kreuzinger, A. Schulz, Matthias Pfeffer, Theo Ungerer, Uwe Brinkschulte, C. Krakowski	Real-time scheduling on multithreaded processors.	RTCSA	2000	DBLP DOI BibTeX RDF	core processor, real-time events, interrupt service threads, interrupt service routines, zero-cycle context switching, fixed priority preemptive, least laxity first, embedded systems, real-time scheduling, processor scheduling, system-on-a-chip, multi-threading, earliest deadline first, multithreaded processors
1	Haitham Akkary, Sébastien Hily	The Case for Speculative Multithreading on SMT Processors.	ISHPC	2000	DBLP DOI BibTeX RDF
1	Mahamed Adda, Smaïl Niar, H. Bleuel, A. Lopez	A Simulator for a Multithreaded Processor.	Applied Informatics	1999	DBLP BibTeX RDF
1	Dean M. Tullsen, Jack L. Lo, Susan J. Eggers, Henry M. Levy	Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor.	HPCA	1999	DBLP DOI BibTeX RDF
1	Lucian Codrescu, D. Scott Wills	On Dynamic Speculative Thread Partitioning and the MEM-Slicing Algorithm.	IEEE PACT	1999	DBLP DOI BibTeX RDF	Thread Partitioning, Multiscalar, Thread Speculation, Speculative Multithreading, Dynamic Partitioning
1	Heiko Oehring, Ulrich Sigmund, Theo Ungerer	MPEG-2 Video Decompression on Simultaneous Multithreaded Multimedia Processors.	IEEE PACT	1999	DBLP DOI BibTeX RDF	MPEG-2 video decompression, Simultaneous multithreading, multimedia extension
1	Daniel Ortega, Ivan Martel, Venkata Krishnan, Eduard Ayguadé, Mateo Valero	Quantifying the Benefits of SPECint Distant Parallelism in Simultaneous Multi-Threading Architectures.	IEEE PACT	1999	DBLP DOI BibTeX RDF	distant parallelism, integer applications, multithreading
1	Jian Huang, David J. Lilja	An Efficient Strategy for Developing a Simulator for a Novel Concurrent Multithreaded Processor Architecture. (PDF / PS)	MASCOTS	1998	DBLP DOI BibTeX RDF
1	Jenn-Yuan Tsai, Zhenzhen Jiang, Eric Ness, Pen-Chung Yew	Performance Study of a Concurrent Multithreaded Processor.	HPCA	1998	DBLP DOI BibTeX RDF
1	C. John Glossner, Stamatis Vassiliadis	The Delft-Java Engine: An Introduction.	Euro-Par	1997	DBLP DOI BibTeX RDF
1	Alfred Mikschl, Werner Damm	MSparc: A Multithreaded Sparc.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF
1	Martin T. Rowland, Randall A. Helzerman	An Empirical Study of the Performance of a Simulated Multithreaded Processor.	Parallel and Distributed Computing and Systems	1995	DBLP BibTeX RDF
1	Pradeep K. Dubey, Arvind Krishna, Mark S. Squillante	Analytic Performance Modeling for a Spectrum of Multithreaded Processor Architectures.	MASCOTS	1995	DBLP BibTeX RDF
1	Dean M. Tullsen, Susan J. Eggers, Henry M. Levy	Simultaneous Multithreading: Maximizing On-Chip Parallelism.	ISCA	1995	DBLP DOI BibTeX RDF
1	C.-S. Chen, C.-C. Tseng	Integrated Support to Improve Inter-Thread Communication and Synchronization in a Multithreaded Processor.	ICPADS	1994	DBLP BibTeX RDF
1	Robert H. Halstead Jr., Tetsuya Fujita	MASA: A Multithreaded Processor Architecture for Parallel Symbolic Computing.	ISCA	1988	DBLP BibTeX RDF